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staging: usbip: bugfix for isochronous packets and optimization
[zen-stable.git] / drivers / media / dvb / frontends / stv0900_sw.c
blobba0709b2d4333a3d9811ceecb63e2142f11e361e
1 /*
2 * stv0900_sw.c
3 *
4 * Driver for ST STV0900 satellite demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include "stv0900.h"
27 #include "stv0900_reg.h"
28 #include "stv0900_priv.h"
29
30 s32 shiftx(s32 x, int demod, s32 shift)
31 {
32 if (demod == 1)
33 return x - shift;
34
35 return x;
36 }
37
38 int stv0900_check_signal_presence(struct stv0900_internal *intp,
39 enum fe_stv0900_demod_num demod)
40 {
41 s32 carr_offset,
42 agc2_integr,
43 max_carrier;
44
45 int no_signal = FALSE;
46
47 carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
48 | stv0900_read_reg(intp, CFR1);
49 carr_offset = ge2comp(carr_offset, 16);
50 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
51 | stv0900_read_reg(intp, AGC2I0);
52 max_carrier = intp->srch_range[demod] / 1000;
53
54 max_carrier += (max_carrier / 10);
55 max_carrier = 65536 * (max_carrier / 2);
56 max_carrier /= intp->mclk / 1000;
57 if (max_carrier > 0x4000)
58 max_carrier = 0x4000;
59
60 if ((agc2_integr > 0x2000)
61 || (carr_offset > (2 * max_carrier))
62 || (carr_offset < (-2 * max_carrier)))
63 no_signal = TRUE;
64
65 return no_signal;
66 }
67
68 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
69 s32 *frequency_inc, s32 *sw_timeout,
70 s32 *steps,
71 enum fe_stv0900_demod_num demod)
72 {
73 s32 timeout, freq_inc, max_steps, srate, max_carrier;
74
75 enum fe_stv0900_search_standard standard;
76
77 srate = intp->symbol_rate[demod];
78 max_carrier = intp->srch_range[demod] / 1000;
79 max_carrier += max_carrier / 10;
80 standard = intp->srch_standard[demod];
81
82 max_carrier = 65536 * (max_carrier / 2);
83 max_carrier /= intp->mclk / 1000;
84
85 if (max_carrier > 0x4000)
86 max_carrier = 0x4000;
87
88 freq_inc = srate;
89 freq_inc /= intp->mclk >> 10;
90 freq_inc = freq_inc << 6;
91
92 switch (standard) {
93 case STV0900_SEARCH_DVBS1:
94 case STV0900_SEARCH_DSS:
95 freq_inc *= 3;
96 timeout = 20;
97 break;
98 case STV0900_SEARCH_DVBS2:
99 freq_inc *= 4;
100 timeout = 25;
101 break;
102 case STV0900_AUTO_SEARCH:
103 default:
104 freq_inc *= 3;
105 timeout = 25;
106 break;
107 }
108
109 freq_inc /= 100;
110
111 if ((freq_inc > max_carrier) || (freq_inc < 0))
112 freq_inc = max_carrier / 2;
113
114 timeout *= 27500;
115
116 if (srate > 0)
117 timeout /= srate / 1000;
118
119 if ((timeout > 100) || (timeout < 0))
120 timeout = 100;
121
122 max_steps = (max_carrier / freq_inc) + 1;
123
124 if ((max_steps > 100) || (max_steps < 0)) {
125 max_steps = 100;
126 freq_inc = max_carrier / max_steps;
127 }
128
129 *frequency_inc = freq_inc;
130 *sw_timeout = timeout;
131 *steps = max_steps;
132
133 }
134
135 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
136 s32 FreqIncr, s32 Timeout, int zigzag,
137 s32 MaxStep, enum fe_stv0900_demod_num demod)
138 {
139 int no_signal,
140 lock = FALSE;
141 s32 stepCpt,
142 freqOffset,
143 max_carrier;
144
145 max_carrier = intp->srch_range[demod] / 1000;
146 max_carrier += (max_carrier / 10);
147
148 max_carrier = 65536 * (max_carrier / 2);
149 max_carrier /= intp->mclk / 1000;
150
151 if (max_carrier > 0x4000)
152 max_carrier = 0x4000;
153
154 if (zigzag == TRUE)
155 freqOffset = 0;
156 else
157 freqOffset = -max_carrier + FreqIncr;
158
159 stepCpt = 0;
160
161 do {
162 stv0900_write_reg(intp, DMDISTATE, 0x1c);
163 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
164 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
165 stv0900_write_reg(intp, DMDISTATE, 0x18);
166 stv0900_write_bits(intp, ALGOSWRST, 1);
167
168 if (intp->chip_id == 0x12) {
169 stv0900_write_bits(intp, RST_HWARE, 1);
170 stv0900_write_bits(intp, RST_HWARE, 0);
171 }
172
173 if (zigzag == TRUE) {
174 if (freqOffset >= 0)
175 freqOffset = -freqOffset - 2 * FreqIncr;
176 else
177 freqOffset = -freqOffset;
178 } else
179 freqOffset += + 2 * FreqIncr;
180
181 stepCpt++;
182 lock = stv0900_get_demod_lock(intp, demod, Timeout);
183 no_signal = stv0900_check_signal_presence(intp, demod);
184
185 } while ((lock == FALSE)
186 && (no_signal == FALSE)
187 && ((freqOffset - FreqIncr) < max_carrier)
188 && ((freqOffset + FreqIncr) > -max_carrier)
189 && (stepCpt < MaxStep));
190
191 stv0900_write_bits(intp, ALGOSWRST, 0);
192
193 return lock;
194 }
195
196 static int stv0900_sw_algo(struct stv0900_internal *intp,
197 enum fe_stv0900_demod_num demod)
198 {
199 int lock = FALSE,
200 no_signal,
201 zigzag;
202 s32 s2fw,
203 fqc_inc,
204 sft_stp_tout,
205 trial_cntr,
206 max_steps;
207
208 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
209 &max_steps, demod);
210 switch (intp->srch_standard[demod]) {
211 case STV0900_SEARCH_DVBS1:
212 case STV0900_SEARCH_DSS:
213 if (intp->chip_id >= 0x20)
214 stv0900_write_reg(intp, CARFREQ, 0x3b);
215 else
216 stv0900_write_reg(intp, CARFREQ, 0xef);
217
218 stv0900_write_reg(intp, DMDCFGMD, 0x49);
219 zigzag = FALSE;
220 break;
221 case STV0900_SEARCH_DVBS2:
222 if (intp->chip_id >= 0x20)
223 stv0900_write_reg(intp, CORRELABS, 0x79);
224 else
225 stv0900_write_reg(intp, CORRELABS, 0x68);
226
227 stv0900_write_reg(intp, DMDCFGMD, 0x89);
228
229 zigzag = TRUE;
230 break;
231 case STV0900_AUTO_SEARCH:
232 default:
233 if (intp->chip_id >= 0x20) {
234 stv0900_write_reg(intp, CARFREQ, 0x3b);
235 stv0900_write_reg(intp, CORRELABS, 0x79);
236 } else {
237 stv0900_write_reg(intp, CARFREQ, 0xef);
238 stv0900_write_reg(intp, CORRELABS, 0x68);
239 }
240
241 stv0900_write_reg(intp, DMDCFGMD, 0xc9);
242 zigzag = FALSE;
243 break;
244 }
245
246 trial_cntr = 0;
247 do {
248 lock = stv0900_search_carr_sw_loop(intp,
249 fqc_inc,
250 sft_stp_tout,
251 zigzag,
252 max_steps,
253 demod);
254 no_signal = stv0900_check_signal_presence(intp, demod);
255 trial_cntr++;
256 if ((lock == TRUE)
257 || (no_signal == TRUE)
258 || (trial_cntr == 2)) {
259
260 if (intp->chip_id >= 0x20) {
261 stv0900_write_reg(intp, CARFREQ, 0x49);
262 stv0900_write_reg(intp, CORRELABS, 0x9e);
263 } else {
264 stv0900_write_reg(intp, CARFREQ, 0xed);
265 stv0900_write_reg(intp, CORRELABS, 0x88);
266 }
267
268 if ((stv0900_get_bits(intp, HEADER_MODE) ==
269 STV0900_DVBS2_FOUND) &&
270 (lock == TRUE)) {
271 msleep(sft_stp_tout);
272 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
273
274 if (s2fw < 0xd) {
275 msleep(sft_stp_tout);
276 s2fw = stv0900_get_bits(intp,
277 FLYWHEEL_CPT);
278 }
279
280 if (s2fw < 0xd) {
281 lock = FALSE;
282
283 if (trial_cntr < 2) {
284 if (intp->chip_id >= 0x20)
285 stv0900_write_reg(intp,
286 CORRELABS,
287 0x79);
288 else
289 stv0900_write_reg(intp,
290 CORRELABS,
291 0x68);
292
293 stv0900_write_reg(intp,
294 DMDCFGMD,
295 0x89);
296 }
297 }
298 }
299 }
300
301 } while ((lock == FALSE)
302 && (trial_cntr < 2)
303 && (no_signal == FALSE));
304
305 return lock;
306 }
307
308 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
309 u32 mclk,
310 enum fe_stv0900_demod_num demod)
311 {
312 s32 rem1, rem2, intval1, intval2, srate;
313
314 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
315 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
316 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
317 (stv0900_get_bits(intp, SYMB_FREQ0));
318 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
319 srate, stv0900_get_bits(intp, SYMB_FREQ0),
320 stv0900_get_bits(intp, SYMB_FREQ1),
321 stv0900_get_bits(intp, SYMB_FREQ2),
322 stv0900_get_bits(intp, SYMB_FREQ3));
323
324 intval1 = (mclk) >> 16;
325 intval2 = (srate) >> 16;
326
327 rem1 = (mclk) % 0x10000;
328 rem2 = (srate) % 0x10000;
329 srate = (intval1 * intval2) +
330 ((intval1 * rem2) >> 16) +
331 ((intval2 * rem1) >> 16);
332
333 return srate;
334 }
335
336 static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
337 u32 mclk, u32 srate,
338 enum fe_stv0900_demod_num demod)
339 {
340 u32 symb;
341
342 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
343 srate, demod);
344
345 if (srate > 60000000) {
346 symb = srate << 4;
347 symb /= (mclk >> 12);
348 } else if (srate > 6000000) {
349 symb = srate << 6;
350 symb /= (mclk >> 10);
351 } else {
352 symb = srate << 9;
353 symb /= (mclk >> 7);
354 }
355
356 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
357 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
358 }
359
360 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
361 u32 mclk, u32 srate,
362 enum fe_stv0900_demod_num demod)
363 {
364 u32 symb;
365
366 srate = 105 * (srate / 100);
367
368 if (srate > 60000000) {
369 symb = srate << 4;
370 symb /= (mclk >> 12);
371 } else if (srate > 6000000) {
372 symb = srate << 6;
373 symb /= (mclk >> 10);
374 } else {
375 symb = srate << 9;
376 symb /= (mclk >> 7);
377 }
378
379 if (symb < 0x7fff) {
380 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
381 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
382 } else {
383 stv0900_write_reg(intp, SFRUP1, 0x7f);
384 stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
385 }
386 }
387
388 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
389 u32 mclk, u32 srate,
390 enum fe_stv0900_demod_num demod)
391 {
392 u32 symb;
393
394 srate = 95 * (srate / 100);
395 if (srate > 60000000) {
396 symb = srate << 4;
397 symb /= (mclk >> 12);
398
399 } else if (srate > 6000000) {
400 symb = srate << 6;
401 symb /= (mclk >> 10);
402
403 } else {
404 symb = srate << 9;
405 symb /= (mclk >> 7);
406 }
407
408 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
409 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
410 }
411
412 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
413 u32 srate,
414 enum fe_stv0900_demod_num demod)
415 {
416 s32 timingoffset;
417
418
419 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
420 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
421 (stv0900_read_reg(intp, TMGREG2 + 2));
422
423 timingoffset = ge2comp(timingoffset, 24);
424
425
426 if (timingoffset == 0)
427 timingoffset = 1;
428
429 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
430 timingoffset /= 320;
431
432 return timingoffset;
433 }
434
435 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
436 enum fe_stv0900_demod_num demod)
437 {
438 s32 rolloff;
439
440 if (intp->chip_id == 0x10) {
441 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
442 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
443 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
444 } else if (intp->chip_id <= 0x20)
445 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
446 else /* cut 3.0 */
447 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
448 }
449
450 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
451 {
452 u32 rolloff;
453
454 switch (ro) {
455 case STV0900_20:
456 rolloff = 20;
457 break;
458 case STV0900_25:
459 rolloff = 25;
460 break;
461 case STV0900_35:
462 default:
463 rolloff = 35;
464 break;
465 }
466
467 return srate + (srate * rolloff) / 100;
468 }
469
470 static int stv0900_check_timing_lock(struct stv0900_internal *intp,
471 enum fe_stv0900_demod_num demod)
472 {
473 int timingLock = FALSE;
474 s32 i,
475 timingcpt = 0;
476 u8 car_freq,
477 tmg_th_high,
478 tmg_th_low;
479
480 car_freq = stv0900_read_reg(intp, CARFREQ);
481 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
482 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
483 stv0900_write_reg(intp, TMGTHRISE, 0x20);
484 stv0900_write_reg(intp, TMGTHFALL, 0x0);
485 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
486 stv0900_write_reg(intp, RTC, 0x80);
487 stv0900_write_reg(intp, RTCS2, 0x40);
488 stv0900_write_reg(intp, CARFREQ, 0x0);
489 stv0900_write_reg(intp, CFRINIT1, 0x0);
490 stv0900_write_reg(intp, CFRINIT0, 0x0);
491 stv0900_write_reg(intp, AGC2REF, 0x65);
492 stv0900_write_reg(intp, DMDISTATE, 0x18);
493 msleep(7);
494
495 for (i = 0; i < 10; i++) {
496 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
497 timingcpt++;
498
499 msleep(1);
500 }
501
502 if (timingcpt >= 3)
503 timingLock = TRUE;
504
505 stv0900_write_reg(intp, AGC2REF, 0x38);
506 stv0900_write_reg(intp, RTC, 0x88);
507 stv0900_write_reg(intp, RTCS2, 0x68);
508 stv0900_write_reg(intp, CARFREQ, car_freq);
509 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
510 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
511
512 return timingLock;
513 }
514
515 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
516 s32 demod_timeout)
517 {
518 struct stv0900_state *state = fe->demodulator_priv;
519 struct stv0900_internal *intp = state->internal;
520 enum fe_stv0900_demod_num demod = state->demod;
521 int lock = FALSE,
522 d = demod;
523 s32 srate,
524 search_range,
525 locktimeout,
526 currier_step,
527 nb_steps,
528 current_step,
529 direction,
530 tuner_freq,
531 timeout,
532 freq;
533
534 srate = intp->symbol_rate[d];
535 search_range = intp->srch_range[d];
536
537 if (srate >= 10000000)
538 locktimeout = demod_timeout / 3;
539 else
540 locktimeout = demod_timeout / 2;
541
542 lock = stv0900_get_demod_lock(intp, d, locktimeout);
543
544 if (lock != FALSE)
545 return lock;
546
547 if (srate >= 10000000) {
548 if (stv0900_check_timing_lock(intp, d) == TRUE) {
549 stv0900_write_reg(intp, DMDISTATE, 0x1f);
550 stv0900_write_reg(intp, DMDISTATE, 0x15);
551 lock = stv0900_get_demod_lock(intp, d, demod_timeout);
552 } else
553 lock = FALSE;
554
555 return lock;
556 }
557
558 if (intp->chip_id <= 0x20) {
559 if (srate <= 1000000)
560 currier_step = 500;
561 else if (srate <= 4000000)
562 currier_step = 1000;
563 else if (srate <= 7000000)
564 currier_step = 2000;
565 else if (srate <= 10000000)
566 currier_step = 3000;
567 else
568 currier_step = 5000;
569
570 if (srate >= 2000000) {
571 timeout = (demod_timeout / 3);
572 if (timeout > 1000)
573 timeout = 1000;
574 } else
575 timeout = (demod_timeout / 2);
576 } else {
577 /*cut 3.0 */
578 currier_step = srate / 4000;
579 timeout = (demod_timeout * 3) / 4;
580 }
581
582 nb_steps = ((search_range / 1000) / currier_step);
583
584 if ((nb_steps % 2) != 0)
585 nb_steps += 1;
586
587 if (nb_steps <= 0)
588 nb_steps = 2;
589 else if (nb_steps > 12)
590 nb_steps = 12;
591
592 current_step = 1;
593 direction = 1;
594
595 if (intp->chip_id <= 0x20) {
596 tuner_freq = intp->freq[d];
597 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
598 intp->rolloff) + intp->symbol_rate[d];
599 } else
600 tuner_freq = 0;
601
602 while ((current_step <= nb_steps) && (lock == FALSE)) {
603 if (direction > 0)
604 tuner_freq += (current_step * currier_step);
605 else
606 tuner_freq -= (current_step * currier_step);
607
608 if (intp->chip_id <= 0x20) {
609 if (intp->tuner_type[d] == 3)
610 stv0900_set_tuner_auto(intp, tuner_freq,
611 intp->bw[d], demod);
612 else
613 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
614
615 stv0900_write_reg(intp, DMDISTATE, 0x1c);
616 stv0900_write_reg(intp, CFRINIT1, 0);
617 stv0900_write_reg(intp, CFRINIT0, 0);
618 stv0900_write_reg(intp, DMDISTATE, 0x1f);
619 stv0900_write_reg(intp, DMDISTATE, 0x15);
620 } else {
621 stv0900_write_reg(intp, DMDISTATE, 0x1c);
622 freq = (tuner_freq * 65536) / (intp->mclk / 1000);
623 stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
624 stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
625 stv0900_write_reg(intp, DMDISTATE, 0x1f);
626 stv0900_write_reg(intp, DMDISTATE, 0x05);
627 }
628
629 lock = stv0900_get_demod_lock(intp, d, timeout);
630 direction *= -1;
631 current_step++;
632 }
633
634 return lock;
635 }
636
637 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
638 s32 srate,
639 enum fe_stv0900_search_algo algo)
640 {
641 switch (algo) {
642 case STV0900_BLIND_SEARCH:
643 if (srate <= 1500000) {
644 (*demod_timeout) = 1500;
645 (*fec_timeout) = 400;
646 } else if (srate <= 5000000) {
647 (*demod_timeout) = 1000;
648 (*fec_timeout) = 300;
649 } else {
650 (*demod_timeout) = 700;
651 (*fec_timeout) = 100;
652 }
653
654 break;
655 case STV0900_COLD_START:
656 case STV0900_WARM_START:
657 default:
658 if (srate <= 1000000) {
659 (*demod_timeout) = 3000;
660 (*fec_timeout) = 1700;
661 } else if (srate <= 2000000) {
662 (*demod_timeout) = 2500;
663 (*fec_timeout) = 1100;
664 } else if (srate <= 5000000) {
665 (*demod_timeout) = 1000;
666 (*fec_timeout) = 550;
667 } else if (srate <= 10000000) {
668 (*demod_timeout) = 700;
669 (*fec_timeout) = 250;
670 } else if (srate <= 20000000) {
671 (*demod_timeout) = 400;
672 (*fec_timeout) = 130;
673 } else {
674 (*demod_timeout) = 300;
675 (*fec_timeout) = 100;
676 }
677
678 break;
679
680 }
681
682 if (algo == STV0900_WARM_START)
683 (*demod_timeout) /= 2;
684 }
685
686 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
687 enum fe_stv0900_demod_num demod)
688 {
689
690 s32 vth_reg = VTH12;
691
692 dprintk("%s\n", __func__);
693
694 stv0900_write_reg(intp, vth_reg++, 0xd0);
695 stv0900_write_reg(intp, vth_reg++, 0x7d);
696 stv0900_write_reg(intp, vth_reg++, 0x53);
697 stv0900_write_reg(intp, vth_reg++, 0x2f);
698 stv0900_write_reg(intp, vth_reg++, 0x24);
699 stv0900_write_reg(intp, vth_reg++, 0x1f);
700 }
701
702 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
703 enum fe_stv0900_search_standard standard,
704 enum fe_stv0900_fec fec,
705 enum fe_stv0900_demod_num demod)
706 {
707 dprintk("%s: ViterbiStandard = ", __func__);
708
709 switch (standard) {
710 case STV0900_AUTO_SEARCH:
711 dprintk("Auto\n");
712 stv0900_write_reg(intp, FECM, 0x10);
713 stv0900_write_reg(intp, PRVIT, 0x3f);
714 break;
715 case STV0900_SEARCH_DVBS1:
716 dprintk("DVBS1\n");
717 stv0900_write_reg(intp, FECM, 0x00);
718 switch (fec) {
719 case STV0900_FEC_UNKNOWN:
720 default:
721 stv0900_write_reg(intp, PRVIT, 0x2f);
722 break;
723 case STV0900_FEC_1_2:
724 stv0900_write_reg(intp, PRVIT, 0x01);
725 break;
726 case STV0900_FEC_2_3:
727 stv0900_write_reg(intp, PRVIT, 0x02);
728 break;
729 case STV0900_FEC_3_4:
730 stv0900_write_reg(intp, PRVIT, 0x04);
731 break;
732 case STV0900_FEC_5_6:
733 stv0900_write_reg(intp, PRVIT, 0x08);
734 break;
735 case STV0900_FEC_7_8:
736 stv0900_write_reg(intp, PRVIT, 0x20);
737 break;
738 }
739
740 break;
741 case STV0900_SEARCH_DSS:
742 dprintk("DSS\n");
743 stv0900_write_reg(intp, FECM, 0x80);
744 switch (fec) {
745 case STV0900_FEC_UNKNOWN:
746 default:
747 stv0900_write_reg(intp, PRVIT, 0x13);
748 break;
749 case STV0900_FEC_1_2:
750 stv0900_write_reg(intp, PRVIT, 0x01);
751 break;
752 case STV0900_FEC_2_3:
753 stv0900_write_reg(intp, PRVIT, 0x02);
754 break;
755 case STV0900_FEC_6_7:
756 stv0900_write_reg(intp, PRVIT, 0x10);
757 break;
758 }
759 break;
760 default:
761 break;
762 }
763 }
764
765 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
766 enum fe_stv0900_demod_num demod)
767 {
768 enum fe_stv0900_fec prate;
769 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
770
771 switch (rate_fld) {
772 case 13:
773 prate = STV0900_FEC_1_2;
774 break;
775 case 18:
776 prate = STV0900_FEC_2_3;
777 break;
778 case 21:
779 prate = STV0900_FEC_3_4;
780 break;
781 case 24:
782 prate = STV0900_FEC_5_6;
783 break;
784 case 25:
785 prate = STV0900_FEC_6_7;
786 break;
787 case 26:
788 prate = STV0900_FEC_7_8;
789 break;
790 default:
791 prate = STV0900_FEC_UNKNOWN;
792 break;
793 }
794
795 return prate;
796 }
797
798 static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
799 enum fe_stv0900_demod_num demod,
800 u32 srate)
801 {
802 if (intp->chip_id >= 0x30) {
803 if (srate >= 15000000) {
804 stv0900_write_reg(intp, ACLC, 0x2b);
805 stv0900_write_reg(intp, BCLC, 0x1a);
806 } else if ((srate >= 7000000) && (15000000 > srate)) {
807 stv0900_write_reg(intp, ACLC, 0x0c);
808 stv0900_write_reg(intp, BCLC, 0x1b);
809 } else if (srate < 7000000) {
810 stv0900_write_reg(intp, ACLC, 0x2c);
811 stv0900_write_reg(intp, BCLC, 0x1c);
812 }
813
814 } else { /*cut 2.0 and 1.x*/
815 stv0900_write_reg(intp, ACLC, 0x1a);
816 stv0900_write_reg(intp, BCLC, 0x09);
817 }
818
819 }
820
821 static void stv0900_track_optimization(struct dvb_frontend *fe)
822 {
823 struct stv0900_state *state = fe->demodulator_priv;
824 struct stv0900_internal *intp = state->internal;
825 enum fe_stv0900_demod_num demod = state->demod;
826
827 s32 srate,
828 pilots,
829 aclc,
830 freq1,
831 freq0,
832 i = 0,
833 timed,
834 timef,
835 blind_tun_sw = 0,
836 modulation;
837
838 enum fe_stv0900_rolloff rolloff;
839 enum fe_stv0900_modcode foundModcod;
840
841 dprintk("%s\n", __func__);
842
843 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
844 srate += stv0900_get_timing_offst(intp, srate, demod);
845
846 switch (intp->result[demod].standard) {
847 case STV0900_DVBS1_STANDARD:
848 case STV0900_DSS_STANDARD:
849 dprintk("%s: found DVB-S or DSS\n", __func__);
850 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
851 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
852 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
853 }
854
855 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
856 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
857
858 if (intp->chip_id < 0x30) {
859 stv0900_write_reg(intp, ERRCTRL1, 0x75);
860 break;
861 }
862
863 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
864 stv0900_write_reg(intp, GAUSSR0, 0x98);
865 stv0900_write_reg(intp, CCIR0, 0x18);
866 } else {
867 stv0900_write_reg(intp, GAUSSR0, 0x18);
868 stv0900_write_reg(intp, CCIR0, 0x18);
869 }
870
871 stv0900_write_reg(intp, ERRCTRL1, 0x75);
872 break;
873 case STV0900_DVBS2_STANDARD:
874 dprintk("%s: found DVB-S2\n", __func__);
875 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
876 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
877 stv0900_write_reg(intp, ACLC, 0);
878 stv0900_write_reg(intp, BCLC, 0);
879 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
880 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
881 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
882 aclc = stv0900_get_optim_carr_loop(srate,
883 foundModcod,
884 pilots,
885 intp->chip_id);
886 if (foundModcod <= STV0900_QPSK_910)
887 stv0900_write_reg(intp, ACLC2S2Q, aclc);
888 else if (foundModcod <= STV0900_8PSK_910) {
889 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
890 stv0900_write_reg(intp, ACLC2S28, aclc);
891 }
892
893 if ((intp->demod_mode == STV0900_SINGLE) &&
894 (foundModcod > STV0900_8PSK_910)) {
895 if (foundModcod <= STV0900_16APSK_910) {
896 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
897 stv0900_write_reg(intp, ACLC2S216A,
898 aclc);
899 } else if (foundModcod <= STV0900_32APSK_910) {
900 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
901 stv0900_write_reg(intp, ACLC2S232A,
902 aclc);
903 }
904 }
905
906 } else {
907 modulation = intp->result[demod].modulation;
908 aclc = stv0900_get_optim_short_carr_loop(srate,
909 modulation, intp->chip_id);
910 if (modulation == STV0900_QPSK)
911 stv0900_write_reg(intp, ACLC2S2Q, aclc);
912 else if (modulation == STV0900_8PSK) {
913 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
914 stv0900_write_reg(intp, ACLC2S28, aclc);
915 } else if (modulation == STV0900_16APSK) {
916 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
917 stv0900_write_reg(intp, ACLC2S216A, aclc);
918 } else if (modulation == STV0900_32APSK) {
919 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
920 stv0900_write_reg(intp, ACLC2S232A, aclc);
921 }
922
923 }
924
925 if (intp->chip_id <= 0x11) {
926 if (intp->demod_mode != STV0900_SINGLE)
927 stv0900_activate_s2_modcod(intp, demod);
928
929 }
930
931 stv0900_write_reg(intp, ERRCTRL1, 0x67);
932 break;
933 case STV0900_UNKNOWN_STANDARD:
934 default:
935 dprintk("%s: found unknown standard\n", __func__);
936 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
937 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
938 break;
939 }
940
941 freq1 = stv0900_read_reg(intp, CFR2);
942 freq0 = stv0900_read_reg(intp, CFR1);
943 rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
944 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
945 stv0900_write_reg(intp, SFRSTEP, 0x00);
946 stv0900_write_bits(intp, SCAN_ENABLE, 0);
947 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
948 stv0900_write_reg(intp, TMGCFG2, 0xc1);
949 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
950 blind_tun_sw = 1;
951 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
952 stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
953
954 }
955
956 if (intp->chip_id >= 0x20) {
957 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
958 (intp->srch_standard[demod] ==
959 STV0900_SEARCH_DSS) ||
960 (intp->srch_standard[demod] ==
961 STV0900_AUTO_SEARCH)) {
962 stv0900_write_reg(intp, VAVSRVIT, 0x0a);
963 stv0900_write_reg(intp, VITSCALE, 0x0);
964 }
965 }
966
967 if (intp->chip_id < 0x20)
968 stv0900_write_reg(intp, CARHDR, 0x08);
969
970 if (intp->chip_id == 0x10)
971 stv0900_write_reg(intp, CORRELEXP, 0x0a);
972
973 stv0900_write_reg(intp, AGC2REF, 0x38);
974
975 if ((intp->chip_id >= 0x20) ||
976 (blind_tun_sw == 1) ||
977 (intp->symbol_rate[demod] < 10000000)) {
978 stv0900_write_reg(intp, CFRINIT1, freq1);
979 stv0900_write_reg(intp, CFRINIT0, freq0);
980 intp->bw[demod] = stv0900_carrier_width(srate,
981 intp->rolloff) + 10000000;
982
983 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
984 if (intp->srch_algo[demod] != STV0900_WARM_START) {
985 if (intp->tuner_type[demod] == 3)
986 stv0900_set_tuner_auto(intp,
987 intp->freq[demod],
988 intp->bw[demod],
989 demod);
990 else
991 stv0900_set_bandwidth(fe,
992 intp->bw[demod]);
993 }
994 }
995
996 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
997 (intp->symbol_rate[demod] < 10000000))
998 msleep(50);
999 else
1000 msleep(5);
1001
1002 stv0900_get_lock_timeout(&timed, &timef, srate,
1003 STV0900_WARM_START);
1004
1005 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
1006 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1007 stv0900_write_reg(intp, CFRINIT1, freq1);
1008 stv0900_write_reg(intp, CFRINIT0, freq0);
1009 stv0900_write_reg(intp, DMDISTATE, 0x18);
1010 i = 0;
1011 while ((stv0900_get_demod_lock(intp,
1012 demod,
1013 timed / 2) == FALSE) &&
1014 (i <= 2)) {
1015 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1016 stv0900_write_reg(intp, CFRINIT1, freq1);
1017 stv0900_write_reg(intp, CFRINIT0, freq0);
1018 stv0900_write_reg(intp, DMDISTATE, 0x18);
1019 i++;
1020 }
1021 }
1022
1023 }
1024
1025 if (intp->chip_id >= 0x20)
1026 stv0900_write_reg(intp, CARFREQ, 0x49);
1027
1028 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1029 (intp->result[demod].standard == STV0900_DSS_STANDARD))
1030 stv0900_set_viterbi_tracq(intp, demod);
1031
1032 }
1033
1034 static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1035 enum fe_stv0900_demod_num demod, s32 time_out)
1036 {
1037 s32 timer = 0, lock = 0;
1038
1039 enum fe_stv0900_search_state dmd_state;
1040
1041 dprintk("%s\n", __func__);
1042
1043 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1044
1045 while ((timer < time_out) && (lock == 0)) {
1046 switch (dmd_state) {
1047 case STV0900_SEARCH:
1048 case STV0900_PLH_DETECTED:
1049 default:
1050 lock = 0;
1051 break;
1052 case STV0900_DVBS2_FOUND:
1053 lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1054 break;
1055 case STV0900_DVBS_FOUND:
1056 lock = stv0900_get_bits(intp, LOCKEDVIT);
1057 break;
1058 }
1059
1060 if (lock == 0) {
1061 msleep(10);
1062 timer += 10;
1063 }
1064 }
1065
1066 if (lock)
1067 dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1068 else
1069 dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1070
1071 return lock;
1072 }
1073
1074 static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1075 enum fe_stv0900_demod_num demod,
1076 s32 dmd_timeout, s32 fec_timeout)
1077 {
1078
1079 s32 timer = 0, lock = 0;
1080
1081 dprintk("%s\n", __func__);
1082
1083 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1084
1085 if (lock)
1086 lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
1087
1088 if (lock) {
1089 lock = 0;
1090
1091 dprintk("%s: Timer = %d, time_out = %d\n",
1092 __func__, timer, fec_timeout);
1093
1094 while ((timer < fec_timeout) && (lock == 0)) {
1095 lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1096 msleep(1);
1097 timer++;
1098 }
1099 }
1100
1101 if (lock)
1102 dprintk("%s: DEMOD LOCK OK\n", __func__);
1103 else
1104 dprintk("%s: DEMOD LOCK FAIL\n", __func__);
1105
1106 if (lock)
1107 return TRUE;
1108 else
1109 return FALSE;
1110 }
1111
1112 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1113 enum fe_stv0900_demod_num demod)
1114 {
1115 struct stv0900_state *state = fe->demodulator_priv;
1116 struct stv0900_internal *intp = state->internal;
1117 enum fe_stv0900_tracking_standard fnd_standard;
1118
1119 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1120
1121 switch (hdr_mode) {
1122 case 2:
1123 fnd_standard = STV0900_DVBS2_STANDARD;
1124 break;
1125 case 3:
1126 if (stv0900_get_bits(intp, DSS_DVB) == 1)
1127 fnd_standard = STV0900_DSS_STANDARD;
1128 else
1129 fnd_standard = STV0900_DVBS1_STANDARD;
1130
1131 break;
1132 default:
1133 fnd_standard = STV0900_UNKNOWN_STANDARD;
1134 }
1135
1136 dprintk("%s: standard %d\n", __func__, fnd_standard);
1137
1138 return fnd_standard;
1139 }
1140
1141 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1142 enum fe_stv0900_demod_num demod)
1143 {
1144 s32 derot,
1145 rem1,
1146 rem2,
1147 intval1,
1148 intval2;
1149
1150 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1151 (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1152 (stv0900_get_bits(intp, CAR_FREQ0));
1153
1154 derot = ge2comp(derot, 24);
1155 intval1 = mclk >> 12;
1156 intval2 = derot >> 12;
1157 rem1 = mclk % 0x1000;
1158 rem2 = derot % 0x1000;
1159 derot = (intval1 * intval2) +
1160 ((intval1 * rem2) >> 12) +
1161 ((intval2 * rem1) >> 12);
1162
1163 return derot;
1164 }
1165
1166 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1167 {
1168 struct dvb_frontend_ops *frontend_ops = NULL;
1169 struct dvb_tuner_ops *tuner_ops = NULL;
1170 u32 freq = 0;
1171
1172 if (&fe->ops)
1173 frontend_ops = &fe->ops;
1174
1175 if (&frontend_ops->tuner_ops)
1176 tuner_ops = &frontend_ops->tuner_ops;
1177
1178 if (tuner_ops->get_frequency) {
1179 if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1180 dprintk("%s: Invalid parameter\n", __func__);
1181 else
1182 dprintk("%s: Frequency=%d\n", __func__, freq);
1183
1184 }
1185
1186 return freq;
1187 }
1188
1189 static enum
1190 fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1191 {
1192 struct stv0900_state *state = fe->demodulator_priv;
1193 struct stv0900_internal *intp = state->internal;
1194 enum fe_stv0900_demod_num demod = state->demod;
1195 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1196 struct stv0900_signal_info *result = &intp->result[demod];
1197 s32 offsetFreq,
1198 srate_offset;
1199 int i = 0,
1200 d = demod;
1201
1202 u8 timing;
1203
1204 msleep(5);
1205 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1206 timing = stv0900_read_reg(intp, TMGREG2);
1207 i = 0;
1208 stv0900_write_reg(intp, SFRSTEP, 0x5c);
1209
1210 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1211 timing = stv0900_read_reg(intp, TMGREG2);
1212 msleep(5);
1213 i += 5;
1214 }
1215 }
1216
1217 result->standard = stv0900_get_standard(fe, d);
1218 if (intp->tuner_type[demod] == 3)
1219 result->frequency = stv0900_get_freq_auto(intp, d);
1220 else
1221 result->frequency = stv0900_get_tuner_freq(fe);
1222
1223 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1224 result->frequency += offsetFreq;
1225 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1226 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1227 result->symbol_rate += srate_offset;
1228 result->fec = stv0900_get_vit_fec(intp, d);
1229 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1230 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1231 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1232 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1233
1234 dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
1235
1236 switch (result->standard) {
1237 case STV0900_DVBS2_STANDARD:
1238 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1239 if (result->modcode <= STV0900_QPSK_910)
1240 result->modulation = STV0900_QPSK;
1241 else if (result->modcode <= STV0900_8PSK_910)
1242 result->modulation = STV0900_8PSK;
1243 else if (result->modcode <= STV0900_16APSK_910)
1244 result->modulation = STV0900_16APSK;
1245 else if (result->modcode <= STV0900_32APSK_910)
1246 result->modulation = STV0900_32APSK;
1247 else
1248 result->modulation = STV0900_UNKNOWN;
1249 break;
1250 case STV0900_DVBS1_STANDARD:
1251 case STV0900_DSS_STANDARD:
1252 result->spectrum = stv0900_get_bits(intp, IQINV);
1253 result->modulation = STV0900_QPSK;
1254 break;
1255 default:
1256 break;
1257 }
1258
1259 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1260 (intp->symbol_rate[d] < 10000000)) {
1261 offsetFreq = result->frequency - intp->freq[d];
1262 if (intp->tuner_type[demod] == 3)
1263 intp->freq[d] = stv0900_get_freq_auto(intp, d);
1264 else
1265 intp->freq[d] = stv0900_get_tuner_freq(fe);
1266
1267 if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1268 range = STV0900_RANGEOK;
1269 else if (ABS(offsetFreq) <=
1270 (stv0900_carrier_width(result->symbol_rate,
1271 result->rolloff) / 2000))
1272 range = STV0900_RANGEOK;
1273
1274 } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1275 range = STV0900_RANGEOK;
1276
1277 dprintk("%s: range %d\n", __func__, range);
1278
1279 return range;
1280 }
1281
1282 static enum
1283 fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1284 {
1285 struct stv0900_state *state = fe->demodulator_priv;
1286 struct stv0900_internal *intp = state->internal;
1287 enum fe_stv0900_demod_num demod = state->demod;
1288 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1289
1290 s32 srate,
1291 demod_timeout,
1292 fec_timeout,
1293 freq1,
1294 freq0;
1295
1296 intp->result[demod].locked = FALSE;
1297
1298 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1299 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1300 srate += stv0900_get_timing_offst(intp, srate, demod);
1301 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1302 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1303
1304 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1305 srate, STV0900_WARM_START);
1306 freq1 = stv0900_read_reg(intp, CFR2);
1307 freq0 = stv0900_read_reg(intp, CFR1);
1308 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1309 stv0900_write_bits(intp, SPECINV_CONTROL,
1310 STV0900_IQ_FORCE_SWAPPED);
1311 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1312 stv0900_write_reg(intp, CFRINIT1, freq1);
1313 stv0900_write_reg(intp, CFRINIT0, freq0);
1314 stv0900_write_reg(intp, DMDISTATE, 0x18);
1315 if (stv0900_wait_for_lock(intp, demod,
1316 demod_timeout, fec_timeout) == TRUE) {
1317 intp->result[demod].locked = TRUE;
1318 signal_type = stv0900_get_signal_params(fe);
1319 stv0900_track_optimization(fe);
1320 } else {
1321 stv0900_write_bits(intp, SPECINV_CONTROL,
1322 STV0900_IQ_FORCE_NORMAL);
1323 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1324 stv0900_write_reg(intp, CFRINIT1, freq1);
1325 stv0900_write_reg(intp, CFRINIT0, freq0);
1326 stv0900_write_reg(intp, DMDISTATE, 0x18);
1327 if (stv0900_wait_for_lock(intp, demod,
1328 demod_timeout, fec_timeout) == TRUE) {
1329 intp->result[demod].locked = TRUE;
1330 signal_type = stv0900_get_signal_params(fe);
1331 stv0900_track_optimization(fe);
1332 }
1333
1334 }
1335
1336 } else
1337 intp->result[demod].locked = FALSE;
1338
1339 return signal_type;
1340 }
1341
1342 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1343 enum fe_stv0900_demod_num demod)
1344 {
1345 u32 minagc2level = 0xffff,
1346 agc2level,
1347 init_freq, freq_step;
1348
1349 s32 i, j, nb_steps, direction;
1350
1351 dprintk("%s\n", __func__);
1352
1353 stv0900_write_reg(intp, AGC2REF, 0x38);
1354 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1355 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1356
1357 stv0900_write_bits(intp, AUTO_GUP, 1);
1358 stv0900_write_bits(intp, AUTO_GLOW, 1);
1359
1360 stv0900_write_reg(intp, DMDT0M, 0x0);
1361
1362 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1363 nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1364 nb_steps /= 2;
1365 nb_steps = (2 * nb_steps) + 1;
1366
1367 if (nb_steps < 0)
1368 nb_steps = 1;
1369
1370 direction = 1;
1371
1372 freq_step = (1000000 << 8) / (intp->mclk >> 8);
1373
1374 init_freq = 0;
1375
1376 for (i = 0; i < nb_steps; i++) {
1377 if (direction > 0)
1378 init_freq = init_freq + (freq_step * i);
1379 else
1380 init_freq = init_freq - (freq_step * i);
1381
1382 direction *= -1;
1383 stv0900_write_reg(intp, DMDISTATE, 0x5C);
1384 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1385 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1386 stv0900_write_reg(intp, DMDISTATE, 0x58);
1387 msleep(10);
1388 agc2level = 0;
1389
1390 for (j = 0; j < 10; j++)
1391 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1392 | stv0900_read_reg(intp, AGC2I0);
1393
1394 agc2level /= 10;
1395
1396 if (agc2level < minagc2level)
1397 minagc2level = agc2level;
1398
1399 }
1400
1401 return (u16)minagc2level;
1402 }
1403
1404 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1405 {
1406 struct stv0900_state *state = fe->demodulator_priv;
1407 struct stv0900_internal *intp = state->internal;
1408 enum fe_stv0900_demod_num demod = state->demod;
1409 int timing_lck = FALSE;
1410 s32 i, timingcpt = 0,
1411 direction = 1,
1412 nb_steps,
1413 current_step = 0,
1414 tuner_freq;
1415 u32 agc2_th,
1416 coarse_srate = 0,
1417 agc2_integr = 0,
1418 currier_step = 1200;
1419
1420 if (intp->chip_id >= 0x30)
1421 agc2_th = 0x2e00;
1422 else
1423 agc2_th = 0x1f00;
1424
1425 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1426 stv0900_write_reg(intp, TMGCFG, 0x12);
1427 stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1428 stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1429 stv0900_write_bits(intp, SCAN_ENABLE, 1);
1430 stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1431 stv0900_write_reg(intp, SFRUP1, 0x83);
1432 stv0900_write_reg(intp, SFRUP0, 0xc0);
1433 stv0900_write_reg(intp, SFRLOW1, 0x82);
1434 stv0900_write_reg(intp, SFRLOW0, 0xa0);
1435 stv0900_write_reg(intp, DMDT0M, 0x0);
1436 stv0900_write_reg(intp, AGC2REF, 0x50);
1437
1438 if (intp->chip_id >= 0x30) {
1439 stv0900_write_reg(intp, CARFREQ, 0x99);
1440 stv0900_write_reg(intp, SFRSTEP, 0x98);
1441 } else if (intp->chip_id >= 0x20) {
1442 stv0900_write_reg(intp, CARFREQ, 0x6a);
1443 stv0900_write_reg(intp, SFRSTEP, 0x95);
1444 } else {
1445 stv0900_write_reg(intp, CARFREQ, 0xed);
1446 stv0900_write_reg(intp, SFRSTEP, 0x73);
1447 }
1448
1449 if (intp->symbol_rate[demod] <= 2000000)
1450 currier_step = 1000;
1451 else if (intp->symbol_rate[demod] <= 5000000)
1452 currier_step = 2000;
1453 else if (intp->symbol_rate[demod] <= 12000000)
1454 currier_step = 3000;
1455 else
1456 currier_step = 5000;
1457
1458 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1459 nb_steps /= 2;
1460 nb_steps = (2 * nb_steps) + 1;
1461
1462 if (nb_steps < 0)
1463 nb_steps = 1;
1464 else if (nb_steps > 10) {
1465 nb_steps = 11;
1466 currier_step = (intp->srch_range[demod] / 1000) / 10;
1467 }
1468
1469 current_step = 0;
1470 direction = 1;
1471
1472 tuner_freq = intp->freq[demod];
1473
1474 while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1475 stv0900_write_reg(intp, DMDISTATE, 0x5f);
1476 stv0900_write_bits(intp, DEMOD_MODE, 0);
1477
1478 msleep(50);
1479
1480 for (i = 0; i < 10; i++) {
1481 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1482 timingcpt++;
1483
1484 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1485 stv0900_read_reg(intp, AGC2I0);
1486 }
1487
1488 agc2_integr /= 10;
1489 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1490 current_step++;
1491 direction *= -1;
1492
1493 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
1494 " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
1495 tuner_freq, agc2_integr, coarse_srate, timingcpt);
1496
1497 if ((timingcpt >= 5) &&
1498 (agc2_integr < agc2_th) &&
1499 (coarse_srate < 55000000) &&
1500 (coarse_srate > 850000))
1501 timing_lck = TRUE;
1502 else if (current_step < nb_steps) {
1503 if (direction > 0)
1504 tuner_freq += (current_step * currier_step);
1505 else
1506 tuner_freq -= (current_step * currier_step);
1507
1508 if (intp->tuner_type[demod] == 3)
1509 stv0900_set_tuner_auto(intp, tuner_freq,
1510 intp->bw[demod], demod);
1511 else
1512 stv0900_set_tuner(fe, tuner_freq,
1513 intp->bw[demod]);
1514 }
1515 }
1516
1517 if (timing_lck == FALSE)
1518 coarse_srate = 0;
1519 else
1520 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1521
1522 return coarse_srate;
1523 }
1524
1525 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
1526 {
1527 struct stv0900_state *state = fe->demodulator_priv;
1528 struct stv0900_internal *intp = state->internal;
1529 enum fe_stv0900_demod_num demod = state->demod;
1530 u32 coarse_srate,
1531 coarse_freq,
1532 symb,
1533 symbmax,
1534 symbmin,
1535 symbcomp;
1536
1537 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1538
1539 if (coarse_srate > 3000000) {
1540 symbmax = 13 * (coarse_srate / 10);
1541 symbmax = (symbmax / 1000) * 65536;
1542 symbmax /= (intp->mclk / 1000);
1543
1544 symbmin = 10 * (coarse_srate / 13);
1545 symbmin = (symbmin / 1000)*65536;
1546 symbmin /= (intp->mclk / 1000);
1547
1548 symb = (coarse_srate / 1000) * 65536;
1549 symb /= (intp->mclk / 1000);
1550 } else {
1551 symbmax = 13 * (coarse_srate / 10);
1552 symbmax = (symbmax / 100) * 65536;
1553 symbmax /= (intp->mclk / 100);
1554
1555 symbmin = 10 * (coarse_srate / 14);
1556 symbmin = (symbmin / 100) * 65536;
1557 symbmin /= (intp->mclk / 100);
1558
1559 symb = (coarse_srate / 100) * 65536;
1560 symb /= (intp->mclk / 100);
1561 }
1562
1563 symbcomp = 13 * (coarse_srate / 10);
1564 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1565 | stv0900_read_reg(intp, CFR1);
1566
1567 if (symbcomp < intp->symbol_rate[demod])
1568 coarse_srate = 0;
1569 else {
1570 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1571 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1572 stv0900_write_reg(intp, TMGTHRISE, 0x20);
1573 stv0900_write_reg(intp, TMGTHFALL, 0x00);
1574 stv0900_write_reg(intp, TMGCFG, 0xd2);
1575 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1576 stv0900_write_reg(intp, AGC2REF, 0x38);
1577
1578 if (intp->chip_id >= 0x30)
1579 stv0900_write_reg(intp, CARFREQ, 0x79);
1580 else if (intp->chip_id >= 0x20)
1581 stv0900_write_reg(intp, CARFREQ, 0x49);
1582 else
1583 stv0900_write_reg(intp, CARFREQ, 0xed);
1584
1585 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1586 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
1587
1588 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1589 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1590
1591 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1592 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1593
1594 stv0900_write_reg(intp, DMDT0M, 0x20);
1595 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1596 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1597 stv0900_write_reg(intp, DMDISTATE, 0x15);
1598 }
1599
1600 return coarse_srate;
1601 }
1602
1603 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
1604 {
1605 struct stv0900_state *state = fe->demodulator_priv;
1606 struct stv0900_internal *intp = state->internal;
1607 enum fe_stv0900_demod_num demod = state->demod;
1608 u8 k_ref_tmg,
1609 k_ref_tmg_max,
1610 k_ref_tmg_min;
1611 u32 coarse_srate,
1612 agc2_th;
1613 int lock = FALSE,
1614 coarse_fail = FALSE;
1615 s32 demod_timeout = 500,
1616 fec_timeout = 50,
1617 fail_cpt,
1618 i,
1619 agc2_overflow;
1620 u16 agc2_int;
1621 u8 dstatus2;
1622
1623 dprintk("%s\n", __func__);
1624
1625 if (intp->chip_id < 0x20) {
1626 k_ref_tmg_max = 233;
1627 k_ref_tmg_min = 143;
1628 } else {
1629 k_ref_tmg_max = 110;
1630 k_ref_tmg_min = 10;
1631 }
1632
1633 if (intp->chip_id <= 0x20)
1634 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
1635 else
1636 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
1637
1638 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
1639
1640 dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
1641 if (agc2_int > agc2_th)
1642 return FALSE;
1643
1644 if (intp->chip_id == 0x10)
1645 stv0900_write_reg(intp, CORRELEXP, 0xaa);
1646
1647 if (intp->chip_id < 0x20)
1648 stv0900_write_reg(intp, CARHDR, 0x55);
1649 else
1650 stv0900_write_reg(intp, CARHDR, 0x20);
1651
1652 if (intp->chip_id <= 0x20)
1653 stv0900_write_reg(intp, CARCFG, 0xc4);
1654 else
1655 stv0900_write_reg(intp, CARCFG, 0x6);
1656
1657 stv0900_write_reg(intp, RTCS2, 0x44);
1658
1659 if (intp->chip_id >= 0x20) {
1660 stv0900_write_reg(intp, EQUALCFG, 0x41);
1661 stv0900_write_reg(intp, FFECFG, 0x41);
1662 stv0900_write_reg(intp, VITSCALE, 0x82);
1663 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1664 }
1665
1666 k_ref_tmg = k_ref_tmg_max;
1667
1668 do {
1669 stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1670 if (stv0900_search_srate_coarse(fe) != 0) {
1671 coarse_srate = stv0900_search_srate_fine(fe);
1672
1673 if (coarse_srate != 0) {
1674 stv0900_get_lock_timeout(&demod_timeout,
1675 &fec_timeout,
1676 coarse_srate,
1677 STV0900_BLIND_SEARCH);
1678 lock = stv0900_get_demod_lock(intp,
1679 demod,
1680 demod_timeout);
1681 } else
1682 lock = FALSE;
1683 } else {
1684 fail_cpt = 0;
1685 agc2_overflow = 0;
1686
1687 for (i = 0; i < 10; i++) {
1688 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1689 | stv0900_read_reg(intp, AGC2I0);
1690
1691 if (agc2_int >= 0xff00)
1692 agc2_overflow++;
1693
1694 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
1695
1696 if (((dstatus2 & 0x1) == 0x1) &&
1697 ((dstatus2 >> 7) == 1))
1698 fail_cpt++;
1699 }
1700
1701 if ((fail_cpt > 7) || (agc2_overflow > 7))
1702 coarse_fail = TRUE;
1703
1704 lock = FALSE;
1705 }
1706 k_ref_tmg -= 30;
1707 } while ((k_ref_tmg >= k_ref_tmg_min) &&
1708 (lock == FALSE) &&
1709 (coarse_fail == FALSE));
1710
1711 return lock;
1712 }
1713
1714 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
1715 enum fe_stv0900_demod_num demod)
1716 {
1717 s32 vth_reg = VTH12;
1718
1719 dprintk("%s\n", __func__);
1720
1721 stv0900_write_reg(intp, vth_reg++, 0x96);
1722 stv0900_write_reg(intp, vth_reg++, 0x64);
1723 stv0900_write_reg(intp, vth_reg++, 0x36);
1724 stv0900_write_reg(intp, vth_reg++, 0x23);
1725 stv0900_write_reg(intp, vth_reg++, 0x1e);
1726 stv0900_write_reg(intp, vth_reg++, 0x19);
1727 }
1728
1729 static void stv0900_set_search_standard(struct stv0900_internal *intp,
1730 enum fe_stv0900_demod_num demod)
1731 {
1732
1733 dprintk("%s\n", __func__);
1734
1735 switch (intp->srch_standard[demod]) {
1736 case STV0900_SEARCH_DVBS1:
1737 dprintk("Search Standard = DVBS1\n");
1738 break;
1739 case STV0900_SEARCH_DSS:
1740 dprintk("Search Standard = DSS\n");
1741 case STV0900_SEARCH_DVBS2:
1742 break;
1743 dprintk("Search Standard = DVBS2\n");
1744 case STV0900_AUTO_SEARCH:
1745 default:
1746 dprintk("Search Standard = AUTO\n");
1747 break;
1748 }
1749
1750 switch (intp->srch_standard[demod]) {
1751 case STV0900_SEARCH_DVBS1:
1752 case STV0900_SEARCH_DSS:
1753 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1754 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1755 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1756 stv0900_set_dvbs1_track_car_loop(intp,
1757 demod,
1758 intp->symbol_rate[demod]);
1759 stv0900_write_reg(intp, CAR2CFG, 0x22);
1760
1761 stv0900_set_viterbi_acq(intp, demod);
1762 stv0900_set_viterbi_standard(intp,
1763 intp->srch_standard[demod],
1764 intp->fec[demod], demod);
1765
1766 break;
1767 case STV0900_SEARCH_DVBS2:
1768 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1769 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1770 stv0900_write_bits(intp, STOP_CLKVIT, 1);
1771 stv0900_write_reg(intp, ACLC, 0x1a);
1772 stv0900_write_reg(intp, BCLC, 0x09);
1773 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1774 stv0900_write_reg(intp, CAR2CFG, 0x26);
1775 else
1776 stv0900_write_reg(intp, CAR2CFG, 0x66);
1777
1778 if (intp->demod_mode != STV0900_SINGLE) {
1779 if (intp->chip_id <= 0x11)
1780 stv0900_stop_all_s2_modcod(intp, demod);
1781 else
1782 stv0900_activate_s2_modcod(intp, demod);
1783
1784 } else
1785 stv0900_activate_s2_modcod_single(intp, demod);
1786
1787 stv0900_set_viterbi_tracq(intp, demod);
1788
1789 break;
1790 case STV0900_AUTO_SEARCH:
1791 default:
1792 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1793 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1794 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1795 stv0900_write_reg(intp, ACLC, 0x1a);
1796 stv0900_write_reg(intp, BCLC, 0x09);
1797 stv0900_set_dvbs1_track_car_loop(intp,
1798 demod,
1799 intp->symbol_rate[demod]);
1800 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1801 stv0900_write_reg(intp, CAR2CFG, 0x26);
1802 else
1803 stv0900_write_reg(intp, CAR2CFG, 0x66);
1804
1805 if (intp->demod_mode != STV0900_SINGLE) {
1806 if (intp->chip_id <= 0x11)
1807 stv0900_stop_all_s2_modcod(intp, demod);
1808 else
1809 stv0900_activate_s2_modcod(intp, demod);
1810
1811 } else
1812 stv0900_activate_s2_modcod_single(intp, demod);
1813
1814 stv0900_set_viterbi_tracq(intp, demod);
1815 stv0900_set_viterbi_standard(intp,
1816 intp->srch_standard[demod],
1817 intp->fec[demod], demod);
1818
1819 break;
1820 }
1821 }
1822
1823 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
1824 {
1825 struct stv0900_state *state = fe->demodulator_priv;
1826 struct stv0900_internal *intp = state->internal;
1827 enum fe_stv0900_demod_num demod = state->demod;
1828
1829 s32 demod_timeout = 500, fec_timeout = 50;
1830 s32 aq_power, agc1_power, i;
1831
1832 int lock = FALSE, low_sr = FALSE;
1833
1834 enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
1835 enum fe_stv0900_search_algo algo;
1836 int no_signal = FALSE;
1837
1838 dprintk("%s\n", __func__);
1839
1840 algo = intp->srch_algo[demod];
1841 stv0900_write_bits(intp, RST_HWARE, 1);
1842 stv0900_write_reg(intp, DMDISTATE, 0x5c);
1843 if (intp->chip_id >= 0x20) {
1844 if (intp->symbol_rate[demod] > 5000000)
1845 stv0900_write_reg(intp, CORRELABS, 0x9e);
1846 else
1847 stv0900_write_reg(intp, CORRELABS, 0x82);
1848 } else
1849 stv0900_write_reg(intp, CORRELABS, 0x88);
1850
1851 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1852 intp->symbol_rate[demod],
1853 intp->srch_algo[demod]);
1854
1855 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1856 intp->bw[demod] = 2 * 36000000;
1857
1858 stv0900_write_reg(intp, TMGCFG2, 0xc0);
1859 stv0900_write_reg(intp, CORRELMANT, 0x70);
1860
1861 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1862 } else {
1863 stv0900_write_reg(intp, DMDT0M, 0x20);
1864 stv0900_write_reg(intp, TMGCFG, 0xd2);
1865
1866 if (intp->symbol_rate[demod] < 2000000)
1867 stv0900_write_reg(intp, CORRELMANT, 0x63);
1868 else
1869 stv0900_write_reg(intp, CORRELMANT, 0x70);
1870
1871 stv0900_write_reg(intp, AGC2REF, 0x38);
1872
1873 intp->bw[demod] =
1874 stv0900_carrier_width(intp->symbol_rate[demod],
1875 intp->rolloff);
1876 if (intp->chip_id >= 0x20) {
1877 stv0900_write_reg(intp, KREFTMG, 0x5a);
1878
1879 if (intp->srch_algo[demod] == STV0900_COLD_START) {
1880 intp->bw[demod] += 10000000;
1881 intp->bw[demod] *= 15;
1882 intp->bw[demod] /= 10;
1883 } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1884 intp->bw[demod] += 10000000;
1885
1886 } else {
1887 stv0900_write_reg(intp, KREFTMG, 0xc1);
1888 intp->bw[demod] += 10000000;
1889 intp->bw[demod] *= 15;
1890 intp->bw[demod] /= 10;
1891 }
1892
1893 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1894
1895 stv0900_set_symbol_rate(intp, intp->mclk,
1896 intp->symbol_rate[demod], demod);
1897 stv0900_set_max_symbol_rate(intp, intp->mclk,
1898 intp->symbol_rate[demod], demod);
1899 stv0900_set_min_symbol_rate(intp, intp->mclk,
1900 intp->symbol_rate[demod], demod);
1901 if (intp->symbol_rate[demod] >= 10000000)
1902 low_sr = FALSE;
1903 else
1904 low_sr = TRUE;
1905
1906 }
1907
1908 if (intp->tuner_type[demod] == 3)
1909 stv0900_set_tuner_auto(intp, intp->freq[demod],
1910 intp->bw[demod], demod);
1911 else
1912 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
1913
1914 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1915 stv0900_get_bits(intp, AGCIQ_VALUE0));
1916
1917 aq_power = 0;
1918
1919 if (agc1_power == 0) {
1920 for (i = 0; i < 5; i++)
1921 aq_power += (stv0900_get_bits(intp, POWER_I) +
1922 stv0900_get_bits(intp, POWER_Q)) / 2;
1923
1924 aq_power /= 5;
1925 }
1926
1927 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
1928 intp->result[demod].locked = FALSE;
1929 signal_type = STV0900_NOAGC1;
1930 dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1931 } else {
1932 stv0900_write_bits(intp, SPECINV_CONTROL,
1933 intp->srch_iq_inv[demod]);
1934 if (intp->chip_id <= 0x20) /*cut 2.0*/
1935 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1936 else /*cut 3.0*/
1937 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
1938
1939 stv0900_set_search_standard(intp, demod);
1940
1941 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1942 stv0900_start_search(intp, demod);
1943 }
1944
1945 if (signal_type == STV0900_NOAGC1)
1946 return signal_type;
1947
1948 if (intp->chip_id == 0x12) {
1949 stv0900_write_bits(intp, RST_HWARE, 0);
1950 msleep(3);
1951 stv0900_write_bits(intp, RST_HWARE, 1);
1952 stv0900_write_bits(intp, RST_HWARE, 0);
1953 }
1954
1955 if (algo == STV0900_BLIND_SEARCH)
1956 lock = stv0900_blind_search_algo(fe);
1957 else if (algo == STV0900_COLD_START)
1958 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
1959 else if (algo == STV0900_WARM_START)
1960 lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
1961
1962 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
1963 if (low_sr == FALSE) {
1964 if (stv0900_check_timing_lock(intp, demod) == TRUE)
1965 lock = stv0900_sw_algo(intp, demod);
1966 }
1967 }
1968
1969 if (lock == TRUE)
1970 signal_type = stv0900_get_signal_params(fe);
1971
1972 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
1973 stv0900_track_optimization(fe);
1974 if (intp->chip_id <= 0x11) {
1975 if ((stv0900_get_standard(fe, 0) ==
1976 STV0900_DVBS1_STANDARD) &&
1977 (stv0900_get_standard(fe, 1) ==
1978 STV0900_DVBS1_STANDARD)) {
1979 msleep(20);
1980 stv0900_write_bits(intp, RST_HWARE, 0);
1981 } else {
1982 stv0900_write_bits(intp, RST_HWARE, 0);
1983 msleep(3);
1984 stv0900_write_bits(intp, RST_HWARE, 1);
1985 stv0900_write_bits(intp, RST_HWARE, 0);
1986 }
1987
1988 } else if (intp->chip_id >= 0x20) {
1989 stv0900_write_bits(intp, RST_HWARE, 0);
1990 msleep(3);
1991 stv0900_write_bits(intp, RST_HWARE, 1);
1992 stv0900_write_bits(intp, RST_HWARE, 0);
1993 }
1994
1995 if (stv0900_wait_for_lock(intp, demod,
1996 fec_timeout, fec_timeout) == TRUE) {
1997 lock = TRUE;
1998 intp->result[demod].locked = TRUE;
1999 if (intp->result[demod].standard ==
2000 STV0900_DVBS2_STANDARD) {
2001 stv0900_set_dvbs2_rolloff(intp, demod);
2002 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
2003 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
2004 stv0900_write_reg(intp, ERRCTRL1, 0x67);
2005 } else {
2006 stv0900_write_reg(intp, ERRCTRL1, 0x75);
2007 }
2008
2009 stv0900_write_reg(intp, FBERCPT4, 0);
2010 stv0900_write_reg(intp, ERRCTRL2, 0xc1);
2011 } else {
2012 lock = FALSE;
2013 signal_type = STV0900_NODATA;
2014 no_signal = stv0900_check_signal_presence(intp, demod);
2015
2016 intp->result[demod].locked = FALSE;
2017 }
2018 }
2019
2020 if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
2021 return signal_type;
2022
2023 if (intp->chip_id > 0x11) {
2024 intp->result[demod].locked = FALSE;
2025 return signal_type;
2026 }
2027
2028 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
2029 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
2030 signal_type = stv0900_dvbs1_acq_workaround(fe);
2031
2032 return signal_type;
2033 }
2034