staging: brcm80211: remove wl_ops_set_rts_threshold
[zen-stable.git] / arch / blackfin / mach-common / arch_checks.c
blobd8643fdd0fcf1d9ccc7812c7a46c9fd822d08213
1 /*
2 * Do some checking to make sure things are OK
4 * Copyright 2007-2010 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
9 #include <asm/fixed_code.h>
10 #include <mach/anomaly.h>
11 #include <asm/clocks.h>
13 #ifdef CONFIG_BFIN_KERNEL_CLOCK
15 # if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
16 # error "VCO selected is more than maximum value. Please change the VCO multipler"
17 # endif
19 # if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
20 # error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
21 # endif
23 # if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
24 # error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
25 # endif
27 # if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
28 # error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
29 # endif
31 # if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
32 # error "Please select sclk less than cclk"
33 # endif
35 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
37 #if CONFIG_BOOT_LOAD < FIXED_CODE_END
38 # error "The kernel load address must be after the fixed code section"
39 #endif
41 #if (CONFIG_BOOT_LOAD & 0x3)
42 # error "The kernel load address must be 4 byte aligned"
43 #endif
45 /* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
46 #if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
47 # error "The kernel load address is too high; keep it below 10meg for safety"
48 #endif
50 #if ANOMALY_05000263 && defined(CONFIG_MPU)
51 # error the MPU will not function safely while Anomaly 05000263 applies
52 #endif
54 #if ANOMALY_05000448
55 # error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
56 #endif
58 /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
59 #if ANOMALY_05000220 && \
60 (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK))
61 # error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
62 #endif
64 #if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1)
65 # error You need IFLUSH in L1 inst while Anomaly 05000491 applies
66 #endif