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procfs: do not confuse jiffies with cputime64_t
[zen-stable.git] / drivers / isdn / hardware / mISDN / hfc_multi.h
blob0c773866efc7babb16ab2d604dca334a9b62d0d5
1 /*
2 * see notice in hfc_multi.c
3 */
4
5 #define DEBUG_HFCMULTI_FIFO 0x00010000
6 #define DEBUG_HFCMULTI_CRC 0x00020000
7 #define DEBUG_HFCMULTI_INIT 0x00040000
8 #define DEBUG_HFCMULTI_PLXSD 0x00080000
9 #define DEBUG_HFCMULTI_MODE 0x00100000
10 #define DEBUG_HFCMULTI_MSG 0x00200000
11 #define DEBUG_HFCMULTI_STATE 0x00400000
12 #define DEBUG_HFCMULTI_FILL 0x00800000
13 #define DEBUG_HFCMULTI_SYNC 0x01000000
14 #define DEBUG_HFCMULTI_DTMF 0x02000000
15 #define DEBUG_HFCMULTI_LOCK 0x80000000
16
17 #define PCI_ENA_REGIO 0x01
18 #define PCI_ENA_MEMIO 0x02
19
20 #define XHFC_IRQ 4 /* SIU_IRQ2 */
21 #define XHFC_MEMBASE 0xFE000000
22 #define XHFC_MEMSIZE 0x00001000
23 #define XHFC_OFFSET 0x00001000
24 #define PA_XHFC_A0 0x0020 /* PA10 */
25 #define PB_XHFC_IRQ1 0x00000100 /* PB23 */
26 #define PB_XHFC_IRQ2 0x00000200 /* PB22 */
27 #define PB_XHFC_IRQ3 0x00000400 /* PB21 */
28 #define PB_XHFC_IRQ4 0x00000800 /* PB20 */
29
30 /*
31 * NOTE: some registers are assigned multiple times due to different modes
32 * also registers are assigned differen for HFC-4s/8s and HFC-E1
33 */
34
35 /*
36 #define MAX_FRAME_SIZE 2048
37 */
38
39 struct hfc_chan {
40 struct dchannel *dch; /* link if channel is a D-channel */
41 struct bchannel *bch; /* link if channel is a B-channel */
42 int port; /* the interface port this */
43 /* channel is associated with */
44 int nt_timer; /* -1 if off, 0 if elapsed, >0 if running */
45 int los, ais, slip_tx, slip_rx, rdi; /* current alarms */
46 int jitter;
47 u_long cfg; /* port configuration */
48 int sync; /* sync state (used by E1) */
49 u_int protocol; /* current protocol */
50 int slot_tx; /* current pcm slot */
51 int bank_tx; /* current pcm bank */
52 int slot_rx;
53 int bank_rx;
54 int conf; /* conference setting of TX slot */
55 int txpending; /* if there is currently data in */
56 /* the FIFO 0=no, 1=yes, 2=splloop */
57 int Zfill; /* rx-fifo level on last hfcmulti_tx */
58 int rx_off; /* set to turn fifo receive off */
59 int coeff_count; /* curren coeff block */
60 s32 *coeff; /* memory pointer to 8 coeff blocks */
61 };
62
63
64 struct hfcm_hw {
65 u_char r_ctrl;
66 u_char r_irq_ctrl;
67 u_char r_cirm;
68 u_char r_ram_sz;
69 u_char r_pcm_md0;
70 u_char r_irqmsk_misc;
71 u_char r_dtmf;
72 u_char r_st_sync;
73 u_char r_sci_msk;
74 u_char r_tx0, r_tx1;
75 u_char a_st_ctrl0[8];
76 u_char r_bert_wd_md;
77 timer_t timer;
78 };
79
80
81 /* for each stack these flags are used (cfg) */
82 #define HFC_CFG_NONCAP_TX 1 /* S/T TX interface has less capacity */
83 #define HFC_CFG_DIS_ECHANNEL 2 /* disable E-channel processing */
84 #define HFC_CFG_REG_ECHANNEL 3 /* register E-channel */
85 #define HFC_CFG_OPTICAL 4 /* the E1 interface is optical */
86 #define HFC_CFG_REPORT_LOS 5 /* the card should report loss of signal */
87 #define HFC_CFG_REPORT_AIS 6 /* the card should report alarm ind. sign. */
88 #define HFC_CFG_REPORT_SLIP 7 /* the card should report bit slips */
89 #define HFC_CFG_REPORT_RDI 8 /* the card should report remote alarm */
90 #define HFC_CFG_DTMF 9 /* enable DTMF-detection */
91 #define HFC_CFG_CRC4 10 /* disable CRC-4 Multiframe mode, */
92 /* use double frame instead. */
93
94 #define HFC_TYPE_E1 1 /* controller is HFC-E1 */
95 #define HFC_TYPE_4S 4 /* controller is HFC-4S */
96 #define HFC_TYPE_8S 8 /* controller is HFC-8S */
97 #define HFC_TYPE_XHFC 5 /* controller is XHFC */
98
99 #define HFC_CHIP_EXRAM_128 0 /* external ram 128k */
100 #define HFC_CHIP_EXRAM_512 1 /* external ram 256k */
101 #define HFC_CHIP_REVISION0 2 /* old fifo handling */
102 #define HFC_CHIP_PCM_SLAVE 3 /* PCM is slave */
103 #define HFC_CHIP_PCM_MASTER 4 /* PCM is master */
104 #define HFC_CHIP_RX_SYNC 5 /* disable pll sync for pcm */
105 #define HFC_CHIP_DTMF 6 /* DTMF decoding is enabled */
106 #define HFC_CHIP_CONF 7 /* conference handling is enabled */
107 #define HFC_CHIP_ULAW 8 /* ULAW mode */
108 #define HFC_CHIP_CLOCK2 9 /* double clock mode */
109 #define HFC_CHIP_E1CLOCK_GET 10 /* always get clock from E1 interface */
110 #define HFC_CHIP_E1CLOCK_PUT 11 /* always put clock from E1 interface */
111 #define HFC_CHIP_WATCHDOG 12 /* whether we should send signals */
112 /* to the watchdog */
113 #define HFC_CHIP_B410P 13 /* whether we have a b410p with echocan in */
114 /* hw */
115 #define HFC_CHIP_PLXSD 14 /* whether we have a Speech-Design PLX */
116 #define HFC_CHIP_EMBSD 15 /* whether we have a SD Embedded board */
117
118 #define HFC_IO_MODE_PCIMEM 0x00 /* normal memory mapped IO */
119 #define HFC_IO_MODE_REGIO 0x01 /* PCI io access */
120 #define HFC_IO_MODE_PLXSD 0x02 /* access HFC via PLX9030 */
121 #define HFC_IO_MODE_EMBSD 0x03 /* direct access */
122
123 /* table entry in the PCI devices list */
124 struct hm_map {
125 char *vendor_name;
126 char *card_name;
127 int type;
128 int ports;
129 int clock2;
130 int leds;
131 int opticalsupport;
132 int dip_type;
133 int io_mode;
134 int irq;
135 };
136
137 struct hfc_multi {
138 struct list_head list;
139 struct hm_map *mtyp;
140 int id;
141 int pcm; /* id of pcm bus */
142 int ctype; /* controller type */
143 int ports;
144
145 u_int irq; /* irq used by card */
146 u_int irqcnt;
147 struct pci_dev *pci_dev;
148 int io_mode; /* selects mode */
149 #ifdef HFC_REGISTER_DEBUG
150 void (*HFC_outb)(struct hfc_multi *hc, u_char reg,
151 u_char val, const char *function, int line);
152 void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,
153 u_char val, const char *function, int line);
154 u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg,
155 const char *function, int line);
156 u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg,
157 const char *function, int line);
158 u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg,
159 const char *function, int line);
160 u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg,
161 const char *function, int line);
162 void (*HFC_wait)(struct hfc_multi *hc,
163 const char *function, int line);
164 void (*HFC_wait_nodebug)(struct hfc_multi *hc,
165 const char *function, int line);
166 #else
167 void (*HFC_outb)(struct hfc_multi *hc, u_char reg,
168 u_char val);
169 void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,
170 u_char val);
171 u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg);
172 u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg);
173 u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg);
174 u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg);
175 void (*HFC_wait)(struct hfc_multi *hc);
176 void (*HFC_wait_nodebug)(struct hfc_multi *hc);
177 #endif
178 void (*read_fifo)(struct hfc_multi *hc, u_char *data,
179 int len);
180 void (*write_fifo)(struct hfc_multi *hc, u_char *data,
181 int len);
182 u_long pci_origmembase, plx_origmembase;
183 void __iomem *pci_membase; /* PCI memory */
184 void __iomem *plx_membase; /* PLX memory */
185 u_long xhfc_origmembase;
186 u_char *xhfc_membase;
187 u_long *xhfc_memaddr, *xhfc_memdata;
188 #ifdef CONFIG_MISDN_HFCMULTI_8xx
189 struct immap *immap;
190 #endif
191 u_long pb_irqmsk; /* Portbit mask to check the IRQ line */
192 u_long pci_iobase; /* PCI IO */
193 struct hfcm_hw hw; /* remember data of write-only-registers */
194
195 u_long chip; /* chip configuration */
196 int masterclk; /* port that provides master clock -1=off */
197 unsigned char silence;/* silence byte */
198 unsigned char silence_data[128];/* silence block */
199 int dtmf; /* flag that dtmf is currently in process */
200 int Flen; /* F-buffer size */
201 int Zlen; /* Z-buffer size (must be int for calculation)*/
202 int max_trans; /* maximum transparent fifo fill */
203 int Zmin; /* Z-buffer offset */
204 int DTMFbase; /* base address of DTMF coefficients */
205
206 u_int slots; /* number of PCM slots */
207 u_int leds; /* type of leds */
208 u_int ledcount; /* used to animate leds */
209 u_long ledstate; /* save last state of leds */
210 int opticalsupport; /* has the e1 board */
211 /* an optical Interface */
212 int dslot; /* channel # of d-channel (E1) default 16 */
213
214 u_long wdcount; /* every 500 ms we need to */
215 /* send the watchdog a signal */
216 u_char wdbyte; /* watchdog toggle byte */
217 u_int activity[8]; /* if there is any action on this */
218 /* port (will be cleared after */
219 /* showing led-states) */
220 int e1_state; /* keep track of last state */
221 int e1_getclock; /* if sync is retrieved from interface */
222 int syncronized; /* keep track of existing sync interface */
223 int e1_resync; /* resync jobs */
224
225 spinlock_t lock; /* the lock */
226
227 struct mISDNclock *iclock; /* isdn clock support */
228 int iclock_on;
229
230 /*
231 * the channel index is counted from 0, regardless where the channel
232 * is located on the hfc-channel.
233 * the bch->channel is equvalent to the hfc-channel
234 */
235 struct hfc_chan chan[32];
236 u_char created[8]; /* what port is created */
237 signed char slot_owner[256]; /* owner channel of slot */
238 };
239
240 /* PLX GPIOs */
241 #define PLX_GPIO4_DIR_BIT 13
242 #define PLX_GPIO4_BIT 14
243 #define PLX_GPIO5_DIR_BIT 16
244 #define PLX_GPIO5_BIT 17
245 #define PLX_GPIO6_DIR_BIT 19
246 #define PLX_GPIO6_BIT 20
247 #define PLX_GPIO7_DIR_BIT 22
248 #define PLX_GPIO7_BIT 23
249 #define PLX_GPIO8_DIR_BIT 25
250 #define PLX_GPIO8_BIT 26
251
252 #define PLX_GPIO4 (1 << PLX_GPIO4_BIT)
253 #define PLX_GPIO5 (1 << PLX_GPIO5_BIT)
254 #define PLX_GPIO6 (1 << PLX_GPIO6_BIT)
255 #define PLX_GPIO7 (1 << PLX_GPIO7_BIT)
256 #define PLX_GPIO8 (1 << PLX_GPIO8_BIT)
257
258 #define PLX_GPIO4_DIR (1 << PLX_GPIO4_DIR_BIT)
259 #define PLX_GPIO5_DIR (1 << PLX_GPIO5_DIR_BIT)
260 #define PLX_GPIO6_DIR (1 << PLX_GPIO6_DIR_BIT)
261 #define PLX_GPIO7_DIR (1 << PLX_GPIO7_DIR_BIT)
262 #define PLX_GPIO8_DIR (1 << PLX_GPIO8_DIR_BIT)
263
264 #define PLX_TERM_ON PLX_GPIO7
265 #define PLX_SLAVE_EN_N PLX_GPIO5
266 #define PLX_MASTER_EN PLX_GPIO6
267 #define PLX_SYNC_O_EN PLX_GPIO4
268 #define PLX_DSP_RES_N PLX_GPIO8
269 /* GPIO4..8 Enable & Set to OUT, SLAVE_EN_N = 1 */
270 #define PLX_GPIOC_INIT (PLX_GPIO4_DIR | PLX_GPIO5_DIR | PLX_GPIO6_DIR \
271 | PLX_GPIO7_DIR | PLX_GPIO8_DIR | PLX_SLAVE_EN_N)
272
273 /* PLX Interrupt Control/STATUS */
274 #define PLX_INTCSR_LINTI1_ENABLE 0x01
275 #define PLX_INTCSR_LINTI1_STATUS 0x04
276 #define PLX_INTCSR_LINTI2_ENABLE 0x08
277 #define PLX_INTCSR_LINTI2_STATUS 0x20
278 #define PLX_INTCSR_PCIINT_ENABLE 0x40
279
280 /* PLX Registers */
281 #define PLX_INTCSR 0x4c
282 #define PLX_CNTRL 0x50
283 #define PLX_GPIOC 0x54
284
285
286 /*
287 * REGISTER SETTING FOR HFC-4S/8S AND HFC-E1
288 */
289
290 /* write only registers */
291 #define R_CIRM 0x00
292 #define R_CTRL 0x01
293 #define R_BRG_PCM_CFG 0x02
294 #define R_RAM_ADDR0 0x08
295 #define R_RAM_ADDR1 0x09
296 #define R_RAM_ADDR2 0x0A
297 #define R_FIRST_FIFO 0x0B
298 #define R_RAM_SZ 0x0C
299 #define R_FIFO_MD 0x0D
300 #define R_INC_RES_FIFO 0x0E
301 #define R_FSM_IDX 0x0F
302 #define R_FIFO 0x0F
303 #define R_SLOT 0x10
304 #define R_IRQMSK_MISC 0x11
305 #define R_SCI_MSK 0x12
306 #define R_IRQ_CTRL 0x13
307 #define R_PCM_MD0 0x14
308 #define R_PCM_MD1 0x15
309 #define R_PCM_MD2 0x15
310 #define R_SH0H 0x15
311 #define R_SH1H 0x15
312 #define R_SH0L 0x15
313 #define R_SH1L 0x15
314 #define R_SL_SEL0 0x15
315 #define R_SL_SEL1 0x15
316 #define R_SL_SEL2 0x15
317 #define R_SL_SEL3 0x15
318 #define R_SL_SEL4 0x15
319 #define R_SL_SEL5 0x15
320 #define R_SL_SEL6 0x15
321 #define R_SL_SEL7 0x15
322 #define R_ST_SEL 0x16
323 #define R_ST_SYNC 0x17
324 #define R_CONF_EN 0x18
325 #define R_TI_WD 0x1A
326 #define R_BERT_WD_MD 0x1B
327 #define R_DTMF 0x1C
328 #define R_DTMF_N 0x1D
329 #define R_E1_WR_STA 0x20
330 #define R_E1_RD_STA 0x20
331 #define R_LOS0 0x22
332 #define R_LOS1 0x23
333 #define R_RX0 0x24
334 #define R_RX_FR0 0x25
335 #define R_RX_FR1 0x26
336 #define R_TX0 0x28
337 #define R_TX1 0x29
338 #define R_TX_FR0 0x2C
339
340 #define R_TX_FR1 0x2D
341 #define R_TX_FR2 0x2E
342 #define R_JATT_ATT 0x2F /* undocumented */
343 #define A_ST_RD_STATE 0x30
344 #define A_ST_WR_STATE 0x30
345 #define R_RX_OFF 0x30
346 #define A_ST_CTRL0 0x31
347 #define R_SYNC_OUT 0x31
348 #define A_ST_CTRL1 0x32
349 #define A_ST_CTRL2 0x33
350 #define A_ST_SQ_WR 0x34
351 #define R_TX_OFF 0x34
352 #define R_SYNC_CTRL 0x35
353 #define A_ST_CLK_DLY 0x37
354 #define R_PWM0 0x38
355 #define R_PWM1 0x39
356 #define A_ST_B1_TX 0x3C
357 #define A_ST_B2_TX 0x3D
358 #define A_ST_D_TX 0x3E
359 #define R_GPIO_OUT0 0x40
360 #define R_GPIO_OUT1 0x41
361 #define R_GPIO_EN0 0x42
362 #define R_GPIO_EN1 0x43
363 #define R_GPIO_SEL 0x44
364 #define R_BRG_CTRL 0x45
365 #define R_PWM_MD 0x46
366 #define R_BRG_MD 0x47
367 #define R_BRG_TIM0 0x48
368 #define R_BRG_TIM1 0x49
369 #define R_BRG_TIM2 0x4A
370 #define R_BRG_TIM3 0x4B
371 #define R_BRG_TIM_SEL01 0x4C
372 #define R_BRG_TIM_SEL23 0x4D
373 #define R_BRG_TIM_SEL45 0x4E
374 #define R_BRG_TIM_SEL67 0x4F
375 #define A_SL_CFG 0xD0
376 #define A_CONF 0xD1
377 #define A_CH_MSK 0xF4
378 #define A_CON_HDLC 0xFA
379 #define A_SUBCH_CFG 0xFB
380 #define A_CHANNEL 0xFC
381 #define A_FIFO_SEQ 0xFD
382 #define A_IRQ_MSK 0xFF
383
384 /* read only registers */
385 #define A_Z12 0x04
386 #define A_Z1L 0x04
387 #define A_Z1 0x04
388 #define A_Z1H 0x05
389 #define A_Z2L 0x06
390 #define A_Z2 0x06
391 #define A_Z2H 0x07
392 #define A_F1 0x0C
393 #define A_F12 0x0C
394 #define A_F2 0x0D
395 #define R_IRQ_OVIEW 0x10
396 #define R_IRQ_MISC 0x11
397 #define R_IRQ_STATECH 0x12
398 #define R_CONF_OFLOW 0x14
399 #define R_RAM_USE 0x15
400 #define R_CHIP_ID 0x16
401 #define R_BERT_STA 0x17
402 #define R_F0_CNTL 0x18
403 #define R_F0_CNTH 0x19
404 #define R_BERT_EC 0x1A
405 #define R_BERT_ECL 0x1A
406 #define R_BERT_ECH 0x1B
407 #define R_STATUS 0x1C
408 #define R_CHIP_RV 0x1F
409 #define R_STATE 0x20
410 #define R_SYNC_STA 0x24
411 #define R_RX_SL0_0 0x25
412 #define R_RX_SL0_1 0x26
413 #define R_RX_SL0_2 0x27
414 #define R_JATT_DIR 0x2b /* undocumented */
415 #define R_SLIP 0x2c
416 #define A_ST_RD_STA 0x30
417 #define R_FAS_EC 0x30
418 #define R_FAS_ECL 0x30
419 #define R_FAS_ECH 0x31
420 #define R_VIO_EC 0x32
421 #define R_VIO_ECL 0x32
422 #define R_VIO_ECH 0x33
423 #define A_ST_SQ_RD 0x34
424 #define R_CRC_EC 0x34
425 #define R_CRC_ECL 0x34
426 #define R_CRC_ECH 0x35
427 #define R_E_EC 0x36
428 #define R_E_ECL 0x36
429 #define R_E_ECH 0x37
430 #define R_SA6_SA13_EC 0x38
431 #define R_SA6_SA13_ECL 0x38
432 #define R_SA6_SA13_ECH 0x39
433 #define R_SA6_SA23_EC 0x3A
434 #define R_SA6_SA23_ECL 0x3A
435 #define R_SA6_SA23_ECH 0x3B
436 #define A_ST_B1_RX 0x3C
437 #define A_ST_B2_RX 0x3D
438 #define A_ST_D_RX 0x3E
439 #define A_ST_E_RX 0x3F
440 #define R_GPIO_IN0 0x40
441 #define R_GPIO_IN1 0x41
442 #define R_GPI_IN0 0x44
443 #define R_GPI_IN1 0x45
444 #define R_GPI_IN2 0x46
445 #define R_GPI_IN3 0x47
446 #define R_INT_DATA 0x88
447 #define R_IRQ_FIFO_BL0 0xC8
448 #define R_IRQ_FIFO_BL1 0xC9
449 #define R_IRQ_FIFO_BL2 0xCA
450 #define R_IRQ_FIFO_BL3 0xCB
451 #define R_IRQ_FIFO_BL4 0xCC
452 #define R_IRQ_FIFO_BL5 0xCD
453 #define R_IRQ_FIFO_BL6 0xCE
454 #define R_IRQ_FIFO_BL7 0xCF
455
456 /* read and write registers */
457 #define A_FIFO_DATA0 0x80
458 #define A_FIFO_DATA1 0x80
459 #define A_FIFO_DATA2 0x80
460 #define A_FIFO_DATA0_NOINC 0x84
461 #define A_FIFO_DATA1_NOINC 0x84
462 #define A_FIFO_DATA2_NOINC 0x84
463 #define R_RAM_DATA 0xC0
464
465
466 /*
467 * BIT SETTING FOR HFC-4S/8S AND HFC-E1
468 */
469
470 /* chapter 2: universal bus interface */
471 /* R_CIRM */
472 #define V_IRQ_SEL 0x01
473 #define V_SRES 0x08
474 #define V_HFCRES 0x10
475 #define V_PCMRES 0x20
476 #define V_STRES 0x40
477 #define V_ETRES 0x40
478 #define V_RLD_EPR 0x80
479 /* R_CTRL */
480 #define V_FIFO_LPRIO 0x02
481 #define V_SLOW_RD 0x04
482 #define V_EXT_RAM 0x08
483 #define V_CLK_OFF 0x20
484 #define V_ST_CLK 0x40
485 /* R_RAM_ADDR0 */
486 #define V_RAM_ADDR2 0x01
487 #define V_ADDR_RES 0x40
488 #define V_ADDR_INC 0x80
489 /* R_RAM_SZ */
490 #define V_RAM_SZ 0x01
491 #define V_PWM0_16KHZ 0x10
492 #define V_PWM1_16KHZ 0x20
493 #define V_FZ_MD 0x80
494 /* R_CHIP_ID */
495 #define V_PNP_IRQ 0x01
496 #define V_CHIP_ID 0x10
497
498 /* chapter 3: data flow */
499 /* R_FIRST_FIFO */
500 #define V_FIRST_FIRO_DIR 0x01
501 #define V_FIRST_FIFO_NUM 0x02
502 /* R_FIFO_MD */
503 #define V_FIFO_MD 0x01
504 #define V_CSM_MD 0x04
505 #define V_FSM_MD 0x08
506 #define V_FIFO_SZ 0x10
507 /* R_FIFO */
508 #define V_FIFO_DIR 0x01
509 #define V_FIFO_NUM 0x02
510 #define V_REV 0x80
511 /* R_SLOT */
512 #define V_SL_DIR 0x01
513 #define V_SL_NUM 0x02
514 /* A_SL_CFG */
515 #define V_CH_DIR 0x01
516 #define V_CH_SEL 0x02
517 #define V_ROUTING 0x40
518 /* A_CON_HDLC */
519 #define V_IFF 0x01
520 #define V_HDLC_TRP 0x02
521 #define V_TRP_IRQ 0x04
522 #define V_DATA_FLOW 0x20
523 /* A_SUBCH_CFG */
524 #define V_BIT_CNT 0x01
525 #define V_START_BIT 0x08
526 #define V_LOOP_FIFO 0x40
527 #define V_INV_DATA 0x80
528 /* A_CHANNEL */
529 #define V_CH_DIR0 0x01
530 #define V_CH_NUM0 0x02
531 /* A_FIFO_SEQ */
532 #define V_NEXT_FIFO_DIR 0x01
533 #define V_NEXT_FIFO_NUM 0x02
534 #define V_SEQ_END 0x40
535
536 /* chapter 4: FIFO handling and HDLC controller */
537 /* R_INC_RES_FIFO */
538 #define V_INC_F 0x01
539 #define V_RES_F 0x02
540 #define V_RES_LOST 0x04
541
542 /* chapter 5: S/T interface */
543 /* R_SCI_MSK */
544 #define V_SCI_MSK_ST0 0x01
545 #define V_SCI_MSK_ST1 0x02
546 #define V_SCI_MSK_ST2 0x04
547 #define V_SCI_MSK_ST3 0x08
548 #define V_SCI_MSK_ST4 0x10
549 #define V_SCI_MSK_ST5 0x20
550 #define V_SCI_MSK_ST6 0x40
551 #define V_SCI_MSK_ST7 0x80
552 /* R_ST_SEL */
553 #define V_ST_SEL 0x01
554 #define V_MULT_ST 0x08
555 /* R_ST_SYNC */
556 #define V_SYNC_SEL 0x01
557 #define V_AUTO_SYNC 0x08
558 /* A_ST_WR_STA */
559 #define V_ST_SET_STA 0x01
560 #define V_ST_LD_STA 0x10
561 #define V_ST_ACT 0x20
562 #define V_SET_G2_G3 0x80
563 /* A_ST_CTRL0 */
564 #define V_B1_EN 0x01
565 #define V_B2_EN 0x02
566 #define V_ST_MD 0x04
567 #define V_D_PRIO 0x08
568 #define V_SQ_EN 0x10
569 #define V_96KHZ 0x20
570 #define V_TX_LI 0x40
571 #define V_ST_STOP 0x80
572 /* A_ST_CTRL1 */
573 #define V_G2_G3_EN 0x01
574 #define V_D_HI 0x04
575 #define V_E_IGNO 0x08
576 #define V_E_LO 0x10
577 #define V_B12_SWAP 0x80
578 /* A_ST_CTRL2 */
579 #define V_B1_RX_EN 0x01
580 #define V_B2_RX_EN 0x02
581 #define V_ST_TRIS 0x40
582 /* A_ST_CLK_DLY */
583 #define V_ST_CK_DLY 0x01
584 #define V_ST_SMPL 0x10
585 /* A_ST_D_TX */
586 #define V_ST_D_TX 0x40
587 /* R_IRQ_STATECH */
588 #define V_SCI_ST0 0x01
589 #define V_SCI_ST1 0x02
590 #define V_SCI_ST2 0x04
591 #define V_SCI_ST3 0x08
592 #define V_SCI_ST4 0x10
593 #define V_SCI_ST5 0x20
594 #define V_SCI_ST6 0x40
595 #define V_SCI_ST7 0x80
596 /* A_ST_RD_STA */
597 #define V_ST_STA 0x01
598 #define V_FR_SYNC_ST 0x10
599 #define V_TI2_EXP 0x20
600 #define V_INFO0 0x40
601 #define V_G2_G3 0x80
602 /* A_ST_SQ_RD */
603 #define V_ST_SQ 0x01
604 #define V_MF_RX_RDY 0x10
605 #define V_MF_TX_RDY 0x80
606 /* A_ST_D_RX */
607 #define V_ST_D_RX 0x40
608 /* A_ST_E_RX */
609 #define V_ST_E_RX 0x40
610
611 /* chapter 5: E1 interface */
612 /* R_E1_WR_STA */
613 /* R_E1_RD_STA */
614 #define V_E1_SET_STA 0x01
615 #define V_E1_LD_STA 0x10
616 /* R_RX0 */
617 #define V_RX_CODE 0x01
618 #define V_RX_FBAUD 0x04
619 #define V_RX_CMI 0x08
620 #define V_RX_INV_CMI 0x10
621 #define V_RX_INV_CLK 0x20
622 #define V_RX_INV_DATA 0x40
623 #define V_AIS_ITU 0x80
624 /* R_RX_FR0 */
625 #define V_NO_INSYNC 0x01
626 #define V_AUTO_RESYNC 0x02
627 #define V_AUTO_RECO 0x04
628 #define V_SWORD_COND 0x08
629 #define V_SYNC_LOSS 0x10
630 #define V_XCRC_SYNC 0x20
631 #define V_MF_RESYNC 0x40
632 #define V_RESYNC 0x80
633 /* R_RX_FR1 */
634 #define V_RX_MF 0x01
635 #define V_RX_MF_SYNC 0x02
636 #define V_RX_SL0_RAM 0x04
637 #define V_ERR_SIM 0x20
638 #define V_RES_NMF 0x40
639 /* R_TX0 */
640 #define V_TX_CODE 0x01
641 #define V_TX_FBAUD 0x04
642 #define V_TX_CMI_CODE 0x08
643 #define V_TX_INV_CMI_CODE 0x10
644 #define V_TX_INV_CLK 0x20
645 #define V_TX_INV_DATA 0x40
646 #define V_OUT_EN 0x80
647 /* R_TX1 */
648 #define V_INV_CLK 0x01
649 #define V_EXCHG_DATA_LI 0x02
650 #define V_AIS_OUT 0x04
651 #define V_ATX 0x20
652 #define V_NTRI 0x40
653 #define V_AUTO_ERR_RES 0x80
654 /* R_TX_FR0 */
655 #define V_TRP_FAS 0x01
656 #define V_TRP_NFAS 0x02
657 #define V_TRP_RAL 0x04
658 #define V_TRP_SA 0x08
659 /* R_TX_FR1 */
660 #define V_TX_FAS 0x01
661 #define V_TX_NFAS 0x02
662 #define V_TX_RAL 0x04
663 #define V_TX_SA 0x08
664 /* R_TX_FR2 */
665 #define V_TX_MF 0x01
666 #define V_TRP_SL0 0x02
667 #define V_TX_SL0_RAM 0x04
668 #define V_TX_E 0x10
669 #define V_NEG_E 0x20
670 #define V_XS12_ON 0x40
671 #define V_XS15_ON 0x80
672 /* R_RX_OFF */
673 #define V_RX_SZ 0x01
674 #define V_RX_INIT 0x04
675 /* R_SYNC_OUT */
676 #define V_SYNC_E1_RX 0x01
677 #define V_IPATS0 0x20
678 #define V_IPATS1 0x40
679 #define V_IPATS2 0x80
680 /* R_TX_OFF */
681 #define V_TX_SZ 0x01
682 #define V_TX_INIT 0x04
683 /* R_SYNC_CTRL */
684 #define V_EXT_CLK_SYNC 0x01
685 #define V_SYNC_OFFS 0x02
686 #define V_PCM_SYNC 0x04
687 #define V_NEG_CLK 0x08
688 #define V_HCLK 0x10
689 /*
690 #define V_JATT_AUTO_DEL 0x20
691 #define V_JATT_AUTO 0x40
692 */
693 #define V_JATT_OFF 0x80
694 /* R_STATE */
695 #define V_E1_STA 0x01
696 #define V_ALT_FR_RX 0x40
697 #define V_ALT_FR_TX 0x80
698 /* R_SYNC_STA */
699 #define V_RX_STA 0x01
700 #define V_FR_SYNC_E1 0x04
701 #define V_SIG_LOS 0x08
702 #define V_MFA_STA 0x10
703 #define V_AIS 0x40
704 #define V_NO_MF_SYNC 0x80
705 /* R_RX_SL0_0 */
706 #define V_SI_FAS 0x01
707 #define V_SI_NFAS 0x02
708 #define V_A 0x04
709 #define V_CRC_OK 0x08
710 #define V_TX_E1 0x10
711 #define V_TX_E2 0x20
712 #define V_RX_E1 0x40
713 #define V_RX_E2 0x80
714 /* R_SLIP */
715 #define V_SLIP_RX 0x01
716 #define V_FOSLIP_RX 0x08
717 #define V_SLIP_TX 0x10
718 #define V_FOSLIP_TX 0x80
719
720 /* chapter 6: PCM interface */
721 /* R_PCM_MD0 */
722 #define V_PCM_MD 0x01
723 #define V_C4_POL 0x02
724 #define V_F0_NEG 0x04
725 #define V_F0_LEN 0x08
726 #define V_PCM_ADDR 0x10
727 /* R_SL_SEL0 */
728 #define V_SL_SEL0 0x01
729 #define V_SH_SEL0 0x80
730 /* R_SL_SEL1 */
731 #define V_SL_SEL1 0x01
732 #define V_SH_SEL1 0x80
733 /* R_SL_SEL2 */
734 #define V_SL_SEL2 0x01
735 #define V_SH_SEL2 0x80
736 /* R_SL_SEL3 */
737 #define V_SL_SEL3 0x01
738 #define V_SH_SEL3 0x80
739 /* R_SL_SEL4 */
740 #define V_SL_SEL4 0x01
741 #define V_SH_SEL4 0x80
742 /* R_SL_SEL5 */
743 #define V_SL_SEL5 0x01
744 #define V_SH_SEL5 0x80
745 /* R_SL_SEL6 */
746 #define V_SL_SEL6 0x01
747 #define V_SH_SEL6 0x80
748 /* R_SL_SEL7 */
749 #define V_SL_SEL7 0x01
750 #define V_SH_SEL7 0x80
751 /* R_PCM_MD1 */
752 #define V_ODEC_CON 0x01
753 #define V_PLL_ADJ 0x04
754 #define V_PCM_DR 0x10
755 #define V_PCM_LOOP 0x40
756 /* R_PCM_MD2 */
757 #define V_SYNC_PLL 0x02
758 #define V_SYNC_SRC 0x04
759 #define V_SYNC_OUT 0x08
760 #define V_ICR_FR_TIME 0x40
761 #define V_EN_PLL 0x80
762
763 /* chapter 7: pulse width modulation */
764 /* R_PWM_MD */
765 #define V_EXT_IRQ_EN 0x08
766 #define V_PWM0_MD 0x10
767 #define V_PWM1_MD 0x40
768
769 /* chapter 8: multiparty audio conferences */
770 /* R_CONF_EN */
771 #define V_CONF_EN 0x01
772 #define V_ULAW 0x80
773 /* A_CONF */
774 #define V_CONF_NUM 0x01
775 #define V_NOISE_SUPPR 0x08
776 #define V_ATT_LEV 0x20
777 #define V_CONF_SL 0x80
778 /* R_CONF_OFLOW */
779 #define V_CONF_OFLOW0 0x01
780 #define V_CONF_OFLOW1 0x02
781 #define V_CONF_OFLOW2 0x04
782 #define V_CONF_OFLOW3 0x08
783 #define V_CONF_OFLOW4 0x10
784 #define V_CONF_OFLOW5 0x20
785 #define V_CONF_OFLOW6 0x40
786 #define V_CONF_OFLOW7 0x80
787
788 /* chapter 9: DTMF contoller */
789 /* R_DTMF0 */
790 #define V_DTMF_EN 0x01
791 #define V_HARM_SEL 0x02
792 #define V_DTMF_RX_CH 0x04
793 #define V_DTMF_STOP 0x08
794 #define V_CHBL_SEL 0x10
795 #define V_RST_DTMF 0x40
796 #define V_ULAW_SEL 0x80
797
798 /* chapter 10: BERT */
799 /* R_BERT_WD_MD */
800 #define V_PAT_SEQ 0x01
801 #define V_BERT_ERR 0x08
802 #define V_AUTO_WD_RES 0x20
803 #define V_WD_RES 0x80
804 /* R_BERT_STA */
805 #define V_BERT_SYNC_SRC 0x01
806 #define V_BERT_SYNC 0x10
807 #define V_BERT_INV_DATA 0x20
808
809 /* chapter 11: auxiliary interface */
810 /* R_BRG_PCM_CFG */
811 #define V_BRG_EN 0x01
812 #define V_BRG_MD 0x02
813 #define V_PCM_CLK 0x20
814 #define V_ADDR_WRDLY 0x40
815 /* R_BRG_CTRL */
816 #define V_BRG_CS 0x01
817 #define V_BRG_ADDR 0x08
818 #define V_BRG_CS_SRC 0x80
819 /* R_BRG_MD */
820 #define V_BRG_MD0 0x01
821 #define V_BRG_MD1 0x02
822 #define V_BRG_MD2 0x04
823 #define V_BRG_MD3 0x08
824 #define V_BRG_MD4 0x10
825 #define V_BRG_MD5 0x20
826 #define V_BRG_MD6 0x40
827 #define V_BRG_MD7 0x80
828 /* R_BRG_TIM0 */
829 #define V_BRG_TIM0_IDLE 0x01
830 #define V_BRG_TIM0_CLK 0x10
831 /* R_BRG_TIM1 */
832 #define V_BRG_TIM1_IDLE 0x01
833 #define V_BRG_TIM1_CLK 0x10
834 /* R_BRG_TIM2 */
835 #define V_BRG_TIM2_IDLE 0x01
836 #define V_BRG_TIM2_CLK 0x10
837 /* R_BRG_TIM3 */
838 #define V_BRG_TIM3_IDLE 0x01
839 #define V_BRG_TIM3_CLK 0x10
840 /* R_BRG_TIM_SEL01 */
841 #define V_BRG_WR_SEL0 0x01
842 #define V_BRG_RD_SEL0 0x04
843 #define V_BRG_WR_SEL1 0x10
844 #define V_BRG_RD_SEL1 0x40
845 /* R_BRG_TIM_SEL23 */
846 #define V_BRG_WR_SEL2 0x01
847 #define V_BRG_RD_SEL2 0x04
848 #define V_BRG_WR_SEL3 0x10
849 #define V_BRG_RD_SEL3 0x40
850 /* R_BRG_TIM_SEL45 */
851 #define V_BRG_WR_SEL4 0x01
852 #define V_BRG_RD_SEL4 0x04
853 #define V_BRG_WR_SEL5 0x10
854 #define V_BRG_RD_SEL5 0x40
855 /* R_BRG_TIM_SEL67 */
856 #define V_BRG_WR_SEL6 0x01
857 #define V_BRG_RD_SEL6 0x04
858 #define V_BRG_WR_SEL7 0x10
859 #define V_BRG_RD_SEL7 0x40
860
861 /* chapter 12: clock, reset, interrupt, timer and watchdog */
862 /* R_IRQMSK_MISC */
863 #define V_STA_IRQMSK 0x01
864 #define V_TI_IRQMSK 0x02
865 #define V_PROC_IRQMSK 0x04
866 #define V_DTMF_IRQMSK 0x08
867 #define V_IRQ1S_MSK 0x10
868 #define V_SA6_IRQMSK 0x20
869 #define V_RX_EOMF_MSK 0x40
870 #define V_TX_EOMF_MSK 0x80
871 /* R_IRQ_CTRL */
872 #define V_FIFO_IRQ 0x01
873 #define V_GLOB_IRQ_EN 0x08
874 #define V_IRQ_POL 0x10
875 /* R_TI_WD */
876 #define V_EV_TS 0x01
877 #define V_WD_TS 0x10
878 /* A_IRQ_MSK */
879 #define V_IRQ 0x01
880 #define V_BERT_EN 0x02
881 #define V_MIX_IRQ 0x04
882 /* R_IRQ_OVIEW */
883 #define V_IRQ_FIFO_BL0 0x01
884 #define V_IRQ_FIFO_BL1 0x02
885 #define V_IRQ_FIFO_BL2 0x04
886 #define V_IRQ_FIFO_BL3 0x08
887 #define V_IRQ_FIFO_BL4 0x10
888 #define V_IRQ_FIFO_BL5 0x20
889 #define V_IRQ_FIFO_BL6 0x40
890 #define V_IRQ_FIFO_BL7 0x80
891 /* R_IRQ_MISC */
892 #define V_STA_IRQ 0x01
893 #define V_TI_IRQ 0x02
894 #define V_IRQ_PROC 0x04
895 #define V_DTMF_IRQ 0x08
896 #define V_IRQ1S 0x10
897 #define V_SA6_IRQ 0x20
898 #define V_RX_EOMF 0x40
899 #define V_TX_EOMF 0x80
900 /* R_STATUS */
901 #define V_BUSY 0x01
902 #define V_PROC 0x02
903 #define V_DTMF_STA 0x04
904 #define V_LOST_STA 0x08
905 #define V_SYNC_IN 0x10
906 #define V_EXT_IRQSTA 0x20
907 #define V_MISC_IRQSTA 0x40
908 #define V_FR_IRQSTA 0x80
909 /* R_IRQ_FIFO_BL0 */
910 #define V_IRQ_FIFO0_TX 0x01
911 #define V_IRQ_FIFO0_RX 0x02
912 #define V_IRQ_FIFO1_TX 0x04
913 #define V_IRQ_FIFO1_RX 0x08
914 #define V_IRQ_FIFO2_TX 0x10
915 #define V_IRQ_FIFO2_RX 0x20
916 #define V_IRQ_FIFO3_TX 0x40
917 #define V_IRQ_FIFO3_RX 0x80
918 /* R_IRQ_FIFO_BL1 */
919 #define V_IRQ_FIFO4_TX 0x01
920 #define V_IRQ_FIFO4_RX 0x02
921 #define V_IRQ_FIFO5_TX 0x04
922 #define V_IRQ_FIFO5_RX 0x08
923 #define V_IRQ_FIFO6_TX 0x10
924 #define V_IRQ_FIFO6_RX 0x20
925 #define V_IRQ_FIFO7_TX 0x40
926 #define V_IRQ_FIFO7_RX 0x80
927 /* R_IRQ_FIFO_BL2 */
928 #define V_IRQ_FIFO8_TX 0x01
929 #define V_IRQ_FIFO8_RX 0x02
930 #define V_IRQ_FIFO9_TX 0x04
931 #define V_IRQ_FIFO9_RX 0x08
932 #define V_IRQ_FIFO10_TX 0x10
933 #define V_IRQ_FIFO10_RX 0x20
934 #define V_IRQ_FIFO11_TX 0x40
935 #define V_IRQ_FIFO11_RX 0x80
936 /* R_IRQ_FIFO_BL3 */
937 #define V_IRQ_FIFO12_TX 0x01
938 #define V_IRQ_FIFO12_RX 0x02
939 #define V_IRQ_FIFO13_TX 0x04
940 #define V_IRQ_FIFO13_RX 0x08
941 #define V_IRQ_FIFO14_TX 0x10
942 #define V_IRQ_FIFO14_RX 0x20
943 #define V_IRQ_FIFO15_TX 0x40
944 #define V_IRQ_FIFO15_RX 0x80
945 /* R_IRQ_FIFO_BL4 */
946 #define V_IRQ_FIFO16_TX 0x01
947 #define V_IRQ_FIFO16_RX 0x02
948 #define V_IRQ_FIFO17_TX 0x04
949 #define V_IRQ_FIFO17_RX 0x08
950 #define V_IRQ_FIFO18_TX 0x10
951 #define V_IRQ_FIFO18_RX 0x20
952 #define V_IRQ_FIFO19_TX 0x40
953 #define V_IRQ_FIFO19_RX 0x80
954 /* R_IRQ_FIFO_BL5 */
955 #define V_IRQ_FIFO20_TX 0x01
956 #define V_IRQ_FIFO20_RX 0x02
957 #define V_IRQ_FIFO21_TX 0x04
958 #define V_IRQ_FIFO21_RX 0x08
959 #define V_IRQ_FIFO22_TX 0x10
960 #define V_IRQ_FIFO22_RX 0x20
961 #define V_IRQ_FIFO23_TX 0x40
962 #define V_IRQ_FIFO23_RX 0x80
963 /* R_IRQ_FIFO_BL6 */
964 #define V_IRQ_FIFO24_TX 0x01
965 #define V_IRQ_FIFO24_RX 0x02
966 #define V_IRQ_FIFO25_TX 0x04
967 #define V_IRQ_FIFO25_RX 0x08
968 #define V_IRQ_FIFO26_TX 0x10
969 #define V_IRQ_FIFO26_RX 0x20
970 #define V_IRQ_FIFO27_TX 0x40
971 #define V_IRQ_FIFO27_RX 0x80
972 /* R_IRQ_FIFO_BL7 */
973 #define V_IRQ_FIFO28_TX 0x01
974 #define V_IRQ_FIFO28_RX 0x02
975 #define V_IRQ_FIFO29_TX 0x04
976 #define V_IRQ_FIFO29_RX 0x08
977 #define V_IRQ_FIFO30_TX 0x10
978 #define V_IRQ_FIFO30_RX 0x20
979 #define V_IRQ_FIFO31_TX 0x40
980 #define V_IRQ_FIFO31_RX 0x80
981
982 /* chapter 13: general purpose I/O pins (GPIO) and input pins (GPI) */
983 /* R_GPIO_OUT0 */
984 #define V_GPIO_OUT0 0x01
985 #define V_GPIO_OUT1 0x02
986 #define V_GPIO_OUT2 0x04
987 #define V_GPIO_OUT3 0x08
988 #define V_GPIO_OUT4 0x10
989 #define V_GPIO_OUT5 0x20
990 #define V_GPIO_OUT6 0x40
991 #define V_GPIO_OUT7 0x80
992 /* R_GPIO_OUT1 */
993 #define V_GPIO_OUT8 0x01
994 #define V_GPIO_OUT9 0x02
995 #define V_GPIO_OUT10 0x04
996 #define V_GPIO_OUT11 0x08
997 #define V_GPIO_OUT12 0x10
998 #define V_GPIO_OUT13 0x20
999 #define V_GPIO_OUT14 0x40
1000 #define V_GPIO_OUT15 0x80
1001 /* R_GPIO_EN0 */
1002 #define V_GPIO_EN0 0x01
1003 #define V_GPIO_EN1 0x02
1004 #define V_GPIO_EN2 0x04
1005 #define V_GPIO_EN3 0x08
1006 #define V_GPIO_EN4 0x10
1007 #define V_GPIO_EN5 0x20
1008 #define V_GPIO_EN6 0x40
1009 #define V_GPIO_EN7 0x80
1010 /* R_GPIO_EN1 */
1011 #define V_GPIO_EN8 0x01
1012 #define V_GPIO_EN9 0x02
1013 #define V_GPIO_EN10 0x04
1014 #define V_GPIO_EN11 0x08
1015 #define V_GPIO_EN12 0x10
1016 #define V_GPIO_EN13 0x20
1017 #define V_GPIO_EN14 0x40
1018 #define V_GPIO_EN15 0x80
1019 /* R_GPIO_SEL */
1020 #define V_GPIO_SEL0 0x01
1021 #define V_GPIO_SEL1 0x02
1022 #define V_GPIO_SEL2 0x04
1023 #define V_GPIO_SEL3 0x08
1024 #define V_GPIO_SEL4 0x10
1025 #define V_GPIO_SEL5 0x20
1026 #define V_GPIO_SEL6 0x40
1027 #define V_GPIO_SEL7 0x80
1028 /* R_GPIO_IN0 */
1029 #define V_GPIO_IN0 0x01
1030 #define V_GPIO_IN1 0x02
1031 #define V_GPIO_IN2 0x04
1032 #define V_GPIO_IN3 0x08
1033 #define V_GPIO_IN4 0x10
1034 #define V_GPIO_IN5 0x20
1035 #define V_GPIO_IN6 0x40
1036 #define V_GPIO_IN7 0x80
1037 /* R_GPIO_IN1 */
1038 #define V_GPIO_IN8 0x01
1039 #define V_GPIO_IN9 0x02
1040 #define V_GPIO_IN10 0x04
1041 #define V_GPIO_IN11 0x08
1042 #define V_GPIO_IN12 0x10
1043 #define V_GPIO_IN13 0x20
1044 #define V_GPIO_IN14 0x40
1045 #define V_GPIO_IN15 0x80
1046 /* R_GPI_IN0 */
1047 #define V_GPI_IN0 0x01
1048 #define V_GPI_IN1 0x02
1049 #define V_GPI_IN2 0x04
1050 #define V_GPI_IN3 0x08
1051 #define V_GPI_IN4 0x10
1052 #define V_GPI_IN5 0x20
1053 #define V_GPI_IN6 0x40
1054 #define V_GPI_IN7 0x80
1055 /* R_GPI_IN1 */
1056 #define V_GPI_IN8 0x01
1057 #define V_GPI_IN9 0x02
1058 #define V_GPI_IN10 0x04
1059 #define V_GPI_IN11 0x08
1060 #define V_GPI_IN12 0x10
1061 #define V_GPI_IN13 0x20
1062 #define V_GPI_IN14 0x40
1063 #define V_GPI_IN15 0x80
1064 /* R_GPI_IN2 */
1065 #define V_GPI_IN16 0x01
1066 #define V_GPI_IN17 0x02
1067 #define V_GPI_IN18 0x04
1068 #define V_GPI_IN19 0x08
1069 #define V_GPI_IN20 0x10
1070 #define V_GPI_IN21 0x20
1071 #define V_GPI_IN22 0x40
1072 #define V_GPI_IN23 0x80
1073 /* R_GPI_IN3 */
1074 #define V_GPI_IN24 0x01
1075 #define V_GPI_IN25 0x02
1076 #define V_GPI_IN26 0x04
1077 #define V_GPI_IN27 0x08
1078 #define V_GPI_IN28 0x10
1079 #define V_GPI_IN29 0x20
1080 #define V_GPI_IN30 0x40
1081 #define V_GPI_IN31 0x80
1082
1083 /* map of all registers, used for debugging */
1084
1085 #ifdef HFC_REGISTER_DEBUG
1086 struct hfc_register_names {
1087 char *name;
1088 u_char reg;
1089 } hfc_register_names[] = {
1090 /* write registers */
1091 {"R_CIRM", 0x00},
1092 {"R_CTRL", 0x01},
1093 {"R_BRG_PCM_CFG ", 0x02},
1094 {"R_RAM_ADDR0", 0x08},
1095 {"R_RAM_ADDR1", 0x09},
1096 {"R_RAM_ADDR2", 0x0A},
1097 {"R_FIRST_FIFO", 0x0B},
1098 {"R_RAM_SZ", 0x0C},
1099 {"R_FIFO_MD", 0x0D},
1100 {"R_INC_RES_FIFO", 0x0E},
1101 {"R_FIFO / R_FSM_IDX", 0x0F},
1102 {"R_SLOT", 0x10},
1103 {"R_IRQMSK_MISC", 0x11},
1104 {"R_SCI_MSK", 0x12},
1105 {"R_IRQ_CTRL", 0x13},
1106 {"R_PCM_MD0", 0x14},
1107 {"R_0x15", 0x15},
1108 {"R_ST_SEL", 0x16},
1109 {"R_ST_SYNC", 0x17},
1110 {"R_CONF_EN", 0x18},
1111 {"R_TI_WD", 0x1A},
1112 {"R_BERT_WD_MD", 0x1B},
1113 {"R_DTMF", 0x1C},
1114 {"R_DTMF_N", 0x1D},
1115 {"R_E1_XX_STA", 0x20},
1116 {"R_LOS0", 0x22},
1117 {"R_LOS1", 0x23},
1118 {"R_RX0", 0x24},
1119 {"R_RX_FR0", 0x25},
1120 {"R_RX_FR1", 0x26},
1121 {"R_TX0", 0x28},
1122 {"R_TX1", 0x29},
1123 {"R_TX_FR0", 0x2C},
1124 {"R_TX_FR1", 0x2D},
1125 {"R_TX_FR2", 0x2E},
1126 {"R_JATT_ATT", 0x2F},
1127 {"A_ST_xx_STA/R_RX_OFF", 0x30},
1128 {"A_ST_CTRL0/R_SYNC_OUT", 0x31},
1129 {"A_ST_CTRL1", 0x32},
1130 {"A_ST_CTRL2", 0x33},
1131 {"A_ST_SQ_WR", 0x34},
1132 {"R_TX_OFF", 0x34},
1133 {"R_SYNC_CTRL", 0x35},
1134 {"A_ST_CLK_DLY", 0x37},
1135 {"R_PWM0", 0x38},
1136 {"R_PWM1", 0x39},
1137 {"A_ST_B1_TX", 0x3C},
1138 {"A_ST_B2_TX", 0x3D},
1139 {"A_ST_D_TX", 0x3E},
1140 {"R_GPIO_OUT0", 0x40},
1141 {"R_GPIO_OUT1", 0x41},
1142 {"R_GPIO_EN0", 0x42},
1143 {"R_GPIO_EN1", 0x43},
1144 {"R_GPIO_SEL", 0x44},
1145 {"R_BRG_CTRL", 0x45},
1146 {"R_PWM_MD", 0x46},
1147 {"R_BRG_MD", 0x47},
1148 {"R_BRG_TIM0", 0x48},
1149 {"R_BRG_TIM1", 0x49},
1150 {"R_BRG_TIM2", 0x4A},
1151 {"R_BRG_TIM3", 0x4B},
1152 {"R_BRG_TIM_SEL01", 0x4C},
1153 {"R_BRG_TIM_SEL23", 0x4D},
1154 {"R_BRG_TIM_SEL45", 0x4E},
1155 {"R_BRG_TIM_SEL67", 0x4F},
1156 {"A_FIFO_DATA0-2", 0x80},
1157 {"A_FIFO_DATA0-2_NOINC", 0x84},
1158 {"R_RAM_DATA", 0xC0},
1159 {"A_SL_CFG", 0xD0},
1160 {"A_CONF", 0xD1},
1161 {"A_CH_MSK", 0xF4},
1162 {"A_CON_HDLC", 0xFA},
1163 {"A_SUBCH_CFG", 0xFB},
1164 {"A_CHANNEL", 0xFC},
1165 {"A_FIFO_SEQ", 0xFD},
1166 {"A_IRQ_MSK", 0xFF},
1167 {NULL, 0},
1168
1169 /* read registers */
1170 {"A_Z1", 0x04},
1171 {"A_Z1H", 0x05},
1172 {"A_Z2", 0x06},
1173 {"A_Z2H", 0x07},
1174 {"A_F1", 0x0C},
1175 {"A_F2", 0x0D},
1176 {"R_IRQ_OVIEW", 0x10},
1177 {"R_IRQ_MISC", 0x11},
1178 {"R_IRQ_STATECH", 0x12},
1179 {"R_CONF_OFLOW", 0x14},
1180 {"R_RAM_USE", 0x15},
1181 {"R_CHIP_ID", 0x16},
1182 {"R_BERT_STA", 0x17},
1183 {"R_F0_CNTL", 0x18},
1184 {"R_F0_CNTH", 0x19},
1185 {"R_BERT_ECL", 0x1A},
1186 {"R_BERT_ECH", 0x1B},
1187 {"R_STATUS", 0x1C},
1188 {"R_CHIP_RV", 0x1F},
1189 {"R_STATE", 0x20},
1190 {"R_SYNC_STA", 0x24},
1191 {"R_RX_SL0_0", 0x25},
1192 {"R_RX_SL0_1", 0x26},
1193 {"R_RX_SL0_2", 0x27},
1194 {"R_JATT_DIR", 0x2b},
1195 {"R_SLIP", 0x2c},
1196 {"A_ST_RD_STA", 0x30},
1197 {"R_FAS_ECL", 0x30},
1198 {"R_FAS_ECH", 0x31},
1199 {"R_VIO_ECL", 0x32},
1200 {"R_VIO_ECH", 0x33},
1201 {"R_CRC_ECL / A_ST_SQ_RD", 0x34},
1202 {"R_CRC_ECH", 0x35},
1203 {"R_E_ECL", 0x36},
1204 {"R_E_ECH", 0x37},
1205 {"R_SA6_SA13_ECL", 0x38},
1206 {"R_SA6_SA13_ECH", 0x39},
1207 {"R_SA6_SA23_ECL", 0x3A},
1208 {"R_SA6_SA23_ECH", 0x3B},
1209 {"A_ST_B1_RX", 0x3C},
1210 {"A_ST_B2_RX", 0x3D},
1211 {"A_ST_D_RX", 0x3E},
1212 {"A_ST_E_RX", 0x3F},
1213 {"R_GPIO_IN0", 0x40},
1214 {"R_GPIO_IN1", 0x41},
1215 {"R_GPI_IN0", 0x44},
1216 {"R_GPI_IN1", 0x45},
1217 {"R_GPI_IN2", 0x46},
1218 {"R_GPI_IN3", 0x47},
1219 {"A_FIFO_DATA0-2", 0x80},
1220 {"A_FIFO_DATA0-2_NOINC", 0x84},
1221 {"R_INT_DATA", 0x88},
1222 {"R_RAM_DATA", 0xC0},
1223 {"R_IRQ_FIFO_BL0", 0xC8},
1224 {"R_IRQ_FIFO_BL1", 0xC9},
1225 {"R_IRQ_FIFO_BL2", 0xCA},
1226 {"R_IRQ_FIFO_BL3", 0xCB},
1227 {"R_IRQ_FIFO_BL4", 0xCC},
1228 {"R_IRQ_FIFO_BL5", 0xCD},
1229 {"R_IRQ_FIFO_BL6", 0xCE},
1230 {"R_IRQ_FIFO_BL7", 0xCF},
1231 };
1232 #endif /* HFC_REGISTER_DEBUG */
1233