drivers/usb/host/pci-quirks.c

   1 /*
   2  * This file contains code to reset and initialize USB host controllers.
   3  * Some of it includes work-arounds for PCI hardware and BIOS quirks.
   4  * It may need to run early during booting -- before USB would normally
   5  * initialize -- to ensure that Linux doesn't use any legacy modes.
   6  *
   7  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
   8  *  (and others)
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/export.h>
  17 #include <linux/acpi.h>
  18 #include <linux/dmi.h>
  19 #include "pci-quirks.h"
  20 #include "xhci-ext-caps.h"
  21
  22
  23 #define UHCI_USBLEGSUP          0xc0            /* legacy support */
  24 #define UHCI_USBCMD             0               /* command register */
  25 #define UHCI_USBINTR            4               /* interrupt register */
  26 #define UHCI_USBLEGSUP_RWC      0x8f00          /* the R/WC bits */
  27 #define UHCI_USBLEGSUP_RO       0x5040          /* R/O and reserved bits */
  28 #define UHCI_USBCMD_RUN         0x0001          /* RUN/STOP bit */
  29 #define UHCI_USBCMD_HCRESET     0x0002          /* Host Controller reset */
  30 #define UHCI_USBCMD_EGSM        0x0008          /* Global Suspend Mode */
  31 #define UHCI_USBCMD_CONFIGURE   0x0040          /* Config Flag */
  32 #define UHCI_USBINTR_RESUME     0x0002          /* Resume interrupt enable */
  33
  34 #define OHCI_CONTROL            0x04
  35 #define OHCI_CMDSTATUS          0x08
  36 #define OHCI_INTRSTATUS         0x0c
  37 #define OHCI_INTRENABLE         0x10
  38 #define OHCI_INTRDISABLE        0x14
  39 #define OHCI_FMINTERVAL         0x34
  40 #define OHCI_HCFS               (3 << 6)        /* hc functional state */
  41 #define OHCI_HCR                (1 << 0)        /* host controller reset */
  42 #define OHCI_OCR                (1 << 3)        /* ownership change request */
  43 #define OHCI_CTRL_RWC           (1 << 9)        /* remote wakeup connected */
  44 #define OHCI_CTRL_IR            (1 << 8)        /* interrupt routing */
  45 #define OHCI_INTR_OC            (1 << 30)       /* ownership change */
  46
  47 #define EHCI_HCC_PARAMS         0x08            /* extended capabilities */
  48 #define EHCI_USBCMD             0               /* command register */
  49 #define EHCI_USBCMD_RUN         (1 << 0)        /* RUN/STOP bit */
  50 #define EHCI_USBSTS             4               /* status register */
  51 #define EHCI_USBSTS_HALTED      (1 << 12)       /* HCHalted bit */
  52 #define EHCI_USBINTR            8               /* interrupt register */
  53 #define EHCI_CONFIGFLAG         0x40            /* configured flag register */
  54 #define EHCI_USBLEGSUP          0               /* legacy support register */
  55 #define EHCI_USBLEGSUP_BIOS     (1 << 16)       /* BIOS semaphore */
  56 #define EHCI_USBLEGSUP_OS       (1 << 24)       /* OS semaphore */
  57 #define EHCI_USBLEGCTLSTS       4               /* legacy control/status */
  58 #define EHCI_USBLEGCTLSTS_SOOE  (1 << 13)       /* SMI on ownership change */
  59
  60 /* AMD quirk use */
  61 #define AB_REG_BAR_LOW          0xe0
  62 #define AB_REG_BAR_HIGH         0xe1
  63 #define AB_REG_BAR_SB700        0xf0
  64 #define AB_INDX(addr)           ((addr) + 0x00)
  65 #define AB_DATA(addr)           ((addr) + 0x04)
  66 #define AX_INDXC                0x30
  67 #define AX_DATAC                0x34
  68
  69 #define NB_PCIE_INDX_ADDR       0xe0
  70 #define NB_PCIE_INDX_DATA       0xe4
  71 #define PCIE_P_CNTL             0x10040
  72 #define BIF_NB                  0x10002
  73 #define NB_PIF0_PWRDOWN_0       0x01100012
  74 #define NB_PIF0_PWRDOWN_1       0x01100013
  75
  76 #define USB_INTEL_XUSB2PR      0xD0
  77 #define USB_INTEL_USB3_PSSEN   0xD8
  78
  79 static struct amd_chipset_info {
  80         struct pci_dev  *nb_dev;
  81         struct pci_dev  *smbus_dev;
  82         int nb_type;
  83         int sb_type;
  84         int isoc_reqs;
  85         int probe_count;
  86         int probe_result;
  87 } amd_chipset;
  88
  89 static DEFINE_SPINLOCK(amd_lock);
  90
  91 int usb_amd_find_chipset_info(void)
  92 {
  93         u8 rev = 0;
  94         unsigned long flags;
  95         struct amd_chipset_info info;
  96         int ret;
  97
  98         spin_lock_irqsave(&amd_lock, flags);
  99
 100         /* probe only once */
 101         if (amd_chipset.probe_count > 0) {
 102                 amd_chipset.probe_count++;
 103                 spin_unlock_irqrestore(&amd_lock, flags);
 104                 return amd_chipset.probe_result;
 105         }
 106         memset(&info, 0, sizeof(info));
 107         spin_unlock_irqrestore(&amd_lock, flags);
 108
 109         info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
 110         if (info.smbus_dev) {
 111                 rev = info.smbus_dev->revision;
 112                 if (rev >= 0x40)
 113                         info.sb_type = 1;
 114                 else if (rev >= 0x30 && rev <= 0x3b)
 115                         info.sb_type = 3;
 116         } else {
 117                 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
 118                                                 0x780b, NULL);
 119                 if (!info.smbus_dev) {
 120                         ret = 0;
 121                         goto commit;
 122                 }
 123
 124                 rev = info.smbus_dev->revision;
 125                 if (rev >= 0x11 && rev <= 0x18)
 126                         info.sb_type = 2;
 127         }
 128
 129         if (info.sb_type == 0) {
 130                 if (info.smbus_dev) {
 131                         pci_dev_put(info.smbus_dev);
 132                         info.smbus_dev = NULL;
 133                 }
 134                 ret = 0;
 135                 goto commit;
 136         }
 137
 138         info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
 139         if (info.nb_dev) {
 140                 info.nb_type = 1;
 141         } else {
 142                 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
 143                 if (info.nb_dev) {
 144                         info.nb_type = 2;
 145                 } else {
 146                         info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
 147                                                      0x9600, NULL);
 148                         if (info.nb_dev)
 149                                 info.nb_type = 3;
 150                 }
 151         }
 152
 153         ret = info.probe_result = 1;
 154         printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
 155
 156 commit:
 157
 158         spin_lock_irqsave(&amd_lock, flags);
 159         if (amd_chipset.probe_count > 0) {
 160                 /* race - someone else was faster - drop devices */
 161
 162                 /* Mark that we where here */
 163                 amd_chipset.probe_count++;
 164                 ret = amd_chipset.probe_result;
 165
 166                 spin_unlock_irqrestore(&amd_lock, flags);
 167
 168                 if (info.nb_dev)
 169                         pci_dev_put(info.nb_dev);
 170                 if (info.smbus_dev)
 171                         pci_dev_put(info.smbus_dev);
 172
 173         } else {
 174                 /* no race - commit the result */
 175                 info.probe_count++;
 176                 amd_chipset = info;
 177                 spin_unlock_irqrestore(&amd_lock, flags);
 178         }
 179
 180         return ret;
 181 }
 182 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
 183
 184 /*
 185  * The hardware normally enables the A-link power management feature, which
 186  * lets the system lower the power consumption in idle states.
 187  *
 188  * This USB quirk prevents the link going into that lower power state
 189  * during isochronous transfers.
 190  *
 191  * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
 192  * some AMD platforms may stutter or have breaks occasionally.
 193  */
 194 static void usb_amd_quirk_pll(int disable)
 195 {
 196         u32 addr, addr_low, addr_high, val;
 197         u32 bit = disable ? 0 : 1;
 198         unsigned long flags;
 199
 200         spin_lock_irqsave(&amd_lock, flags);
 201
 202         if (disable) {
 203                 amd_chipset.isoc_reqs++;
 204                 if (amd_chipset.isoc_reqs > 1) {
 205                         spin_unlock_irqrestore(&amd_lock, flags);
 206                         return;
 207                 }
 208         } else {
 209                 amd_chipset.isoc_reqs--;
 210                 if (amd_chipset.isoc_reqs > 0) {
 211                         spin_unlock_irqrestore(&amd_lock, flags);
 212                         return;
 213                 }
 214         }
 215
 216         if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
 217                 outb_p(AB_REG_BAR_LOW, 0xcd6);
 218                 addr_low = inb_p(0xcd7);
 219                 outb_p(AB_REG_BAR_HIGH, 0xcd6);
 220                 addr_high = inb_p(0xcd7);
 221                 addr = addr_high << 8 | addr_low;
 222
 223                 outl_p(0x30, AB_INDX(addr));
 224                 outl_p(0x40, AB_DATA(addr));
 225                 outl_p(0x34, AB_INDX(addr));
 226                 val = inl_p(AB_DATA(addr));
 227         } else if (amd_chipset.sb_type == 3) {
 228                 pci_read_config_dword(amd_chipset.smbus_dev,
 229                                         AB_REG_BAR_SB700, &addr);
 230                 outl(AX_INDXC, AB_INDX(addr));
 231                 outl(0x40, AB_DATA(addr));
 232                 outl(AX_DATAC, AB_INDX(addr));
 233                 val = inl(AB_DATA(addr));
 234         } else {
 235                 spin_unlock_irqrestore(&amd_lock, flags);
 236                 return;
 237         }
 238
 239         if (disable) {
 240                 val &= ~0x08;
 241                 val |= (1 << 4) | (1 << 9);
 242         } else {
 243                 val |= 0x08;
 244                 val &= ~((1 << 4) | (1 << 9));
 245         }
 246         outl_p(val, AB_DATA(addr));
 247
 248         if (!amd_chipset.nb_dev) {
 249                 spin_unlock_irqrestore(&amd_lock, flags);
 250                 return;
 251         }
 252
 253         if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
 254                 addr = PCIE_P_CNTL;
 255                 pci_write_config_dword(amd_chipset.nb_dev,
 256                                         NB_PCIE_INDX_ADDR, addr);
 257                 pci_read_config_dword(amd_chipset.nb_dev,
 258                                         NB_PCIE_INDX_DATA, &val);
 259
 260                 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
 261                 val |= bit | (bit << 3) | (bit << 12);
 262                 val |= ((!bit) << 4) | ((!bit) << 9);
 263                 pci_write_config_dword(amd_chipset.nb_dev,
 264                                         NB_PCIE_INDX_DATA, val);
 265
 266                 addr = BIF_NB;
 267                 pci_write_config_dword(amd_chipset.nb_dev,
 268                                         NB_PCIE_INDX_ADDR, addr);
 269                 pci_read_config_dword(amd_chipset.nb_dev,
 270                                         NB_PCIE_INDX_DATA, &val);
 271                 val &= ~(1 << 8);
 272                 val |= bit << 8;
 273
 274                 pci_write_config_dword(amd_chipset.nb_dev,
 275                                         NB_PCIE_INDX_DATA, val);
 276         } else if (amd_chipset.nb_type == 2) {
 277                 addr = NB_PIF0_PWRDOWN_0;
 278                 pci_write_config_dword(amd_chipset.nb_dev,
 279                                         NB_PCIE_INDX_ADDR, addr);
 280                 pci_read_config_dword(amd_chipset.nb_dev,
 281                                         NB_PCIE_INDX_DATA, &val);
 282                 if (disable)
 283                         val &= ~(0x3f << 7);
 284                 else
 285                         val |= 0x3f << 7;
 286
 287                 pci_write_config_dword(amd_chipset.nb_dev,
 288                                         NB_PCIE_INDX_DATA, val);
 289
 290                 addr = NB_PIF0_PWRDOWN_1;
 291                 pci_write_config_dword(amd_chipset.nb_dev,
 292                                         NB_PCIE_INDX_ADDR, addr);
 293                 pci_read_config_dword(amd_chipset.nb_dev,
 294                                         NB_PCIE_INDX_DATA, &val);
 295                 if (disable)
 296                         val &= ~(0x3f << 7);
 297                 else
 298                         val |= 0x3f << 7;
 299
 300                 pci_write_config_dword(amd_chipset.nb_dev,
 301                                         NB_PCIE_INDX_DATA, val);
 302         }
 303
 304         spin_unlock_irqrestore(&amd_lock, flags);
 305         return;
 306 }
 307
 308 void usb_amd_quirk_pll_disable(void)
 309 {
 310         usb_amd_quirk_pll(1);
 311 }
 312 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
 313
 314 void usb_amd_quirk_pll_enable(void)
 315 {
 316         usb_amd_quirk_pll(0);
 317 }
 318 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
 319
 320 void usb_amd_dev_put(void)
 321 {
 322         struct pci_dev *nb, *smbus;
 323         unsigned long flags;
 324
 325         spin_lock_irqsave(&amd_lock, flags);
 326
 327         amd_chipset.probe_count--;
 328         if (amd_chipset.probe_count > 0) {
 329                 spin_unlock_irqrestore(&amd_lock, flags);
 330                 return;
 331         }
 332
 333         /* save them to pci_dev_put outside of spinlock */
 334         nb    = amd_chipset.nb_dev;
 335         smbus = amd_chipset.smbus_dev;
 336
 337         amd_chipset.nb_dev = NULL;
 338         amd_chipset.smbus_dev = NULL;
 339         amd_chipset.nb_type = 0;
 340         amd_chipset.sb_type = 0;
 341         amd_chipset.isoc_reqs = 0;
 342         amd_chipset.probe_result = 0;
 343
 344         spin_unlock_irqrestore(&amd_lock, flags);
 345
 346         if (nb)
 347                 pci_dev_put(nb);
 348         if (smbus)
 349                 pci_dev_put(smbus);
 350 }
 351 EXPORT_SYMBOL_GPL(usb_amd_dev_put);
 352
 353 /*
 354  * Make sure the controller is completely inactive, unable to
 355  * generate interrupts or do DMA.
 356  */
 357 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
 358 {
 359         /* Turn off PIRQ enable and SMI enable.  (This also turns off the
 360          * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
 361          */
 362         pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
 363
 364         /* Reset the HC - this will force us to get a
 365          * new notification of any already connected
 366          * ports due to the virtual disconnect that it
 367          * implies.
 368          */
 369         outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
 370         mb();
 371         udelay(5);
 372         if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
 373                 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
 374
 375         /* Just to be safe, disable interrupt requests and
 376          * make sure the controller is stopped.
 377          */
 378         outw(0, base + UHCI_USBINTR);
 379         outw(0, base + UHCI_USBCMD);
 380 }
 381 EXPORT_SYMBOL_GPL(uhci_reset_hc);
 382
 383 /*
 384  * Initialize a controller that was newly discovered or has just been
 385  * resumed.  In either case we can't be sure of its previous state.
 386  *
 387  * Returns: 1 if the controller was reset, 0 otherwise.
 388  */
 389 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
 390 {
 391         u16 legsup;
 392         unsigned int cmd, intr;
 393
 394         /*
 395          * When restarting a suspended controller, we expect all the
 396          * settings to be the same as we left them:
 397          *
 398          *      PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
 399          *      Controller is stopped and configured with EGSM set;
 400          *      No interrupts enabled except possibly Resume Detect.
 401          *
 402          * If any of these conditions are violated we do a complete reset.
 403          */
 404         pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
 405         if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
 406                 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
 407                                 __func__, legsup);
 408                 goto reset_needed;
 409         }
 410
 411         cmd = inw(base + UHCI_USBCMD);
 412         if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
 413                         !(cmd & UHCI_USBCMD_EGSM)) {
 414                 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
 415                                 __func__, cmd);
 416                 goto reset_needed;
 417         }
 418
 419         intr = inw(base + UHCI_USBINTR);
 420         if (intr & (~UHCI_USBINTR_RESUME)) {
 421                 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
 422                                 __func__, intr);
 423                 goto reset_needed;
 424         }
 425         return 0;
 426
 427 reset_needed:
 428         dev_dbg(&pdev->dev, "Performing full reset\n");
 429         uhci_reset_hc(pdev, base);
 430         return 1;
 431 }
 432 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
 433
 434 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
 435 {
 436         u16 cmd;
 437         return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
 438 }
 439
 440 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
 441 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
 442
 443 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
 444 {
 445         unsigned long base = 0;
 446         int i;
 447
 448         if (!pio_enabled(pdev))
 449                 return;
 450
 451         for (i = 0; i < PCI_ROM_RESOURCE; i++)
 452                 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
 453                         base = pci_resource_start(pdev, i);
 454                         break;
 455                 }
 456
 457         if (base)
 458                 uhci_check_and_reset_hc(pdev, base);
 459 }
 460
 461 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
 462 {
 463         return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
 464 }
 465
 466 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
 467 {
 468         void __iomem *base;
 469         u32 control;
 470         u32 fminterval;
 471         int cnt;
 472
 473         if (!mmio_resource_enabled(pdev, 0))
 474                 return;
 475
 476         base = pci_ioremap_bar(pdev, 0);
 477         if (base == NULL)
 478                 return;
 479
 480         control = readl(base + OHCI_CONTROL);
 481
 482 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
 483 #ifdef __hppa__
 484 #define OHCI_CTRL_MASK          (OHCI_CTRL_RWC | OHCI_CTRL_IR)
 485 #else
 486 #define OHCI_CTRL_MASK          OHCI_CTRL_RWC
 487
 488         if (control & OHCI_CTRL_IR) {
 489                 int wait_time = 500; /* arbitrary; 5 seconds */
 490                 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
 491                 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
 492                 while (wait_time > 0 &&
 493                                 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
 494                         wait_time -= 10;
 495                         msleep(10);
 496                 }
 497                 if (wait_time <= 0)
 498                         dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
 499                                         " (BIOS bug?) %08x\n",
 500                                         readl(base + OHCI_CONTROL));
 501         }
 502 #endif
 503
 504         /* disable interrupts */
 505         writel((u32) ~0, base + OHCI_INTRDISABLE);
 506
 507         /* Reset the USB bus, if the controller isn't already in RESET */
 508         if (control & OHCI_HCFS) {
 509                 /* Go into RESET, preserving RWC (and possibly IR) */
 510                 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
 511                 readl(base + OHCI_CONTROL);
 512
 513                 /* drive bus reset for at least 50 ms (7.1.7.5) */
 514                 msleep(50);
 515         }
 516
 517         /* software reset of the controller, preserving HcFmInterval */
 518         fminterval = readl(base + OHCI_FMINTERVAL);
 519         writel(OHCI_HCR, base + OHCI_CMDSTATUS);
 520
 521         /* reset requires max 10 us delay */
 522         for (cnt = 30; cnt > 0; --cnt) {        /* ... allow extra time */
 523                 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
 524                         break;
 525                 udelay(1);
 526         }
 527         writel(fminterval, base + OHCI_FMINTERVAL);
 528
 529         /* Now the controller is safely in SUSPEND and nothing can wake it up */
 530         iounmap(base);
 531 }
 532
 533 static const struct dmi_system_id __devinitconst ehci_dmi_nohandoff_table[] = {
 534         {
 535                 /*  Pegatron Lucid (ExoPC) */
 536                 .matches = {
 537                         DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
 538                         DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
 539                 },
 540         },
 541         {
 542                 /*  Pegatron Lucid (Ordissimo AIRIS) */
 543                 .matches = {
 544                         DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
 545                         DMI_MATCH(DMI_BIOS_VERSION, "Lucid-GE-133"),
 546                 },
 547         },
 548         { }
 549 };
 550
 551 static void __devinit ehci_bios_handoff(struct pci_dev *pdev,
 552                                         void __iomem *op_reg_base,
 553                                         u32 cap, u8 offset)
 554 {
 555         int try_handoff = 1, tried_handoff = 0;
 556
 557         /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying
 558          * the handoff on its unused controller.  Skip it. */
 559         if (pdev->vendor == 0x8086 && pdev->device == 0x283a) {
 560                 if (dmi_check_system(ehci_dmi_nohandoff_table))
 561                         try_handoff = 0;
 562         }
 563
 564         if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
 565                 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
 566
 567 #if 0
 568 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
 569  * but that seems dubious in general (the BIOS left it off intentionally)
 570  * and is known to prevent some systems from booting.  so we won't do this
 571  * unless maybe we can determine when we're on a system that needs SMI forced.
 572  */
 573                 /* BIOS workaround (?): be sure the pre-Linux code
 574                  * receives the SMI
 575                  */
 576                 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
 577                 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
 578                                        val | EHCI_USBLEGCTLSTS_SOOE);
 579 #endif
 580
 581                 /* some systems get upset if this semaphore is
 582                  * set for any other reason than forcing a BIOS
 583                  * handoff..
 584                  */
 585                 pci_write_config_byte(pdev, offset + 3, 1);
 586         }
 587
 588         /* if boot firmware now owns EHCI, spin till it hands it over. */
 589         if (try_handoff) {
 590                 int msec = 1000;
 591                 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
 592                         tried_handoff = 1;
 593                         msleep(10);
 594                         msec -= 10;
 595                         pci_read_config_dword(pdev, offset, &cap);
 596                 }
 597         }
 598
 599         if (cap & EHCI_USBLEGSUP_BIOS) {
 600                 /* well, possibly buggy BIOS... try to shut it down,
 601                  * and hope nothing goes too wrong
 602                  */
 603                 if (try_handoff)
 604                         dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
 605                                  " (BIOS bug?) %08x\n", cap);
 606                 pci_write_config_byte(pdev, offset + 2, 0);
 607         }
 608
 609         /* just in case, always disable EHCI SMIs */
 610         pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
 611
 612         /* If the BIOS ever owned the controller then we can't expect
 613          * any power sessions to remain intact.
 614          */
 615         if (tried_handoff)
 616                 writel(0, op_reg_base + EHCI_CONFIGFLAG);
 617 }
 618
 619 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
 620 {
 621         void __iomem *base, *op_reg_base;
 622         u32     hcc_params, cap, val;
 623         u8      offset, cap_length;
 624         int     wait_time, count = 256/4;
 625
 626         if (!mmio_resource_enabled(pdev, 0))
 627                 return;
 628
 629         base = pci_ioremap_bar(pdev, 0);
 630         if (base == NULL)
 631                 return;
 632
 633         cap_length = readb(base);
 634         op_reg_base = base + cap_length;
 635
 636         /* EHCI 0.96 and later may have "extended capabilities"
 637          * spec section 5.1 explains the bios handoff, e.g. for
 638          * booting from USB disk or using a usb keyboard
 639          */
 640         hcc_params = readl(base + EHCI_HCC_PARAMS);
 641         offset = (hcc_params >> 8) & 0xff;
 642         while (offset && --count) {
 643                 pci_read_config_dword(pdev, offset, &cap);
 644
 645                 switch (cap & 0xff) {
 646                 case 1:
 647                         ehci_bios_handoff(pdev, op_reg_base, cap, offset);
 648                         break;
 649                 case 0: /* Illegal reserved cap, set cap=0 so we exit */
 650                         cap = 0; /* then fallthrough... */
 651                 default:
 652                         dev_warn(&pdev->dev, "EHCI: unrecognized capability "
 653                                  "%02x\n", cap & 0xff);
 654                 }
 655                 offset = (cap >> 8) & 0xff;
 656         }
 657         if (!count)
 658                 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
 659
 660         /*
 661          * halt EHCI & disable its interrupts in any case
 662          */
 663         val = readl(op_reg_base + EHCI_USBSTS);
 664         if ((val & EHCI_USBSTS_HALTED) == 0) {
 665                 val = readl(op_reg_base + EHCI_USBCMD);
 666                 val &= ~EHCI_USBCMD_RUN;
 667                 writel(val, op_reg_base + EHCI_USBCMD);
 668
 669                 wait_time = 2000;
 670                 do {
 671                         writel(0x3f, op_reg_base + EHCI_USBSTS);
 672                         udelay(100);
 673                         wait_time -= 100;
 674                         val = readl(op_reg_base + EHCI_USBSTS);
 675                         if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
 676                                 break;
 677                         }
 678                 } while (wait_time > 0);
 679         }
 680         writel(0, op_reg_base + EHCI_USBINTR);
 681         writel(0x3f, op_reg_base + EHCI_USBSTS);
 682
 683         iounmap(base);
 684 }
 685
 686 /*
 687  * handshake - spin reading a register until handshake completes
 688  * @ptr: address of hc register to be read
 689  * @mask: bits to look at in result of read
 690  * @done: value of those bits when handshake succeeds
 691  * @wait_usec: timeout in microseconds
 692  * @delay_usec: delay in microseconds to wait between polling
 693  *
 694  * Polls a register every delay_usec microseconds.
 695  * Returns 0 when the mask bits have the value done.
 696  * Returns -ETIMEDOUT if this condition is not true after
 697  * wait_usec microseconds have passed.
 698  */
 699 static int handshake(void __iomem *ptr, u32 mask, u32 done,
 700                 int wait_usec, int delay_usec)
 701 {
 702         u32     result;
 703
 704         do {
 705                 result = readl(ptr);
 706                 result &= mask;
 707                 if (result == done)
 708                         return 0;
 709                 udelay(delay_usec);
 710                 wait_usec -= delay_usec;
 711         } while (wait_usec > 0);
 712         return -ETIMEDOUT;
 713 }
 714
 715 bool usb_is_intel_switchable_xhci(struct pci_dev *pdev)
 716 {
 717         return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
 718                 pdev->vendor == PCI_VENDOR_ID_INTEL &&
 719                 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI;
 720 }
 721 EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci);
 722
 723 /*
 724  * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
 725  * share some number of ports.  These ports can be switched between either
 726  * controller.  Not all of the ports under the EHCI host controller may be
 727  * switchable.
 728  *
 729  * The ports should be switched over to xHCI before PCI probes for any device
 730  * start.  This avoids active devices under EHCI being disconnected during the
 731  * port switchover, which could cause loss of data on USB storage devices, or
 732  * failed boot when the root file system is on a USB mass storage device and is
 733  * enumerated under EHCI first.
 734  *
 735  * We write into the xHC's PCI configuration space in some Intel-specific
 736  * registers to switch the ports over.  The USB 3.0 terminations and the USB
 737  * 2.0 data wires are switched separately.  We want to enable the SuperSpeed
 738  * terminations before switching the USB 2.0 wires over, so that USB 3.0
 739  * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
 740  */
 741 void usb_enable_xhci_ports(struct pci_dev *xhci_pdev)
 742 {
 743         u32             ports_available;
 744
 745         ports_available = 0xffffffff;
 746         /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
 747          * Register, to turn on SuperSpeed terminations for all
 748          * available ports.
 749          */
 750         pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
 751                         cpu_to_le32(ports_available));
 752
 753         pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
 754                         &ports_available);
 755         dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "
 756                         "under xHCI: 0x%x\n", ports_available);
 757
 758         ports_available = 0xffffffff;
 759         /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
 760          * switch the USB 2.0 power and data lines over to the xHCI
 761          * host.
 762          */
 763         pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
 764                         cpu_to_le32(ports_available));
 765
 766         pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
 767                         &ports_available);
 768         dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
 769                         "to xHCI: 0x%x\n", ports_available);
 770 }
 771 EXPORT_SYMBOL_GPL(usb_enable_xhci_ports);
 772
 773 /**
 774  * PCI Quirks for xHCI.
 775  *
 776  * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
 777  * It signals to the BIOS that the OS wants control of the host controller,
 778  * and then waits 5 seconds for the BIOS to hand over control.
 779  * If we timeout, assume the BIOS is broken and take control anyway.
 780  */
 781 static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
 782 {
 783         void __iomem *base;
 784         int ext_cap_offset;
 785         void __iomem *op_reg_base;
 786         u32 val;
 787         int timeout;
 788
 789         if (!mmio_resource_enabled(pdev, 0))
 790                 return;
 791
 792         base = ioremap_nocache(pci_resource_start(pdev, 0),
 793                                 pci_resource_len(pdev, 0));
 794         if (base == NULL)
 795                 return;
 796
 797         /*
 798          * Find the Legacy Support Capability register -
 799          * this is optional for xHCI host controllers.
 800          */
 801         ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
 802         do {
 803                 if (!ext_cap_offset)
 804                         /* We've reached the end of the extended capabilities */
 805                         goto hc_init;
 806                 val = readl(base + ext_cap_offset);
 807                 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
 808                         break;
 809                 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
 810         } while (1);
 811
 812         /* If the BIOS owns the HC, signal that the OS wants it, and wait */
 813         if (val & XHCI_HC_BIOS_OWNED) {
 814                 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
 815
 816                 /* Wait for 5 seconds with 10 microsecond polling interval */
 817                 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
 818                                 0, 5000, 10);
 819
 820                 /* Assume a buggy BIOS and take HC ownership anyway */
 821                 if (timeout) {
 822                         dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
 823                                         " (BIOS bug ?) %08x\n", val);
 824                         writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
 825                 }
 826         }
 827
 828         /* Disable any BIOS SMIs */
 829         writel(XHCI_LEGACY_DISABLE_SMI,
 830                         base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
 831
 832         if (usb_is_intel_switchable_xhci(pdev))
 833                 usb_enable_xhci_ports(pdev);
 834 hc_init:
 835         op_reg_base = base + XHCI_HC_LENGTH(readl(base));
 836
 837         /* Wait for the host controller to be ready before writing any
 838          * operational or runtime registers.  Wait 5 seconds and no more.
 839          */
 840         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
 841                         5000, 10);
 842         /* Assume a buggy HC and start HC initialization anyway */
 843         if (timeout) {
 844                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 845                 dev_warn(&pdev->dev,
 846                                 "xHCI HW not ready after 5 sec (HC bug?) "
 847                                 "status = 0x%x\n", val);
 848         }
 849
 850         /* Send the halt and disable interrupts command */
 851         val = readl(op_reg_base + XHCI_CMD_OFFSET);
 852         val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
 853         writel(val, op_reg_base + XHCI_CMD_OFFSET);
 854
 855         /* Wait for the HC to halt - poll every 125 usec (one microframe). */
 856         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
 857                         XHCI_MAX_HALT_USEC, 125);
 858         if (timeout) {
 859                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 860                 dev_warn(&pdev->dev,
 861                                 "xHCI HW did not halt within %d usec "
 862                                 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
 863         }
 864
 865         iounmap(base);
 866 }
 867
 868 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
 869 {
 870         if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
 871                 quirk_usb_handoff_uhci(pdev);
 872         else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
 873                 quirk_usb_handoff_ohci(pdev);
 874         else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
 875                 quirk_usb_disable_ehci(pdev);
 876         else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
 877                 quirk_usb_handoff_xhci(pdev);
 878 }
 879 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);