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regulator, mc13xxx: Remove pointless test for unsigned less than zero
[zen-stable.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
blob8d8181334f862d9b7e79f64328e7dcaf29e8d699
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
13 *
14 * XXX these should be marked initdata for multi-OMAP kernels
15 */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l4_3xxx.h>
22 #include <plat/i2c.h>
23 #include <plat/gpio.h>
24 #include <plat/smartreflex.h>
25
26 #include "omap_hwmod_common_data.h"
27
28 #include "prm-regbits-34xx.h"
29 #include "cm-regbits-34xx.h"
30 #include "wd_timer.h"
31
32 /*
33 * OMAP3xxx hardware module integration data
34 *
35 * ALl of the data in this section should be autogeneratable from the
36 * TI hardware database or other technical documentation. Data that
37 * is driver-specific or driver-kernel integration-specific belongs
38 * elsewhere.
39 */
40
41 static struct omap_hwmod omap3xxx_mpu_hwmod;
42 static struct omap_hwmod omap3xxx_iva_hwmod;
43 static struct omap_hwmod omap3xxx_l3_main_hwmod;
44 static struct omap_hwmod omap3xxx_l4_core_hwmod;
45 static struct omap_hwmod omap3xxx_l4_per_hwmod;
46 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
47 static struct omap_hwmod omap3xxx_i2c1_hwmod;
48 static struct omap_hwmod omap3xxx_i2c2_hwmod;
49 static struct omap_hwmod omap3xxx_i2c3_hwmod;
50 static struct omap_hwmod omap3xxx_gpio1_hwmod;
51 static struct omap_hwmod omap3xxx_gpio2_hwmod;
52 static struct omap_hwmod omap3xxx_gpio3_hwmod;
53 static struct omap_hwmod omap3xxx_gpio4_hwmod;
54 static struct omap_hwmod omap3xxx_gpio5_hwmod;
55 static struct omap_hwmod omap3xxx_gpio6_hwmod;
56 static struct omap_hwmod omap34xx_sr1_hwmod;
57 static struct omap_hwmod omap34xx_sr2_hwmod;
58
59 static struct omap_hwmod omap3xxx_dma_system_hwmod;
60
61 /* L3 -> L4_CORE interface */
62 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
63 .master = &omap3xxx_l3_main_hwmod,
64 .slave = &omap3xxx_l4_core_hwmod,
65 .user = OCP_USER_MPU | OCP_USER_SDMA,
66 };
67
68 /* L3 -> L4_PER interface */
69 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
70 .master = &omap3xxx_l3_main_hwmod,
71 .slave = &omap3xxx_l4_per_hwmod,
72 .user = OCP_USER_MPU | OCP_USER_SDMA,
73 };
74
75 /* MPU -> L3 interface */
76 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
77 .master = &omap3xxx_mpu_hwmod,
78 .slave = &omap3xxx_l3_main_hwmod,
79 .user = OCP_USER_MPU,
80 };
81
82 /* Slave interfaces on the L3 interconnect */
83 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
84 &omap3xxx_mpu__l3_main,
85 };
86
87 /* Master interfaces on the L3 interconnect */
88 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
89 &omap3xxx_l3_main__l4_core,
90 &omap3xxx_l3_main__l4_per,
91 };
92
93 /* L3 */
94 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
95 .name = "l3_main",
96 .class = &l3_hwmod_class,
97 .masters = omap3xxx_l3_main_masters,
98 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
99 .slaves = omap3xxx_l3_main_slaves,
100 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
102 .flags = HWMOD_NO_IDLEST,
103 };
104
105 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
106 static struct omap_hwmod omap3xxx_uart1_hwmod;
107 static struct omap_hwmod omap3xxx_uart2_hwmod;
108 static struct omap_hwmod omap3xxx_uart3_hwmod;
109 static struct omap_hwmod omap3xxx_uart4_hwmod;
110
111 /* L4_CORE -> L4_WKUP interface */
112 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
113 .master = &omap3xxx_l4_core_hwmod,
114 .slave = &omap3xxx_l4_wkup_hwmod,
115 .user = OCP_USER_MPU | OCP_USER_SDMA,
116 };
117
118 /* L4 CORE -> UART1 interface */
119 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
120 {
121 .pa_start = OMAP3_UART1_BASE,
122 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
123 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
124 },
125 };
126
127 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
128 .master = &omap3xxx_l4_core_hwmod,
129 .slave = &omap3xxx_uart1_hwmod,
130 .clk = "uart1_ick",
131 .addr = omap3xxx_uart1_addr_space,
132 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
133 .user = OCP_USER_MPU | OCP_USER_SDMA,
134 };
135
136 /* L4 CORE -> UART2 interface */
137 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
138 {
139 .pa_start = OMAP3_UART2_BASE,
140 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
141 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
142 },
143 };
144
145 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
146 .master = &omap3xxx_l4_core_hwmod,
147 .slave = &omap3xxx_uart2_hwmod,
148 .clk = "uart2_ick",
149 .addr = omap3xxx_uart2_addr_space,
150 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
151 .user = OCP_USER_MPU | OCP_USER_SDMA,
152 };
153
154 /* L4 PER -> UART3 interface */
155 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
156 {
157 .pa_start = OMAP3_UART3_BASE,
158 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
159 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
160 },
161 };
162
163 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
164 .master = &omap3xxx_l4_per_hwmod,
165 .slave = &omap3xxx_uart3_hwmod,
166 .clk = "uart3_ick",
167 .addr = omap3xxx_uart3_addr_space,
168 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
169 .user = OCP_USER_MPU | OCP_USER_SDMA,
170 };
171
172 /* L4 PER -> UART4 interface */
173 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
174 {
175 .pa_start = OMAP3_UART4_BASE,
176 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
177 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
178 },
179 };
180
181 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
182 .master = &omap3xxx_l4_per_hwmod,
183 .slave = &omap3xxx_uart4_hwmod,
184 .clk = "uart4_ick",
185 .addr = omap3xxx_uart4_addr_space,
186 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
187 .user = OCP_USER_MPU | OCP_USER_SDMA,
188 };
189
190 /* I2C IP block address space length (in bytes) */
191 #define OMAP2_I2C_AS_LEN 128
192
193 /* L4 CORE -> I2C1 interface */
194 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
195 {
196 .pa_start = 0x48070000,
197 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
198 .flags = ADDR_TYPE_RT,
199 },
200 };
201
202 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
203 .master = &omap3xxx_l4_core_hwmod,
204 .slave = &omap3xxx_i2c1_hwmod,
205 .clk = "i2c1_ick",
206 .addr = omap3xxx_i2c1_addr_space,
207 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
208 .fw = {
209 .omap2 = {
210 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
211 .l4_prot_group = 7,
212 .flags = OMAP_FIREWALL_L4,
213 }
214 },
215 .user = OCP_USER_MPU | OCP_USER_SDMA,
216 };
217
218 /* L4 CORE -> I2C2 interface */
219 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
220 {
221 .pa_start = 0x48072000,
222 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
223 .flags = ADDR_TYPE_RT,
224 },
225 };
226
227 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
228 .master = &omap3xxx_l4_core_hwmod,
229 .slave = &omap3xxx_i2c2_hwmod,
230 .clk = "i2c2_ick",
231 .addr = omap3xxx_i2c2_addr_space,
232 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
233 .fw = {
234 .omap2 = {
235 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
236 .l4_prot_group = 7,
237 .flags = OMAP_FIREWALL_L4,
238 }
239 },
240 .user = OCP_USER_MPU | OCP_USER_SDMA,
241 };
242
243 /* L4 CORE -> I2C3 interface */
244 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
245 {
246 .pa_start = 0x48060000,
247 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
248 .flags = ADDR_TYPE_RT,
249 },
250 };
251
252 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
253 .master = &omap3xxx_l4_core_hwmod,
254 .slave = &omap3xxx_i2c3_hwmod,
255 .clk = "i2c3_ick",
256 .addr = omap3xxx_i2c3_addr_space,
257 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
258 .fw = {
259 .omap2 = {
260 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
261 .l4_prot_group = 7,
262 .flags = OMAP_FIREWALL_L4,
263 }
264 },
265 .user = OCP_USER_MPU | OCP_USER_SDMA,
266 };
267
268 /* L4 CORE -> SR1 interface */
269 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
270 {
271 .pa_start = OMAP34XX_SR1_BASE,
272 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
273 .flags = ADDR_TYPE_RT,
274 },
275 };
276
277 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
278 .master = &omap3xxx_l4_core_hwmod,
279 .slave = &omap34xx_sr1_hwmod,
280 .clk = "sr_l4_ick",
281 .addr = omap3_sr1_addr_space,
282 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
283 .user = OCP_USER_MPU,
284 };
285
286 /* L4 CORE -> SR1 interface */
287 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
288 {
289 .pa_start = OMAP34XX_SR2_BASE,
290 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
291 .flags = ADDR_TYPE_RT,
292 },
293 };
294
295 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
296 .master = &omap3xxx_l4_core_hwmod,
297 .slave = &omap34xx_sr2_hwmod,
298 .clk = "sr_l4_ick",
299 .addr = omap3_sr2_addr_space,
300 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
301 .user = OCP_USER_MPU,
302 };
303
304 /* Slave interfaces on the L4_CORE interconnect */
305 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
306 &omap3xxx_l3_main__l4_core,
307 &omap3_l4_core__sr1,
308 &omap3_l4_core__sr2,
309 };
310
311 /* Master interfaces on the L4_CORE interconnect */
312 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
313 &omap3xxx_l4_core__l4_wkup,
314 &omap3_l4_core__uart1,
315 &omap3_l4_core__uart2,
316 &omap3_l4_core__i2c1,
317 &omap3_l4_core__i2c2,
318 &omap3_l4_core__i2c3,
319 };
320
321 /* L4 CORE */
322 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
323 .name = "l4_core",
324 .class = &l4_hwmod_class,
325 .masters = omap3xxx_l4_core_masters,
326 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
327 .slaves = omap3xxx_l4_core_slaves,
328 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
329 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
330 .flags = HWMOD_NO_IDLEST,
331 };
332
333 /* Slave interfaces on the L4_PER interconnect */
334 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
335 &omap3xxx_l3_main__l4_per,
336 };
337
338 /* Master interfaces on the L4_PER interconnect */
339 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
340 &omap3_l4_per__uart3,
341 &omap3_l4_per__uart4,
342 };
343
344 /* L4 PER */
345 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
346 .name = "l4_per",
347 .class = &l4_hwmod_class,
348 .masters = omap3xxx_l4_per_masters,
349 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
350 .slaves = omap3xxx_l4_per_slaves,
351 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
352 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
353 .flags = HWMOD_NO_IDLEST,
354 };
355
356 /* Slave interfaces on the L4_WKUP interconnect */
357 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
358 &omap3xxx_l4_core__l4_wkup,
359 };
360
361 /* Master interfaces on the L4_WKUP interconnect */
362 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
363 };
364
365 /* L4 WKUP */
366 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
367 .name = "l4_wkup",
368 .class = &l4_hwmod_class,
369 .masters = omap3xxx_l4_wkup_masters,
370 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
371 .slaves = omap3xxx_l4_wkup_slaves,
372 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
373 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
374 .flags = HWMOD_NO_IDLEST,
375 };
376
377 /* Master interfaces on the MPU device */
378 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
379 &omap3xxx_mpu__l3_main,
380 };
381
382 /* MPU */
383 static struct omap_hwmod omap3xxx_mpu_hwmod = {
384 .name = "mpu",
385 .class = &mpu_hwmod_class,
386 .main_clk = "arm_fck",
387 .masters = omap3xxx_mpu_masters,
388 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
389 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
390 };
391
392 /*
393 * IVA2_2 interface data
394 */
395
396 /* IVA2 <- L3 interface */
397 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
398 .master = &omap3xxx_l3_main_hwmod,
399 .slave = &omap3xxx_iva_hwmod,
400 .clk = "iva2_ck",
401 .user = OCP_USER_MPU | OCP_USER_SDMA,
402 };
403
404 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
405 &omap3xxx_l3__iva,
406 };
407
408 /*
409 * IVA2 (IVA2)
410 */
411
412 static struct omap_hwmod omap3xxx_iva_hwmod = {
413 .name = "iva",
414 .class = &iva_hwmod_class,
415 .masters = omap3xxx_iva_masters,
416 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
417 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
418 };
419
420 /* l4_wkup -> wd_timer2 */
421 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
422 {
423 .pa_start = 0x48314000,
424 .pa_end = 0x4831407f,
425 .flags = ADDR_TYPE_RT
426 },
427 };
428
429 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
430 .master = &omap3xxx_l4_wkup_hwmod,
431 .slave = &omap3xxx_wd_timer2_hwmod,
432 .clk = "wdt2_ick",
433 .addr = omap3xxx_wd_timer2_addrs,
434 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
435 .user = OCP_USER_MPU | OCP_USER_SDMA,
436 };
437
438 /*
439 * 'wd_timer' class
440 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
441 * overflow condition
442 */
443
444 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
445 .rev_offs = 0x0000,
446 .sysc_offs = 0x0010,
447 .syss_offs = 0x0014,
448 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
449 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
450 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
452 .sysc_fields = &omap_hwmod_sysc_type1,
453 };
454
455 /* I2C common */
456 static struct omap_hwmod_class_sysconfig i2c_sysc = {
457 .rev_offs = 0x00,
458 .sysc_offs = 0x20,
459 .syss_offs = 0x10,
460 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
461 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
462 SYSC_HAS_AUTOIDLE),
463 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
464 .sysc_fields = &omap_hwmod_sysc_type1,
465 };
466
467 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
468 .name = "wd_timer",
469 .sysc = &omap3xxx_wd_timer_sysc,
470 .pre_shutdown = &omap2_wd_timer_disable
471 };
472
473 /* wd_timer2 */
474 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
475 &omap3xxx_l4_wkup__wd_timer2,
476 };
477
478 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
479 .name = "wd_timer2",
480 .class = &omap3xxx_wd_timer_hwmod_class,
481 .main_clk = "wdt2_fck",
482 .prcm = {
483 .omap2 = {
484 .prcm_reg_id = 1,
485 .module_bit = OMAP3430_EN_WDT2_SHIFT,
486 .module_offs = WKUP_MOD,
487 .idlest_reg_id = 1,
488 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
489 },
490 },
491 .slaves = omap3xxx_wd_timer2_slaves,
492 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
493 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
494 };
495
496 /* UART common */
497
498 static struct omap_hwmod_class_sysconfig uart_sysc = {
499 .rev_offs = 0x50,
500 .sysc_offs = 0x54,
501 .syss_offs = 0x58,
502 .sysc_flags = (SYSC_HAS_SIDLEMODE |
503 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
504 SYSC_HAS_AUTOIDLE),
505 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
506 .sysc_fields = &omap_hwmod_sysc_type1,
507 };
508
509 static struct omap_hwmod_class uart_class = {
510 .name = "uart",
511 .sysc = &uart_sysc,
512 };
513
514 /* UART1 */
515
516 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
517 { .irq = INT_24XX_UART1_IRQ, },
518 };
519
520 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
521 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
522 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
523 };
524
525 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
526 &omap3_l4_core__uart1,
527 };
528
529 static struct omap_hwmod omap3xxx_uart1_hwmod = {
530 .name = "uart1",
531 .mpu_irqs = uart1_mpu_irqs,
532 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
533 .sdma_reqs = uart1_sdma_reqs,
534 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
535 .main_clk = "uart1_fck",
536 .prcm = {
537 .omap2 = {
538 .module_offs = CORE_MOD,
539 .prcm_reg_id = 1,
540 .module_bit = OMAP3430_EN_UART1_SHIFT,
541 .idlest_reg_id = 1,
542 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
543 },
544 },
545 .slaves = omap3xxx_uart1_slaves,
546 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
547 .class = &uart_class,
548 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
549 };
550
551 /* UART2 */
552
553 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
554 { .irq = INT_24XX_UART2_IRQ, },
555 };
556
557 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
558 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
559 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
560 };
561
562 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
563 &omap3_l4_core__uart2,
564 };
565
566 static struct omap_hwmod omap3xxx_uart2_hwmod = {
567 .name = "uart2",
568 .mpu_irqs = uart2_mpu_irqs,
569 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
570 .sdma_reqs = uart2_sdma_reqs,
571 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
572 .main_clk = "uart2_fck",
573 .prcm = {
574 .omap2 = {
575 .module_offs = CORE_MOD,
576 .prcm_reg_id = 1,
577 .module_bit = OMAP3430_EN_UART2_SHIFT,
578 .idlest_reg_id = 1,
579 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
580 },
581 },
582 .slaves = omap3xxx_uart2_slaves,
583 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
584 .class = &uart_class,
585 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
586 };
587
588 /* UART3 */
589
590 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
591 { .irq = INT_24XX_UART3_IRQ, },
592 };
593
594 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
595 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
596 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
597 };
598
599 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
600 &omap3_l4_per__uart3,
601 };
602
603 static struct omap_hwmod omap3xxx_uart3_hwmod = {
604 .name = "uart3",
605 .mpu_irqs = uart3_mpu_irqs,
606 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
607 .sdma_reqs = uart3_sdma_reqs,
608 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
609 .main_clk = "uart3_fck",
610 .prcm = {
611 .omap2 = {
612 .module_offs = OMAP3430_PER_MOD,
613 .prcm_reg_id = 1,
614 .module_bit = OMAP3430_EN_UART3_SHIFT,
615 .idlest_reg_id = 1,
616 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
617 },
618 },
619 .slaves = omap3xxx_uart3_slaves,
620 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
621 .class = &uart_class,
622 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
623 };
624
625 /* UART4 */
626
627 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
628 { .irq = INT_36XX_UART4_IRQ, },
629 };
630
631 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
632 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
633 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
634 };
635
636 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
637 &omap3_l4_per__uart4,
638 };
639
640 static struct omap_hwmod omap3xxx_uart4_hwmod = {
641 .name = "uart4",
642 .mpu_irqs = uart4_mpu_irqs,
643 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
644 .sdma_reqs = uart4_sdma_reqs,
645 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
646 .main_clk = "uart4_fck",
647 .prcm = {
648 .omap2 = {
649 .module_offs = OMAP3430_PER_MOD,
650 .prcm_reg_id = 1,
651 .module_bit = OMAP3630_EN_UART4_SHIFT,
652 .idlest_reg_id = 1,
653 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
654 },
655 },
656 .slaves = omap3xxx_uart4_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
658 .class = &uart_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
660 };
661
662 static struct omap_hwmod_class i2c_class = {
663 .name = "i2c",
664 .sysc = &i2c_sysc,
665 };
666
667 /* I2C1 */
668
669 static struct omap_i2c_dev_attr i2c1_dev_attr = {
670 .fifo_depth = 8, /* bytes */
671 };
672
673 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
674 { .irq = INT_24XX_I2C1_IRQ, },
675 };
676
677 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
678 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
679 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
680 };
681
682 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
683 &omap3_l4_core__i2c1,
684 };
685
686 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
687 .name = "i2c1",
688 .mpu_irqs = i2c1_mpu_irqs,
689 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
690 .sdma_reqs = i2c1_sdma_reqs,
691 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
692 .main_clk = "i2c1_fck",
693 .prcm = {
694 .omap2 = {
695 .module_offs = CORE_MOD,
696 .prcm_reg_id = 1,
697 .module_bit = OMAP3430_EN_I2C1_SHIFT,
698 .idlest_reg_id = 1,
699 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
700 },
701 },
702 .slaves = omap3xxx_i2c1_slaves,
703 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
704 .class = &i2c_class,
705 .dev_attr = &i2c1_dev_attr,
706 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
707 };
708
709 /* I2C2 */
710
711 static struct omap_i2c_dev_attr i2c2_dev_attr = {
712 .fifo_depth = 8, /* bytes */
713 };
714
715 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
716 { .irq = INT_24XX_I2C2_IRQ, },
717 };
718
719 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
720 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
721 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
722 };
723
724 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
725 &omap3_l4_core__i2c2,
726 };
727
728 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
729 .name = "i2c2",
730 .mpu_irqs = i2c2_mpu_irqs,
731 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
732 .sdma_reqs = i2c2_sdma_reqs,
733 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
734 .main_clk = "i2c2_fck",
735 .prcm = {
736 .omap2 = {
737 .module_offs = CORE_MOD,
738 .prcm_reg_id = 1,
739 .module_bit = OMAP3430_EN_I2C2_SHIFT,
740 .idlest_reg_id = 1,
741 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
742 },
743 },
744 .slaves = omap3xxx_i2c2_slaves,
745 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
746 .class = &i2c_class,
747 .dev_attr = &i2c2_dev_attr,
748 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
749 };
750
751 /* I2C3 */
752
753 static struct omap_i2c_dev_attr i2c3_dev_attr = {
754 .fifo_depth = 64, /* bytes */
755 };
756
757 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
758 { .irq = INT_34XX_I2C3_IRQ, },
759 };
760
761 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
762 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
763 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
764 };
765
766 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
767 &omap3_l4_core__i2c3,
768 };
769
770 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
771 .name = "i2c3",
772 .mpu_irqs = i2c3_mpu_irqs,
773 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
774 .sdma_reqs = i2c3_sdma_reqs,
775 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
776 .main_clk = "i2c3_fck",
777 .prcm = {
778 .omap2 = {
779 .module_offs = CORE_MOD,
780 .prcm_reg_id = 1,
781 .module_bit = OMAP3430_EN_I2C3_SHIFT,
782 .idlest_reg_id = 1,
783 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
784 },
785 },
786 .slaves = omap3xxx_i2c3_slaves,
787 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
788 .class = &i2c_class,
789 .dev_attr = &i2c3_dev_attr,
790 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
791 };
792
793 /* l4_wkup -> gpio1 */
794 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
795 {
796 .pa_start = 0x48310000,
797 .pa_end = 0x483101ff,
798 .flags = ADDR_TYPE_RT
799 },
800 };
801
802 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
803 .master = &omap3xxx_l4_wkup_hwmod,
804 .slave = &omap3xxx_gpio1_hwmod,
805 .addr = omap3xxx_gpio1_addrs,
806 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
807 .user = OCP_USER_MPU | OCP_USER_SDMA,
808 };
809
810 /* l4_per -> gpio2 */
811 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
812 {
813 .pa_start = 0x49050000,
814 .pa_end = 0x490501ff,
815 .flags = ADDR_TYPE_RT
816 },
817 };
818
819 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
820 .master = &omap3xxx_l4_per_hwmod,
821 .slave = &omap3xxx_gpio2_hwmod,
822 .addr = omap3xxx_gpio2_addrs,
823 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
824 .user = OCP_USER_MPU | OCP_USER_SDMA,
825 };
826
827 /* l4_per -> gpio3 */
828 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
829 {
830 .pa_start = 0x49052000,
831 .pa_end = 0x490521ff,
832 .flags = ADDR_TYPE_RT
833 },
834 };
835
836 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
837 .master = &omap3xxx_l4_per_hwmod,
838 .slave = &omap3xxx_gpio3_hwmod,
839 .addr = omap3xxx_gpio3_addrs,
840 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
841 .user = OCP_USER_MPU | OCP_USER_SDMA,
842 };
843
844 /* l4_per -> gpio4 */
845 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
846 {
847 .pa_start = 0x49054000,
848 .pa_end = 0x490541ff,
849 .flags = ADDR_TYPE_RT
850 },
851 };
852
853 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
854 .master = &omap3xxx_l4_per_hwmod,
855 .slave = &omap3xxx_gpio4_hwmod,
856 .addr = omap3xxx_gpio4_addrs,
857 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
858 .user = OCP_USER_MPU | OCP_USER_SDMA,
859 };
860
861 /* l4_per -> gpio5 */
862 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
863 {
864 .pa_start = 0x49056000,
865 .pa_end = 0x490561ff,
866 .flags = ADDR_TYPE_RT
867 },
868 };
869
870 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
871 .master = &omap3xxx_l4_per_hwmod,
872 .slave = &omap3xxx_gpio5_hwmod,
873 .addr = omap3xxx_gpio5_addrs,
874 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
875 .user = OCP_USER_MPU | OCP_USER_SDMA,
876 };
877
878 /* l4_per -> gpio6 */
879 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
880 {
881 .pa_start = 0x49058000,
882 .pa_end = 0x490581ff,
883 .flags = ADDR_TYPE_RT
884 },
885 };
886
887 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
888 .master = &omap3xxx_l4_per_hwmod,
889 .slave = &omap3xxx_gpio6_hwmod,
890 .addr = omap3xxx_gpio6_addrs,
891 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
892 .user = OCP_USER_MPU | OCP_USER_SDMA,
893 };
894
895 /*
896 * 'gpio' class
897 * general purpose io module
898 */
899
900 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
901 .rev_offs = 0x0000,
902 .sysc_offs = 0x0010,
903 .syss_offs = 0x0014,
904 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
905 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
906 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
907 .sysc_fields = &omap_hwmod_sysc_type1,
908 };
909
910 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
911 .name = "gpio",
912 .sysc = &omap3xxx_gpio_sysc,
913 .rev = 1,
914 };
915
916 /* gpio_dev_attr*/
917 static struct omap_gpio_dev_attr gpio_dev_attr = {
918 .bank_width = 32,
919 .dbck_flag = true,
920 };
921
922 /* gpio1 */
923 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
924 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
925 };
926
927 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
928 { .role = "dbclk", .clk = "gpio1_dbck", },
929 };
930
931 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
932 &omap3xxx_l4_wkup__gpio1,
933 };
934
935 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
936 .name = "gpio1",
937 .mpu_irqs = omap3xxx_gpio1_irqs,
938 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
939 .main_clk = "gpio1_ick",
940 .opt_clks = gpio1_opt_clks,
941 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
942 .prcm = {
943 .omap2 = {
944 .prcm_reg_id = 1,
945 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
946 .module_offs = WKUP_MOD,
947 .idlest_reg_id = 1,
948 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
949 },
950 },
951 .slaves = omap3xxx_gpio1_slaves,
952 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
953 .class = &omap3xxx_gpio_hwmod_class,
954 .dev_attr = &gpio_dev_attr,
955 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
956 };
957
958 /* gpio2 */
959 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
960 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
961 };
962
963 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
964 { .role = "dbclk", .clk = "gpio2_dbck", },
965 };
966
967 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
968 &omap3xxx_l4_per__gpio2,
969 };
970
971 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
972 .name = "gpio2",
973 .mpu_irqs = omap3xxx_gpio2_irqs,
974 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
975 .main_clk = "gpio2_ick",
976 .opt_clks = gpio2_opt_clks,
977 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
978 .prcm = {
979 .omap2 = {
980 .prcm_reg_id = 1,
981 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
982 .module_offs = OMAP3430_PER_MOD,
983 .idlest_reg_id = 1,
984 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
985 },
986 },
987 .slaves = omap3xxx_gpio2_slaves,
988 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
989 .class = &omap3xxx_gpio_hwmod_class,
990 .dev_attr = &gpio_dev_attr,
991 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
992 };
993
994 /* gpio3 */
995 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
996 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
997 };
998
999 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1000 { .role = "dbclk", .clk = "gpio3_dbck", },
1001 };
1002
1003 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1004 &omap3xxx_l4_per__gpio3,
1005 };
1006
1007 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1008 .name = "gpio3",
1009 .mpu_irqs = omap3xxx_gpio3_irqs,
1010 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
1011 .main_clk = "gpio3_ick",
1012 .opt_clks = gpio3_opt_clks,
1013 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1014 .prcm = {
1015 .omap2 = {
1016 .prcm_reg_id = 1,
1017 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1018 .module_offs = OMAP3430_PER_MOD,
1019 .idlest_reg_id = 1,
1020 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1021 },
1022 },
1023 .slaves = omap3xxx_gpio3_slaves,
1024 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1025 .class = &omap3xxx_gpio_hwmod_class,
1026 .dev_attr = &gpio_dev_attr,
1027 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1028 };
1029
1030 /* gpio4 */
1031 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
1032 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
1033 };
1034
1035 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1036 { .role = "dbclk", .clk = "gpio4_dbck", },
1037 };
1038
1039 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1040 &omap3xxx_l4_per__gpio4,
1041 };
1042
1043 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1044 .name = "gpio4",
1045 .mpu_irqs = omap3xxx_gpio4_irqs,
1046 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
1047 .main_clk = "gpio4_ick",
1048 .opt_clks = gpio4_opt_clks,
1049 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1050 .prcm = {
1051 .omap2 = {
1052 .prcm_reg_id = 1,
1053 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1054 .module_offs = OMAP3430_PER_MOD,
1055 .idlest_reg_id = 1,
1056 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1057 },
1058 },
1059 .slaves = omap3xxx_gpio4_slaves,
1060 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1061 .class = &omap3xxx_gpio_hwmod_class,
1062 .dev_attr = &gpio_dev_attr,
1063 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1064 };
1065
1066 /* gpio5 */
1067 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1068 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1069 };
1070
1071 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1072 { .role = "dbclk", .clk = "gpio5_dbck", },
1073 };
1074
1075 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1076 &omap3xxx_l4_per__gpio5,
1077 };
1078
1079 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1080 .name = "gpio5",
1081 .mpu_irqs = omap3xxx_gpio5_irqs,
1082 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
1083 .main_clk = "gpio5_ick",
1084 .opt_clks = gpio5_opt_clks,
1085 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1086 .prcm = {
1087 .omap2 = {
1088 .prcm_reg_id = 1,
1089 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1090 .module_offs = OMAP3430_PER_MOD,
1091 .idlest_reg_id = 1,
1092 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1093 },
1094 },
1095 .slaves = omap3xxx_gpio5_slaves,
1096 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1097 .class = &omap3xxx_gpio_hwmod_class,
1098 .dev_attr = &gpio_dev_attr,
1099 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1100 };
1101
1102 /* gpio6 */
1103 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1104 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1105 };
1106
1107 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1108 { .role = "dbclk", .clk = "gpio6_dbck", },
1109 };
1110
1111 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1112 &omap3xxx_l4_per__gpio6,
1113 };
1114
1115 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1116 .name = "gpio6",
1117 .mpu_irqs = omap3xxx_gpio6_irqs,
1118 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
1119 .main_clk = "gpio6_ick",
1120 .opt_clks = gpio6_opt_clks,
1121 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1122 .prcm = {
1123 .omap2 = {
1124 .prcm_reg_id = 1,
1125 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1126 .module_offs = OMAP3430_PER_MOD,
1127 .idlest_reg_id = 1,
1128 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1129 },
1130 },
1131 .slaves = omap3xxx_gpio6_slaves,
1132 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
1133 .class = &omap3xxx_gpio_hwmod_class,
1134 .dev_attr = &gpio_dev_attr,
1135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1136 };
1137
1138 /* dma_system -> L3 */
1139 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
1140 .master = &omap3xxx_dma_system_hwmod,
1141 .slave = &omap3xxx_l3_main_hwmod,
1142 .clk = "core_l3_ick",
1143 .user = OCP_USER_MPU | OCP_USER_SDMA,
1144 };
1145
1146 /* dma attributes */
1147 static struct omap_dma_dev_attr dma_dev_attr = {
1148 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1149 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1150 .lch_count = 32,
1151 };
1152
1153 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1154 .rev_offs = 0x0000,
1155 .sysc_offs = 0x002c,
1156 .syss_offs = 0x0028,
1157 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1158 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1159 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
1160 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1161 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1162 .sysc_fields = &omap_hwmod_sysc_type1,
1163 };
1164
1165 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1166 .name = "dma",
1167 .sysc = &omap3xxx_dma_sysc,
1168 };
1169
1170 /* dma_system */
1171 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
1172 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1173 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1174 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1175 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1176 };
1177
1178 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
1179 {
1180 .pa_start = 0x48056000,
1181 .pa_end = 0x4a0560ff,
1182 .flags = ADDR_TYPE_RT
1183 },
1184 };
1185
1186 /* dma_system master ports */
1187 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
1188 &omap3xxx_dma_system__l3,
1189 };
1190
1191 /* l4_cfg -> dma_system */
1192 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
1193 .master = &omap3xxx_l4_core_hwmod,
1194 .slave = &omap3xxx_dma_system_hwmod,
1195 .clk = "core_l4_ick",
1196 .addr = omap3xxx_dma_system_addrs,
1197 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
1198 .user = OCP_USER_MPU | OCP_USER_SDMA,
1199 };
1200
1201 /* dma_system slave ports */
1202 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
1203 &omap3xxx_l4_core__dma_system,
1204 };
1205
1206 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1207 .name = "dma",
1208 .class = &omap3xxx_dma_hwmod_class,
1209 .mpu_irqs = omap3xxx_dma_system_irqs,
1210 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
1211 .main_clk = "core_l3_ick",
1212 .prcm = {
1213 .omap2 = {
1214 .module_offs = CORE_MOD,
1215 .prcm_reg_id = 1,
1216 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1217 .idlest_reg_id = 1,
1218 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1219 },
1220 },
1221 .slaves = omap3xxx_dma_system_slaves,
1222 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
1223 .masters = omap3xxx_dma_system_masters,
1224 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
1225 .dev_attr = &dma_dev_attr,
1226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1227 .flags = HWMOD_NO_IDLEST,
1228 };
1229
1230 /* SR common */
1231 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1232 .clkact_shift = 20,
1233 };
1234
1235 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1236 .sysc_offs = 0x24,
1237 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1238 .clockact = CLOCKACT_TEST_ICLK,
1239 .sysc_fields = &omap34xx_sr_sysc_fields,
1240 };
1241
1242 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1243 .name = "smartreflex",
1244 .sysc = &omap34xx_sr_sysc,
1245 .rev = 1,
1246 };
1247
1248 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1249 .sidle_shift = 24,
1250 .enwkup_shift = 26
1251 };
1252
1253 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1254 .sysc_offs = 0x38,
1255 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1256 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1257 SYSC_NO_CACHE),
1258 .sysc_fields = &omap36xx_sr_sysc_fields,
1259 };
1260
1261 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1262 .name = "smartreflex",
1263 .sysc = &omap36xx_sr_sysc,
1264 .rev = 2,
1265 };
1266
1267 /* SR1 */
1268 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
1269 &omap3_l4_core__sr1,
1270 };
1271
1272 static struct omap_hwmod omap34xx_sr1_hwmod = {
1273 .name = "sr1_hwmod",
1274 .class = &omap34xx_smartreflex_hwmod_class,
1275 .main_clk = "sr1_fck",
1276 .vdd_name = "mpu",
1277 .prcm = {
1278 .omap2 = {
1279 .prcm_reg_id = 1,
1280 .module_bit = OMAP3430_EN_SR1_SHIFT,
1281 .module_offs = WKUP_MOD,
1282 .idlest_reg_id = 1,
1283 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1284 },
1285 },
1286 .slaves = omap3_sr1_slaves,
1287 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
1288 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
1289 CHIP_IS_OMAP3430ES3_0 |
1290 CHIP_IS_OMAP3430ES3_1),
1291 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1292 };
1293
1294 static struct omap_hwmod omap36xx_sr1_hwmod = {
1295 .name = "sr1_hwmod",
1296 .class = &omap36xx_smartreflex_hwmod_class,
1297 .main_clk = "sr1_fck",
1298 .vdd_name = "mpu",
1299 .prcm = {
1300 .omap2 = {
1301 .prcm_reg_id = 1,
1302 .module_bit = OMAP3430_EN_SR1_SHIFT,
1303 .module_offs = WKUP_MOD,
1304 .idlest_reg_id = 1,
1305 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1306 },
1307 },
1308 .slaves = omap3_sr1_slaves,
1309 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
1310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1311 };
1312
1313 /* SR2 */
1314 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
1315 &omap3_l4_core__sr2,
1316 };
1317
1318 static struct omap_hwmod omap34xx_sr2_hwmod = {
1319 .name = "sr2_hwmod",
1320 .class = &omap34xx_smartreflex_hwmod_class,
1321 .main_clk = "sr2_fck",
1322 .vdd_name = "core",
1323 .prcm = {
1324 .omap2 = {
1325 .prcm_reg_id = 1,
1326 .module_bit = OMAP3430_EN_SR2_SHIFT,
1327 .module_offs = WKUP_MOD,
1328 .idlest_reg_id = 1,
1329 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1330 },
1331 },
1332 .slaves = omap3_sr2_slaves,
1333 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
1334 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
1335 CHIP_IS_OMAP3430ES3_0 |
1336 CHIP_IS_OMAP3430ES3_1),
1337 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1338 };
1339
1340 static struct omap_hwmod omap36xx_sr2_hwmod = {
1341 .name = "sr2_hwmod",
1342 .class = &omap36xx_smartreflex_hwmod_class,
1343 .main_clk = "sr2_fck",
1344 .vdd_name = "core",
1345 .prcm = {
1346 .omap2 = {
1347 .prcm_reg_id = 1,
1348 .module_bit = OMAP3430_EN_SR2_SHIFT,
1349 .module_offs = WKUP_MOD,
1350 .idlest_reg_id = 1,
1351 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1352 },
1353 },
1354 .slaves = omap3_sr2_slaves,
1355 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
1356 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1357 };
1358
1359 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1360 &omap3xxx_l3_main_hwmod,
1361 &omap3xxx_l4_core_hwmod,
1362 &omap3xxx_l4_per_hwmod,
1363 &omap3xxx_l4_wkup_hwmod,
1364 &omap3xxx_mpu_hwmod,
1365 &omap3xxx_iva_hwmod,
1366 &omap3xxx_wd_timer2_hwmod,
1367 &omap3xxx_uart1_hwmod,
1368 &omap3xxx_uart2_hwmod,
1369 &omap3xxx_uart3_hwmod,
1370 &omap3xxx_uart4_hwmod,
1371 &omap3xxx_i2c1_hwmod,
1372 &omap3xxx_i2c2_hwmod,
1373 &omap3xxx_i2c3_hwmod,
1374 &omap34xx_sr1_hwmod,
1375 &omap34xx_sr2_hwmod,
1376 &omap36xx_sr1_hwmod,
1377 &omap36xx_sr2_hwmod,
1378
1379
1380 /* gpio class */
1381 &omap3xxx_gpio1_hwmod,
1382 &omap3xxx_gpio2_hwmod,
1383 &omap3xxx_gpio3_hwmod,
1384 &omap3xxx_gpio4_hwmod,
1385 &omap3xxx_gpio5_hwmod,
1386 &omap3xxx_gpio6_hwmod,
1387
1388 /* dma_system class*/
1389 &omap3xxx_dma_system_hwmod,
1390 NULL,
1391 };
1392
1393 int __init omap3xxx_hwmod_init(void)
1394 {
1395 return omap_hwmod_init(omap3xxx_hwmods);
1396 }