arch/arm/mach-tcc8k/time.c

   1 /*
   2  * TCC8000 system timer setup
   3  *
   4  * (C) 2009 Hans J. Koch <hjk@linutronix.de>
   5  *
   6  * Licensed under the terms of the GPL version 2.
   7  *
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/spinlock.h>
  18
  19 #include <asm/mach/time.h>
  20
  21 #include <mach/tcc8k-regs.h>
  22 #include <mach/irqs.h>
  23
  24 #include "common.h"
  25
  26 static void __iomem *timer_base;
  27
  28 static cycle_t tcc_get_cycles(struct clocksource *cs)
  29 {
  30         return __raw_readl(timer_base + TC32MCNT_OFFS);
  31 }
  32
  33 static struct clocksource clocksource_tcc = {
  34         .name           = "tcc_tc32",
  35         .rating         = 200,
  36         .read           = tcc_get_cycles,
  37         .mask           = CLOCKSOURCE_MASK(32),
  38         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  39 };
  40
  41 static int tcc_set_next_event(unsigned long evt,
  42                               struct clock_event_device *unused)
  43 {
  44         unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
  45
  46         __raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
  47         return 0;
  48 }
  49
  50 static void tcc_set_mode(enum clock_event_mode mode,
  51                                 struct clock_event_device *evt)
  52 {
  53         unsigned long tc32irq;
  54
  55         switch (mode) {
  56         case CLOCK_EVT_MODE_ONESHOT:
  57                 tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
  58                 tc32irq |= TC32IRQ_IRQEN0;
  59                 __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
  60                 break;
  61         case CLOCK_EVT_MODE_SHUTDOWN:
  62         case CLOCK_EVT_MODE_UNUSED:
  63                 tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
  64                 tc32irq &= ~TC32IRQ_IRQEN0;
  65                 __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
  66                 break;
  67         case CLOCK_EVT_MODE_PERIODIC:
  68         case CLOCK_EVT_MODE_RESUME:
  69                 break;
  70         }
  71 }
  72
  73 static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
  74 {
  75         struct clock_event_device *evt = dev_id;
  76
  77         /* Acknowledge TC32 interrupt by reading TC32IRQ */
  78         __raw_readl(timer_base + TC32IRQ_OFFS);
  79
  80         evt->event_handler(evt);
  81
  82         return IRQ_HANDLED;
  83 }
  84
  85 static struct clock_event_device clockevent_tcc = {
  86         .name           = "tcc_timer1",
  87         .features       = CLOCK_EVT_FEAT_ONESHOT,
  88         .shift          = 32,
  89         .set_mode       = tcc_set_mode,
  90         .set_next_event = tcc_set_next_event,
  91         .rating         = 200,
  92 };
  93
  94 static struct irqaction tcc8k_timer_irq = {
  95         .name           = "TC32_timer",
  96         .flags          = IRQF_DISABLED | IRQF_TIMER,
  97         .handler        = tcc8k_timer_interrupt,
  98         .dev_id         = &clockevent_tcc,
  99 };
 100
 101 static int __init tcc_clockevent_init(struct clk *clock)
 102 {
 103         unsigned int c = clk_get_rate(clock);
 104
 105         clocksource_register_hz(&clocksource_tcc, c);
 106
 107         clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
 108                                         clockevent_tcc.shift);
 109         clockevent_tcc.max_delta_ns =
 110                         clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
 111         clockevent_tcc.min_delta_ns =
 112                         clockevent_delta2ns(0xff, &clockevent_tcc);
 113
 114         clockevent_tcc.cpumask = cpumask_of(0);
 115
 116         clockevents_register_device(&clockevent_tcc);
 117
 118         return 0;
 119 }
 120
 121 void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
 122 {
 123         u32 reg;
 124
 125         timer_base = base;
 126         tcc8k_timer_irq.irq = irq;
 127
 128         /* Enable clocks */
 129         clk_enable(clock);
 130
 131         /* Initialize 32-bit timer */
 132         reg = __raw_readl(timer_base + TC32EN_OFFS);
 133         reg &= ~TC32EN_ENABLE; /* Disable timer */
 134         __raw_writel(reg, timer_base + TC32EN_OFFS);
 135         /* Free running timer, counting from 0 to 0xffffffff */
 136         __raw_writel(0, timer_base + TC32EN_OFFS);
 137         __raw_writel(0, timer_base + TC32LDV_OFFS);
 138         reg = __raw_readl(timer_base + TC32IRQ_OFFS);
 139         reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
 140         __raw_writel(reg, timer_base + TC32IRQ_OFFS);
 141
 142         __raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
 143
 144         tcc_clockevent_init(clock);
 145         setup_irq(irq, &tcc8k_timer_irq);
 146 }