drivers/gpu/drm/radeon/r200.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "radeon_drm.h"
  31 #include "radeon_reg.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34
  35 #include "r100d.h"
  36 #include "r200_reg_safe.h"
  37
  38 #include "r100_track.h"
  39
  40 static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
  41 {
  42         int vtx_size, i;
  43         vtx_size = 2;
  44
  45         if (vtx_fmt_0 & R200_VTX_Z0)
  46                 vtx_size++;
  47         if (vtx_fmt_0 & R200_VTX_W0)
  48                 vtx_size++;
  49         /* blend weight */
  50         if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
  51                 vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
  52         if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
  53                 vtx_size++;
  54         if (vtx_fmt_0 & R200_VTX_N0)
  55                 vtx_size += 3;
  56         if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
  57                 vtx_size++;
  58         if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
  59                 vtx_size++;
  60         if (vtx_fmt_0 & R200_VTX_SHININESS_0)
  61                 vtx_size++;
  62         if (vtx_fmt_0 & R200_VTX_SHININESS_1)
  63                 vtx_size++;
  64         for (i = 0; i < 8; i++) {
  65                 int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
  66                 switch (color_size) {
  67                 case 0: break;
  68                 case 1: vtx_size++; break;
  69                 case 2: vtx_size += 3; break;
  70                 case 3: vtx_size += 4; break;
  71                 }
  72         }
  73         if (vtx_fmt_0 & R200_VTX_XY1)
  74                 vtx_size += 2;
  75         if (vtx_fmt_0 & R200_VTX_Z1)
  76                 vtx_size++;
  77         if (vtx_fmt_0 & R200_VTX_W1)
  78                 vtx_size++;
  79         if (vtx_fmt_0 & R200_VTX_N1)
  80                 vtx_size += 3;
  81         return vtx_size;
  82 }
  83
  84 int r200_copy_dma(struct radeon_device *rdev,
  85                   uint64_t src_offset,
  86                   uint64_t dst_offset,
  87                   unsigned num_gpu_pages,
  88                   struct radeon_fence *fence)
  89 {
  90         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  91         uint32_t size;
  92         uint32_t cur_size;
  93         int i, num_loops;
  94         int r = 0;
  95
  96         /* radeon pitch is /64 */
  97         size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
  98         num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
  99         r = radeon_ring_lock(rdev, ring, num_loops * 4 + 64);
 100         if (r) {
 101                 DRM_ERROR("radeon: moving bo (%d).\n", r);
 102                 return r;
 103         }
 104         /* Must wait for 2D idle & clean before DMA or hangs might happen */
 105         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 106         radeon_ring_write(ring, (1 << 16));
 107         for (i = 0; i < num_loops; i++) {
 108                 cur_size = size;
 109                 if (cur_size > 0x1FFFFF) {
 110                         cur_size = 0x1FFFFF;
 111                 }
 112                 size -= cur_size;
 113                 radeon_ring_write(ring, PACKET0(0x720, 2));
 114                 radeon_ring_write(ring, src_offset);
 115                 radeon_ring_write(ring, dst_offset);
 116                 radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30));
 117                 src_offset += cur_size;
 118                 dst_offset += cur_size;
 119         }
 120         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 121         radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);
 122         if (fence) {
 123                 r = radeon_fence_emit(rdev, fence);
 124         }
 125         radeon_ring_unlock_commit(rdev, ring);
 126         return r;
 127 }
 128
 129
 130 static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
 131 {
 132         int vtx_size, i, tex_size;
 133         vtx_size = 0;
 134         for (i = 0; i < 6; i++) {
 135                 tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
 136                 if (tex_size > 4)
 137                         continue;
 138                 vtx_size += tex_size;
 139         }
 140         return vtx_size;
 141 }
 142
 143 int r200_packet0_check(struct radeon_cs_parser *p,
 144                        struct radeon_cs_packet *pkt,
 145                        unsigned idx, unsigned reg)
 146 {
 147         struct radeon_cs_reloc *reloc;
 148         struct r100_cs_track *track;
 149         volatile uint32_t *ib;
 150         uint32_t tmp;
 151         int r;
 152         int i;
 153         int face;
 154         u32 tile_flags = 0;
 155         u32 idx_value;
 156
 157         ib = p->ib->ptr;
 158         track = (struct r100_cs_track *)p->track;
 159         idx_value = radeon_get_ib_value(p, idx);
 160         switch (reg) {
 161         case RADEON_CRTC_GUI_TRIG_VLINE:
 162                 r = r100_cs_packet_parse_vline(p);
 163                 if (r) {
 164                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 165                                   idx, reg);
 166                         r100_cs_dump_packet(p, pkt);
 167                         return r;
 168                 }
 169                 break;
 170                 /* FIXME: only allow PACKET3 blit? easier to check for out of
 171                  * range access */
 172         case RADEON_DST_PITCH_OFFSET:
 173         case RADEON_SRC_PITCH_OFFSET:
 174                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 175                 if (r)
 176                         return r;
 177                 break;
 178         case RADEON_RB3D_DEPTHOFFSET:
 179                 r = r100_cs_packet_next_reloc(p, &reloc);
 180                 if (r) {
 181                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 182                                   idx, reg);
 183                         r100_cs_dump_packet(p, pkt);
 184                         return r;
 185                 }
 186                 track->zb.robj = reloc->robj;
 187                 track->zb.offset = idx_value;
 188                 track->zb_dirty = true;
 189                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 190                 break;
 191         case RADEON_RB3D_COLOROFFSET:
 192                 r = r100_cs_packet_next_reloc(p, &reloc);
 193                 if (r) {
 194                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 195                                   idx, reg);
 196                         r100_cs_dump_packet(p, pkt);
 197                         return r;
 198                 }
 199                 track->cb[0].robj = reloc->robj;
 200                 track->cb[0].offset = idx_value;
 201                 track->cb_dirty = true;
 202                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 203                 break;
 204         case R200_PP_TXOFFSET_0:
 205         case R200_PP_TXOFFSET_1:
 206         case R200_PP_TXOFFSET_2:
 207         case R200_PP_TXOFFSET_3:
 208         case R200_PP_TXOFFSET_4:
 209         case R200_PP_TXOFFSET_5:
 210                 i = (reg - R200_PP_TXOFFSET_0) / 24;
 211                 r = r100_cs_packet_next_reloc(p, &reloc);
 212                 if (r) {
 213                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 214                                   idx, reg);
 215                         r100_cs_dump_packet(p, pkt);
 216                         return r;
 217                 }
 218                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 219                 track->textures[i].robj = reloc->robj;
 220                 track->tex_dirty = true;
 221                 break;
 222         case R200_PP_CUBIC_OFFSET_F1_0:
 223         case R200_PP_CUBIC_OFFSET_F2_0:
 224         case R200_PP_CUBIC_OFFSET_F3_0:
 225         case R200_PP_CUBIC_OFFSET_F4_0:
 226         case R200_PP_CUBIC_OFFSET_F5_0:
 227         case R200_PP_CUBIC_OFFSET_F1_1:
 228         case R200_PP_CUBIC_OFFSET_F2_1:
 229         case R200_PP_CUBIC_OFFSET_F3_1:
 230         case R200_PP_CUBIC_OFFSET_F4_1:
 231         case R200_PP_CUBIC_OFFSET_F5_1:
 232         case R200_PP_CUBIC_OFFSET_F1_2:
 233         case R200_PP_CUBIC_OFFSET_F2_2:
 234         case R200_PP_CUBIC_OFFSET_F3_2:
 235         case R200_PP_CUBIC_OFFSET_F4_2:
 236         case R200_PP_CUBIC_OFFSET_F5_2:
 237         case R200_PP_CUBIC_OFFSET_F1_3:
 238         case R200_PP_CUBIC_OFFSET_F2_3:
 239         case R200_PP_CUBIC_OFFSET_F3_3:
 240         case R200_PP_CUBIC_OFFSET_F4_3:
 241         case R200_PP_CUBIC_OFFSET_F5_3:
 242         case R200_PP_CUBIC_OFFSET_F1_4:
 243         case R200_PP_CUBIC_OFFSET_F2_4:
 244         case R200_PP_CUBIC_OFFSET_F3_4:
 245         case R200_PP_CUBIC_OFFSET_F4_4:
 246         case R200_PP_CUBIC_OFFSET_F5_4:
 247         case R200_PP_CUBIC_OFFSET_F1_5:
 248         case R200_PP_CUBIC_OFFSET_F2_5:
 249         case R200_PP_CUBIC_OFFSET_F3_5:
 250         case R200_PP_CUBIC_OFFSET_F4_5:
 251         case R200_PP_CUBIC_OFFSET_F5_5:
 252                 i = (reg - R200_PP_TXOFFSET_0) / 24;
 253                 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
 254                 r = r100_cs_packet_next_reloc(p, &reloc);
 255                 if (r) {
 256                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 257                                   idx, reg);
 258                         r100_cs_dump_packet(p, pkt);
 259                         return r;
 260                 }
 261                 track->textures[i].cube_info[face - 1].offset = idx_value;
 262                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 263                 track->textures[i].cube_info[face - 1].robj = reloc->robj;
 264                 track->tex_dirty = true;
 265                 break;
 266         case RADEON_RE_WIDTH_HEIGHT:
 267                 track->maxy = ((idx_value >> 16) & 0x7FF);
 268                 track->cb_dirty = true;
 269                 track->zb_dirty = true;
 270                 break;
 271         case RADEON_RB3D_COLORPITCH:
 272                 r = r100_cs_packet_next_reloc(p, &reloc);
 273                 if (r) {
 274                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 275                                   idx, reg);
 276                         r100_cs_dump_packet(p, pkt);
 277                         return r;
 278                 }
 279
 280                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 281                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
 282                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 283                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
 284
 285                 tmp = idx_value & ~(0x7 << 16);
 286                 tmp |= tile_flags;
 287                 ib[idx] = tmp;
 288
 289                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
 290                 track->cb_dirty = true;
 291                 break;
 292         case RADEON_RB3D_DEPTHPITCH:
 293                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
 294                 track->zb_dirty = true;
 295                 break;
 296         case RADEON_RB3D_CNTL:
 297                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
 298                 case 7:
 299                 case 8:
 300                 case 9:
 301                 case 11:
 302                 case 12:
 303                         track->cb[0].cpp = 1;
 304                         break;
 305                 case 3:
 306                 case 4:
 307                 case 15:
 308                         track->cb[0].cpp = 2;
 309                         break;
 310                 case 6:
 311                         track->cb[0].cpp = 4;
 312                         break;
 313                 default:
 314                         DRM_ERROR("Invalid color buffer format (%d) !\n",
 315                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
 316                         return -EINVAL;
 317                 }
 318                 if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
 319                         DRM_ERROR("No support for depth xy offset in kms\n");
 320                         return -EINVAL;
 321                 }
 322
 323                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
 324                 track->cb_dirty = true;
 325                 track->zb_dirty = true;
 326                 break;
 327         case RADEON_RB3D_ZSTENCILCNTL:
 328                 switch (idx_value & 0xf) {
 329                 case 0:
 330                         track->zb.cpp = 2;
 331                         break;
 332                 case 2:
 333                 case 3:
 334                 case 4:
 335                 case 5:
 336                 case 9:
 337                 case 11:
 338                         track->zb.cpp = 4;
 339                         break;
 340                 default:
 341                         break;
 342                 }
 343                 track->zb_dirty = true;
 344                 break;
 345         case RADEON_RB3D_ZPASS_ADDR:
 346                 r = r100_cs_packet_next_reloc(p, &reloc);
 347                 if (r) {
 348                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 349                                   idx, reg);
 350                         r100_cs_dump_packet(p, pkt);
 351                         return r;
 352                 }
 353                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 354                 break;
 355         case RADEON_PP_CNTL:
 356                 {
 357                         uint32_t temp = idx_value >> 4;
 358                         for (i = 0; i < track->num_texture; i++)
 359                                 track->textures[i].enabled = !!(temp & (1 << i));
 360                         track->tex_dirty = true;
 361                 }
 362                 break;
 363         case RADEON_SE_VF_CNTL:
 364                 track->vap_vf_cntl = idx_value;
 365                 break;
 366         case 0x210c:
 367                 /* VAP_VF_MAX_VTX_INDX */
 368                 track->max_indx = idx_value & 0x00FFFFFFUL;
 369                 break;
 370         case R200_SE_VTX_FMT_0:
 371                 track->vtx_size = r200_get_vtx_size_0(idx_value);
 372                 break;
 373         case R200_SE_VTX_FMT_1:
 374                 track->vtx_size += r200_get_vtx_size_1(idx_value);
 375                 break;
 376         case R200_PP_TXSIZE_0:
 377         case R200_PP_TXSIZE_1:
 378         case R200_PP_TXSIZE_2:
 379         case R200_PP_TXSIZE_3:
 380         case R200_PP_TXSIZE_4:
 381         case R200_PP_TXSIZE_5:
 382                 i = (reg - R200_PP_TXSIZE_0) / 32;
 383                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
 384                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
 385                 track->tex_dirty = true;
 386                 break;
 387         case R200_PP_TXPITCH_0:
 388         case R200_PP_TXPITCH_1:
 389         case R200_PP_TXPITCH_2:
 390         case R200_PP_TXPITCH_3:
 391         case R200_PP_TXPITCH_4:
 392         case R200_PP_TXPITCH_5:
 393                 i = (reg - R200_PP_TXPITCH_0) / 32;
 394                 track->textures[i].pitch = idx_value + 32;
 395                 track->tex_dirty = true;
 396                 break;
 397         case R200_PP_TXFILTER_0:
 398         case R200_PP_TXFILTER_1:
 399         case R200_PP_TXFILTER_2:
 400         case R200_PP_TXFILTER_3:
 401         case R200_PP_TXFILTER_4:
 402         case R200_PP_TXFILTER_5:
 403                 i = (reg - R200_PP_TXFILTER_0) / 32;
 404                 track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
 405                                                  >> R200_MAX_MIP_LEVEL_SHIFT);
 406                 tmp = (idx_value >> 23) & 0x7;
 407                 if (tmp == 2 || tmp == 6)
 408                         track->textures[i].roundup_w = false;
 409                 tmp = (idx_value >> 27) & 0x7;
 410                 if (tmp == 2 || tmp == 6)
 411                         track->textures[i].roundup_h = false;
 412                 track->tex_dirty = true;
 413                 break;
 414         case R200_PP_TXMULTI_CTL_0:
 415         case R200_PP_TXMULTI_CTL_1:
 416         case R200_PP_TXMULTI_CTL_2:
 417         case R200_PP_TXMULTI_CTL_3:
 418         case R200_PP_TXMULTI_CTL_4:
 419         case R200_PP_TXMULTI_CTL_5:
 420                 i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
 421                 break;
 422         case R200_PP_TXFORMAT_X_0:
 423         case R200_PP_TXFORMAT_X_1:
 424         case R200_PP_TXFORMAT_X_2:
 425         case R200_PP_TXFORMAT_X_3:
 426         case R200_PP_TXFORMAT_X_4:
 427         case R200_PP_TXFORMAT_X_5:
 428                 i = (reg - R200_PP_TXFORMAT_X_0) / 32;
 429                 track->textures[i].txdepth = idx_value & 0x7;
 430                 tmp = (idx_value >> 16) & 0x3;
 431                 /* 2D, 3D, CUBE */
 432                 switch (tmp) {
 433                 case 0:
 434                 case 3:
 435                 case 4:
 436                 case 5:
 437                 case 6:
 438                 case 7:
 439                         /* 1D/2D */
 440                         track->textures[i].tex_coord_type = 0;
 441                         break;
 442                 case 1:
 443                         /* CUBE */
 444                         track->textures[i].tex_coord_type = 2;
 445                         break;
 446                 case 2:
 447                         /* 3D */
 448                         track->textures[i].tex_coord_type = 1;
 449                         break;
 450                 }
 451                 track->tex_dirty = true;
 452                 break;
 453         case R200_PP_TXFORMAT_0:
 454         case R200_PP_TXFORMAT_1:
 455         case R200_PP_TXFORMAT_2:
 456         case R200_PP_TXFORMAT_3:
 457         case R200_PP_TXFORMAT_4:
 458         case R200_PP_TXFORMAT_5:
 459                 i = (reg - R200_PP_TXFORMAT_0) / 32;
 460                 if (idx_value & R200_TXFORMAT_NON_POWER2) {
 461                         track->textures[i].use_pitch = 1;
 462                 } else {
 463                         track->textures[i].use_pitch = 0;
 464                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
 465                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
 466                 }
 467                 if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
 468                         track->textures[i].lookup_disable = true;
 469                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
 470                 case R200_TXFORMAT_I8:
 471                 case R200_TXFORMAT_RGB332:
 472                 case R200_TXFORMAT_Y8:
 473                         track->textures[i].cpp = 1;
 474                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 475                         break;
 476                 case R200_TXFORMAT_AI88:
 477                 case R200_TXFORMAT_ARGB1555:
 478                 case R200_TXFORMAT_RGB565:
 479                 case R200_TXFORMAT_ARGB4444:
 480                 case R200_TXFORMAT_VYUY422:
 481                 case R200_TXFORMAT_YVYU422:
 482                 case R200_TXFORMAT_LDVDU655:
 483                 case R200_TXFORMAT_DVDU88:
 484                 case R200_TXFORMAT_AVYU4444:
 485                         track->textures[i].cpp = 2;
 486                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 487                         break;
 488                 case R200_TXFORMAT_ARGB8888:
 489                 case R200_TXFORMAT_RGBA8888:
 490                 case R200_TXFORMAT_ABGR8888:
 491                 case R200_TXFORMAT_BGR111110:
 492                 case R200_TXFORMAT_LDVDU8888:
 493                         track->textures[i].cpp = 4;
 494                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 495                         break;
 496                 case R200_TXFORMAT_DXT1:
 497                         track->textures[i].cpp = 1;
 498                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 499                         break;
 500                 case R200_TXFORMAT_DXT23:
 501                 case R200_TXFORMAT_DXT45:
 502                         track->textures[i].cpp = 1;
 503                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 504                         break;
 505                 }
 506                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
 507                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
 508                 track->tex_dirty = true;
 509                 break;
 510         case R200_PP_CUBIC_FACES_0:
 511         case R200_PP_CUBIC_FACES_1:
 512         case R200_PP_CUBIC_FACES_2:
 513         case R200_PP_CUBIC_FACES_3:
 514         case R200_PP_CUBIC_FACES_4:
 515         case R200_PP_CUBIC_FACES_5:
 516                 tmp = idx_value;
 517                 i = (reg - R200_PP_CUBIC_FACES_0) / 32;
 518                 for (face = 0; face < 4; face++) {
 519                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
 520                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
 521                 }
 522                 track->tex_dirty = true;
 523                 break;
 524         default:
 525                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
 526                        reg, idx);
 527                 return -EINVAL;
 528         }
 529         return 0;
 530 }
 531
 532 void r200_set_safe_registers(struct radeon_device *rdev)
 533 {
 534         rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
 535         rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
 536 }