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percpu, x86: don't use PMD_SIZE as embedded atom_size on 32bit
[zen-stable.git] / drivers / usb / gadget / omap_udc.c
blob7d0835e4bb927bebbd14e200cc65d33018bc5e3a
1 /*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15 #undef DEBUG
16 #undef VERBOSE
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/timer.h>
27 #include <linux/list.h>
28 #include <linux/interrupt.h>
29 #include <linux/proc_fs.h>
30 #include <linux/mm.h>
31 #include <linux/moduleparam.h>
32 #include <linux/platform_device.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/otg.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/prefetch.h>
39
40 #include <asm/byteorder.h>
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
45 #include <asm/mach-types.h>
46
47 #include <plat/dma.h>
48 #include <plat/usb.h>
49
50 #include "omap_udc.h"
51
52 #undef USB_TRACE
53
54 /* bulk DMA seems to be behaving for both IN and OUT */
55 #define USE_DMA
56
57 /* ISO too */
58 #define USE_ISO
59
60 #define DRIVER_DESC "OMAP UDC driver"
61 #define DRIVER_VERSION "4 October 2004"
62
63 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
64
65 #define OMAP2_DMA_CH(ch) (((ch) - 1) << 1)
66 #define OMAP24XX_DMA(name, ch) (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
67
68 /*
69 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
70 * D+ pullup to allow enumeration. That's too early for the gadget
71 * framework to use from usb_endpoint_enable(), which happens after
72 * enumeration as part of activating an interface. (But if we add an
73 * optional new "UDC not yet running" state to the gadget driver model,
74 * even just during driver binding, the endpoint autoconfig logic is the
75 * natural spot to manufacture new endpoints.)
76 *
77 * So instead of using endpoint enable calls to control the hardware setup,
78 * this driver defines a "fifo mode" parameter. It's used during driver
79 * initialization to choose among a set of pre-defined endpoint configs.
80 * See omap_udc_setup() for available modes, or to add others. That code
81 * lives in an init section, so use this driver as a module if you need
82 * to change the fifo mode after the kernel boots.
83 *
84 * Gadget drivers normally ignore endpoints they don't care about, and
85 * won't include them in configuration descriptors. That means only
86 * misbehaving hosts would even notice they exist.
87 */
88 #ifdef USE_ISO
89 static unsigned fifo_mode = 3;
90 #else
91 static unsigned fifo_mode = 0;
92 #endif
93
94 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
95 * boot parameter "omap_udc:fifo_mode=42"
96 */
97 module_param (fifo_mode, uint, 0);
98 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
99
100 #ifdef USE_DMA
101 static bool use_dma = 1;
102
103 /* "modprobe omap_udc use_dma=y", or else as a kernel
104 * boot parameter "omap_udc:use_dma=y"
105 */
106 module_param (use_dma, bool, 0);
107 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
108 #else /* !USE_DMA */
109
110 /* save a bit of code */
111 #define use_dma 0
112 #endif /* !USE_DMA */
113
114
115 static const char driver_name [] = "omap_udc";
116 static const char driver_desc [] = DRIVER_DESC;
117
118 /*-------------------------------------------------------------------------*/
119
120 /* there's a notion of "current endpoint" for modifying endpoint
121 * state, and PIO access to its FIFO.
122 */
123
124 static void use_ep(struct omap_ep *ep, u16 select)
125 {
126 u16 num = ep->bEndpointAddress & 0x0f;
127
128 if (ep->bEndpointAddress & USB_DIR_IN)
129 num |= UDC_EP_DIR;
130 omap_writew(num | select, UDC_EP_NUM);
131 /* when select, MUST deselect later !! */
132 }
133
134 static inline void deselect_ep(void)
135 {
136 u16 w;
137
138 w = omap_readw(UDC_EP_NUM);
139 w &= ~UDC_EP_SEL;
140 omap_writew(w, UDC_EP_NUM);
141 /* 6 wait states before TX will happen */
142 }
143
144 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
145
146 /*-------------------------------------------------------------------------*/
147
148 static int omap_ep_enable(struct usb_ep *_ep,
149 const struct usb_endpoint_descriptor *desc)
150 {
151 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
152 struct omap_udc *udc;
153 unsigned long flags;
154 u16 maxp;
155
156 /* catch various bogus parameters */
157 if (!_ep || !desc || ep->desc
158 || desc->bDescriptorType != USB_DT_ENDPOINT
159 || ep->bEndpointAddress != desc->bEndpointAddress
160 || ep->maxpacket < usb_endpoint_maxp(desc)) {
161 DBG("%s, bad ep or descriptor\n", __func__);
162 return -EINVAL;
163 }
164 maxp = usb_endpoint_maxp(desc);
165 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
166 && maxp != ep->maxpacket)
167 || usb_endpoint_maxp(desc) > ep->maxpacket
168 || !desc->wMaxPacketSize) {
169 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
170 return -ERANGE;
171 }
172
173 #ifdef USE_ISO
174 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
175 && desc->bInterval != 1)) {
176 /* hardware wants period = 1; USB allows 2^(Interval-1) */
177 DBG("%s, unsupported ISO period %dms\n", _ep->name,
178 1 << (desc->bInterval - 1));
179 return -EDOM;
180 }
181 #else
182 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
183 DBG("%s, ISO nyet\n", _ep->name);
184 return -EDOM;
185 }
186 #endif
187
188 /* xfer types must match, except that interrupt ~= bulk */
189 if (ep->bmAttributes != desc->bmAttributes
190 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
191 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
192 DBG("%s, %s type mismatch\n", __func__, _ep->name);
193 return -EINVAL;
194 }
195
196 udc = ep->udc;
197 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
198 DBG("%s, bogus device state\n", __func__);
199 return -ESHUTDOWN;
200 }
201
202 spin_lock_irqsave(&udc->lock, flags);
203
204 ep->desc = desc;
205 ep->irqs = 0;
206 ep->stopped = 0;
207 ep->ep.maxpacket = maxp;
208
209 /* set endpoint to initial state */
210 ep->dma_channel = 0;
211 ep->has_dma = 0;
212 ep->lch = -1;
213 use_ep(ep, UDC_EP_SEL);
214 omap_writew(udc->clr_halt, UDC_CTRL);
215 ep->ackwait = 0;
216 deselect_ep();
217
218 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
219 list_add(&ep->iso, &udc->iso);
220
221 /* maybe assign a DMA channel to this endpoint */
222 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
223 /* FIXME ISO can dma, but prefers first channel */
224 dma_channel_claim(ep, 0);
225
226 /* PIO OUT may RX packets */
227 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
228 && !ep->has_dma
229 && !(ep->bEndpointAddress & USB_DIR_IN)) {
230 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
231 ep->ackwait = 1 + ep->double_buf;
232 }
233
234 spin_unlock_irqrestore(&udc->lock, flags);
235 VDBG("%s enabled\n", _ep->name);
236 return 0;
237 }
238
239 static void nuke(struct omap_ep *, int status);
240
241 static int omap_ep_disable(struct usb_ep *_ep)
242 {
243 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
244 unsigned long flags;
245
246 if (!_ep || !ep->desc) {
247 DBG("%s, %s not enabled\n", __func__,
248 _ep ? ep->ep.name : NULL);
249 return -EINVAL;
250 }
251
252 spin_lock_irqsave(&ep->udc->lock, flags);
253 ep->desc = NULL;
254 ep->ep.desc = NULL;
255 nuke (ep, -ESHUTDOWN);
256 ep->ep.maxpacket = ep->maxpacket;
257 ep->has_dma = 0;
258 omap_writew(UDC_SET_HALT, UDC_CTRL);
259 list_del_init(&ep->iso);
260 del_timer(&ep->timer);
261
262 spin_unlock_irqrestore(&ep->udc->lock, flags);
263
264 VDBG("%s disabled\n", _ep->name);
265 return 0;
266 }
267
268 /*-------------------------------------------------------------------------*/
269
270 static struct usb_request *
271 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
272 {
273 struct omap_req *req;
274
275 req = kzalloc(sizeof(*req), gfp_flags);
276 if (req) {
277 req->req.dma = DMA_ADDR_INVALID;
278 INIT_LIST_HEAD (&req->queue);
279 }
280 return &req->req;
281 }
282
283 static void
284 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
285 {
286 struct omap_req *req = container_of(_req, struct omap_req, req);
287
288 if (_req)
289 kfree (req);
290 }
291
292 /*-------------------------------------------------------------------------*/
293
294 static void
295 done(struct omap_ep *ep, struct omap_req *req, int status)
296 {
297 unsigned stopped = ep->stopped;
298
299 list_del_init(&req->queue);
300
301 if (req->req.status == -EINPROGRESS)
302 req->req.status = status;
303 else
304 status = req->req.status;
305
306 if (use_dma && ep->has_dma) {
307 if (req->mapped) {
308 dma_unmap_single(ep->udc->gadget.dev.parent,
309 req->req.dma, req->req.length,
310 (ep->bEndpointAddress & USB_DIR_IN)
311 ? DMA_TO_DEVICE
312 : DMA_FROM_DEVICE);
313 req->req.dma = DMA_ADDR_INVALID;
314 req->mapped = 0;
315 } else
316 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
317 req->req.dma, req->req.length,
318 (ep->bEndpointAddress & USB_DIR_IN)
319 ? DMA_TO_DEVICE
320 : DMA_FROM_DEVICE);
321 }
322
323 #ifndef USB_TRACE
324 if (status && status != -ESHUTDOWN)
325 #endif
326 VDBG("complete %s req %p stat %d len %u/%u\n",
327 ep->ep.name, &req->req, status,
328 req->req.actual, req->req.length);
329
330 /* don't modify queue heads during completion callback */
331 ep->stopped = 1;
332 spin_unlock(&ep->udc->lock);
333 req->req.complete(&ep->ep, &req->req);
334 spin_lock(&ep->udc->lock);
335 ep->stopped = stopped;
336 }
337
338 /*-------------------------------------------------------------------------*/
339
340 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
341 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
342
343 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
344 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
345
346 static inline int
347 write_packet(u8 *buf, struct omap_req *req, unsigned max)
348 {
349 unsigned len;
350 u16 *wp;
351
352 len = min(req->req.length - req->req.actual, max);
353 req->req.actual += len;
354
355 max = len;
356 if (likely((((int)buf) & 1) == 0)) {
357 wp = (u16 *)buf;
358 while (max >= 2) {
359 omap_writew(*wp++, UDC_DATA);
360 max -= 2;
361 }
362 buf = (u8 *)wp;
363 }
364 while (max--)
365 omap_writeb(*buf++, UDC_DATA);
366 return len;
367 }
368
369 // FIXME change r/w fifo calling convention
370
371
372 // return: 0 = still running, 1 = completed, negative = errno
373 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
374 {
375 u8 *buf;
376 unsigned count;
377 int is_last;
378 u16 ep_stat;
379
380 buf = req->req.buf + req->req.actual;
381 prefetch(buf);
382
383 /* PIO-IN isn't double buffered except for iso */
384 ep_stat = omap_readw(UDC_STAT_FLG);
385 if (ep_stat & UDC_FIFO_UNWRITABLE)
386 return 0;
387
388 count = ep->ep.maxpacket;
389 count = write_packet(buf, req, count);
390 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
391 ep->ackwait = 1;
392
393 /* last packet is often short (sometimes a zlp) */
394 if (count != ep->ep.maxpacket)
395 is_last = 1;
396 else if (req->req.length == req->req.actual
397 && !req->req.zero)
398 is_last = 1;
399 else
400 is_last = 0;
401
402 /* NOTE: requests complete when all IN data is in a
403 * FIFO (or sometimes later, if a zlp was needed).
404 * Use usb_ep_fifo_status() where needed.
405 */
406 if (is_last)
407 done(ep, req, 0);
408 return is_last;
409 }
410
411 static inline int
412 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
413 {
414 unsigned len;
415 u16 *wp;
416
417 len = min(req->req.length - req->req.actual, avail);
418 req->req.actual += len;
419 avail = len;
420
421 if (likely((((int)buf) & 1) == 0)) {
422 wp = (u16 *)buf;
423 while (avail >= 2) {
424 *wp++ = omap_readw(UDC_DATA);
425 avail -= 2;
426 }
427 buf = (u8 *)wp;
428 }
429 while (avail--)
430 *buf++ = omap_readb(UDC_DATA);
431 return len;
432 }
433
434 // return: 0 = still running, 1 = queue empty, negative = errno
435 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
436 {
437 u8 *buf;
438 unsigned count, avail;
439 int is_last;
440
441 buf = req->req.buf + req->req.actual;
442 prefetchw(buf);
443
444 for (;;) {
445 u16 ep_stat = omap_readw(UDC_STAT_FLG);
446
447 is_last = 0;
448 if (ep_stat & FIFO_EMPTY) {
449 if (!ep->double_buf)
450 break;
451 ep->fnf = 1;
452 }
453 if (ep_stat & UDC_EP_HALTED)
454 break;
455
456 if (ep_stat & UDC_FIFO_FULL)
457 avail = ep->ep.maxpacket;
458 else {
459 avail = omap_readw(UDC_RXFSTAT);
460 ep->fnf = ep->double_buf;
461 }
462 count = read_packet(buf, req, avail);
463
464 /* partial packet reads may not be errors */
465 if (count < ep->ep.maxpacket) {
466 is_last = 1;
467 /* overflowed this request? flush extra data */
468 if (count != avail) {
469 req->req.status = -EOVERFLOW;
470 avail -= count;
471 while (avail--)
472 omap_readw(UDC_DATA);
473 }
474 } else if (req->req.length == req->req.actual)
475 is_last = 1;
476 else
477 is_last = 0;
478
479 if (!ep->bEndpointAddress)
480 break;
481 if (is_last)
482 done(ep, req, 0);
483 break;
484 }
485 return is_last;
486 }
487
488 /*-------------------------------------------------------------------------*/
489
490 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
491 {
492 dma_addr_t end;
493
494 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
495 * the last transfer's bytecount by more than a FIFO's worth.
496 */
497 if (cpu_is_omap15xx())
498 return 0;
499
500 end = omap_get_dma_src_pos(ep->lch);
501 if (end == ep->dma_counter)
502 return 0;
503
504 end |= start & (0xffff << 16);
505 if (end < start)
506 end += 0x10000;
507 return end - start;
508 }
509
510 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
511 {
512 dma_addr_t end;
513
514 end = omap_get_dma_dst_pos(ep->lch);
515 if (end == ep->dma_counter)
516 return 0;
517
518 end |= start & (0xffff << 16);
519 if (cpu_is_omap15xx())
520 end++;
521 if (end < start)
522 end += 0x10000;
523 return end - start;
524 }
525
526
527 /* Each USB transfer request using DMA maps to one or more DMA transfers.
528 * When DMA completion isn't request completion, the UDC continues with
529 * the next DMA transfer for that USB transfer.
530 */
531
532 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
533 {
534 u16 txdma_ctrl, w;
535 unsigned length = req->req.length - req->req.actual;
536 const int sync_mode = cpu_is_omap15xx()
537 ? OMAP_DMA_SYNC_FRAME
538 : OMAP_DMA_SYNC_ELEMENT;
539 int dma_trigger = 0;
540
541 if (cpu_is_omap24xx())
542 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
543
544 /* measure length in either bytes or packets */
545 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
546 || (cpu_is_omap24xx() && length < ep->maxpacket)
547 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
548 txdma_ctrl = UDC_TXN_EOT | length;
549 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
550 length, 1, sync_mode, dma_trigger, 0);
551 } else {
552 length = min(length / ep->maxpacket,
553 (unsigned) UDC_TXN_TSC + 1);
554 txdma_ctrl = length;
555 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
556 ep->ep.maxpacket >> 1, length, sync_mode,
557 dma_trigger, 0);
558 length *= ep->maxpacket;
559 }
560 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
561 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
562 0, 0);
563
564 omap_start_dma(ep->lch);
565 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
566 w = omap_readw(UDC_DMA_IRQ_EN);
567 w |= UDC_TX_DONE_IE(ep->dma_channel);
568 omap_writew(w, UDC_DMA_IRQ_EN);
569 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
570 req->dma_bytes = length;
571 }
572
573 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
574 {
575 u16 w;
576
577 if (status == 0) {
578 req->req.actual += req->dma_bytes;
579
580 /* return if this request needs to send data or zlp */
581 if (req->req.actual < req->req.length)
582 return;
583 if (req->req.zero
584 && req->dma_bytes != 0
585 && (req->req.actual % ep->maxpacket) == 0)
586 return;
587 } else
588 req->req.actual += dma_src_len(ep, req->req.dma
589 + req->req.actual);
590
591 /* tx completion */
592 omap_stop_dma(ep->lch);
593 w = omap_readw(UDC_DMA_IRQ_EN);
594 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
595 omap_writew(w, UDC_DMA_IRQ_EN);
596 done(ep, req, status);
597 }
598
599 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
600 {
601 unsigned packets = req->req.length - req->req.actual;
602 int dma_trigger = 0;
603 u16 w;
604
605 if (cpu_is_omap24xx())
606 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
607
608 /* NOTE: we filtered out "short reads" before, so we know
609 * the buffer has only whole numbers of packets.
610 * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
611 */
612 if (cpu_is_omap24xx() && packets < ep->maxpacket) {
613 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
614 packets, 1, OMAP_DMA_SYNC_ELEMENT,
615 dma_trigger, 0);
616 req->dma_bytes = packets;
617 } else {
618 /* set up this DMA transfer, enable the fifo, start */
619 packets /= ep->ep.maxpacket;
620 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
621 req->dma_bytes = packets * ep->ep.maxpacket;
622 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
623 ep->ep.maxpacket >> 1, packets,
624 OMAP_DMA_SYNC_ELEMENT,
625 dma_trigger, 0);
626 }
627 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
628 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
629 0, 0);
630 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
631
632 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
633 w = omap_readw(UDC_DMA_IRQ_EN);
634 w |= UDC_RX_EOT_IE(ep->dma_channel);
635 omap_writew(w, UDC_DMA_IRQ_EN);
636 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
637 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
638
639 omap_start_dma(ep->lch);
640 }
641
642 static void
643 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
644 {
645 u16 count, w;
646
647 if (status == 0)
648 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
649 count = dma_dest_len(ep, req->req.dma + req->req.actual);
650 count += req->req.actual;
651 if (one)
652 count--;
653 if (count <= req->req.length)
654 req->req.actual = count;
655
656 if (count != req->dma_bytes || status)
657 omap_stop_dma(ep->lch);
658
659 /* if this wasn't short, request may need another transfer */
660 else if (req->req.actual < req->req.length)
661 return;
662
663 /* rx completion */
664 w = omap_readw(UDC_DMA_IRQ_EN);
665 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
666 omap_writew(w, UDC_DMA_IRQ_EN);
667 done(ep, req, status);
668 }
669
670 static void dma_irq(struct omap_udc *udc, u16 irq_src)
671 {
672 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
673 struct omap_ep *ep;
674 struct omap_req *req;
675
676 /* IN dma: tx to host */
677 if (irq_src & UDC_TXN_DONE) {
678 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
679 ep->irqs++;
680 /* can see TXN_DONE after dma abort */
681 if (!list_empty(&ep->queue)) {
682 req = container_of(ep->queue.next,
683 struct omap_req, queue);
684 finish_in_dma(ep, req, 0);
685 }
686 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
687
688 if (!list_empty (&ep->queue)) {
689 req = container_of(ep->queue.next,
690 struct omap_req, queue);
691 next_in_dma(ep, req);
692 }
693 }
694
695 /* OUT dma: rx from host */
696 if (irq_src & UDC_RXN_EOT) {
697 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
698 ep->irqs++;
699 /* can see RXN_EOT after dma abort */
700 if (!list_empty(&ep->queue)) {
701 req = container_of(ep->queue.next,
702 struct omap_req, queue);
703 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
704 }
705 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
706
707 if (!list_empty (&ep->queue)) {
708 req = container_of(ep->queue.next,
709 struct omap_req, queue);
710 next_out_dma(ep, req);
711 }
712 }
713
714 if (irq_src & UDC_RXN_CNT) {
715 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
716 ep->irqs++;
717 /* omap15xx does this unasked... */
718 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
719 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
720 }
721 }
722
723 static void dma_error(int lch, u16 ch_status, void *data)
724 {
725 struct omap_ep *ep = data;
726
727 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
728 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
729 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
730
731 /* complete current transfer ... */
732 }
733
734 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
735 {
736 u16 reg;
737 int status, restart, is_in;
738 int dma_channel;
739
740 is_in = ep->bEndpointAddress & USB_DIR_IN;
741 if (is_in)
742 reg = omap_readw(UDC_TXDMA_CFG);
743 else
744 reg = omap_readw(UDC_RXDMA_CFG);
745 reg |= UDC_DMA_REQ; /* "pulse" activated */
746
747 ep->dma_channel = 0;
748 ep->lch = -1;
749 if (channel == 0 || channel > 3) {
750 if ((reg & 0x0f00) == 0)
751 channel = 3;
752 else if ((reg & 0x00f0) == 0)
753 channel = 2;
754 else if ((reg & 0x000f) == 0) /* preferred for ISO */
755 channel = 1;
756 else {
757 status = -EMLINK;
758 goto just_restart;
759 }
760 }
761 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
762 ep->dma_channel = channel;
763
764 if (is_in) {
765 if (cpu_is_omap24xx())
766 dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
767 else
768 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
769 status = omap_request_dma(dma_channel,
770 ep->ep.name, dma_error, ep, &ep->lch);
771 if (status == 0) {
772 omap_writew(reg, UDC_TXDMA_CFG);
773 /* EMIFF or SDRC */
774 omap_set_dma_src_burst_mode(ep->lch,
775 OMAP_DMA_DATA_BURST_4);
776 omap_set_dma_src_data_pack(ep->lch, 1);
777 /* TIPB */
778 omap_set_dma_dest_params(ep->lch,
779 OMAP_DMA_PORT_TIPB,
780 OMAP_DMA_AMODE_CONSTANT,
781 UDC_DATA_DMA,
782 0, 0);
783 }
784 } else {
785 if (cpu_is_omap24xx())
786 dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
787 else
788 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
789
790 status = omap_request_dma(dma_channel,
791 ep->ep.name, dma_error, ep, &ep->lch);
792 if (status == 0) {
793 omap_writew(reg, UDC_RXDMA_CFG);
794 /* TIPB */
795 omap_set_dma_src_params(ep->lch,
796 OMAP_DMA_PORT_TIPB,
797 OMAP_DMA_AMODE_CONSTANT,
798 UDC_DATA_DMA,
799 0, 0);
800 /* EMIFF or SDRC */
801 omap_set_dma_dest_burst_mode(ep->lch,
802 OMAP_DMA_DATA_BURST_4);
803 omap_set_dma_dest_data_pack(ep->lch, 1);
804 }
805 }
806 if (status)
807 ep->dma_channel = 0;
808 else {
809 ep->has_dma = 1;
810 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
811
812 /* channel type P: hw synch (fifo) */
813 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
814 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
815 }
816
817 just_restart:
818 /* restart any queue, even if the claim failed */
819 restart = !ep->stopped && !list_empty(&ep->queue);
820
821 if (status)
822 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
823 restart ? " (restart)" : "");
824 else
825 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
826 is_in ? 't' : 'r',
827 ep->dma_channel - 1, ep->lch,
828 restart ? " (restart)" : "");
829
830 if (restart) {
831 struct omap_req *req;
832 req = container_of(ep->queue.next, struct omap_req, queue);
833 if (ep->has_dma)
834 (is_in ? next_in_dma : next_out_dma)(ep, req);
835 else {
836 use_ep(ep, UDC_EP_SEL);
837 (is_in ? write_fifo : read_fifo)(ep, req);
838 deselect_ep();
839 if (!is_in) {
840 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
841 ep->ackwait = 1 + ep->double_buf;
842 }
843 /* IN: 6 wait states before it'll tx */
844 }
845 }
846 }
847
848 static void dma_channel_release(struct omap_ep *ep)
849 {
850 int shift = 4 * (ep->dma_channel - 1);
851 u16 mask = 0x0f << shift;
852 struct omap_req *req;
853 int active;
854
855 /* abort any active usb transfer request */
856 if (!list_empty(&ep->queue))
857 req = container_of(ep->queue.next, struct omap_req, queue);
858 else
859 req = NULL;
860
861 active = omap_get_dma_active_status(ep->lch);
862
863 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
864 active ? "active" : "idle",
865 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
866 ep->dma_channel - 1, req);
867
868 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
869 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
870 */
871
872 /* wait till current packet DMA finishes, and fifo empties */
873 if (ep->bEndpointAddress & USB_DIR_IN) {
874 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
875 UDC_TXDMA_CFG);
876
877 if (req) {
878 finish_in_dma(ep, req, -ECONNRESET);
879
880 /* clear FIFO; hosts probably won't empty it */
881 use_ep(ep, UDC_EP_SEL);
882 omap_writew(UDC_CLR_EP, UDC_CTRL);
883 deselect_ep();
884 }
885 while (omap_readw(UDC_TXDMA_CFG) & mask)
886 udelay(10);
887 } else {
888 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
889 UDC_RXDMA_CFG);
890
891 /* dma empties the fifo */
892 while (omap_readw(UDC_RXDMA_CFG) & mask)
893 udelay(10);
894 if (req)
895 finish_out_dma(ep, req, -ECONNRESET, 0);
896 }
897 omap_free_dma(ep->lch);
898 ep->dma_channel = 0;
899 ep->lch = -1;
900 /* has_dma still set, till endpoint is fully quiesced */
901 }
902
903
904 /*-------------------------------------------------------------------------*/
905
906 static int
907 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
908 {
909 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
910 struct omap_req *req = container_of(_req, struct omap_req, req);
911 struct omap_udc *udc;
912 unsigned long flags;
913 int is_iso = 0;
914
915 /* catch various bogus parameters */
916 if (!_req || !req->req.complete || !req->req.buf
917 || !list_empty(&req->queue)) {
918 DBG("%s, bad params\n", __func__);
919 return -EINVAL;
920 }
921 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
922 DBG("%s, bad ep\n", __func__);
923 return -EINVAL;
924 }
925 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
926 if (req->req.length > ep->ep.maxpacket)
927 return -EMSGSIZE;
928 is_iso = 1;
929 }
930
931 /* this isn't bogus, but OMAP DMA isn't the only hardware to
932 * have a hard time with partial packet reads... reject it.
933 * Except OMAP2 can handle the small packets.
934 */
935 if (use_dma
936 && ep->has_dma
937 && ep->bEndpointAddress != 0
938 && (ep->bEndpointAddress & USB_DIR_IN) == 0
939 && !cpu_class_is_omap2()
940 && (req->req.length % ep->ep.maxpacket) != 0) {
941 DBG("%s, no partial packet OUT reads\n", __func__);
942 return -EMSGSIZE;
943 }
944
945 udc = ep->udc;
946 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
947 return -ESHUTDOWN;
948
949 if (use_dma && ep->has_dma) {
950 if (req->req.dma == DMA_ADDR_INVALID) {
951 req->req.dma = dma_map_single(
952 ep->udc->gadget.dev.parent,
953 req->req.buf,
954 req->req.length,
955 (ep->bEndpointAddress & USB_DIR_IN)
956 ? DMA_TO_DEVICE
957 : DMA_FROM_DEVICE);
958 req->mapped = 1;
959 } else {
960 dma_sync_single_for_device(
961 ep->udc->gadget.dev.parent,
962 req->req.dma, req->req.length,
963 (ep->bEndpointAddress & USB_DIR_IN)
964 ? DMA_TO_DEVICE
965 : DMA_FROM_DEVICE);
966 req->mapped = 0;
967 }
968 }
969
970 VDBG("%s queue req %p, len %d buf %p\n",
971 ep->ep.name, _req, _req->length, _req->buf);
972
973 spin_lock_irqsave(&udc->lock, flags);
974
975 req->req.status = -EINPROGRESS;
976 req->req.actual = 0;
977
978 /* maybe kickstart non-iso i/o queues */
979 if (is_iso) {
980 u16 w;
981
982 w = omap_readw(UDC_IRQ_EN);
983 w |= UDC_SOF_IE;
984 omap_writew(w, UDC_IRQ_EN);
985 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
986 int is_in;
987
988 if (ep->bEndpointAddress == 0) {
989 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
990 spin_unlock_irqrestore(&udc->lock, flags);
991 return -EL2HLT;
992 }
993
994 /* empty DATA stage? */
995 is_in = udc->ep0_in;
996 if (!req->req.length) {
997
998 /* chip became CONFIGURED or ADDRESSED
999 * earlier; drivers may already have queued
1000 * requests to non-control endpoints
1001 */
1002 if (udc->ep0_set_config) {
1003 u16 irq_en = omap_readw(UDC_IRQ_EN);
1004
1005 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1006 if (!udc->ep0_reset_config)
1007 irq_en |= UDC_EPN_RX_IE
1008 | UDC_EPN_TX_IE;
1009 omap_writew(irq_en, UDC_IRQ_EN);
1010 }
1011
1012 /* STATUS for zero length DATA stages is
1013 * always an IN ... even for IN transfers,
1014 * a weird case which seem to stall OMAP.
1015 */
1016 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1017 omap_writew(UDC_CLR_EP, UDC_CTRL);
1018 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1019 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1020
1021 /* cleanup */
1022 udc->ep0_pending = 0;
1023 done(ep, req, 0);
1024 req = NULL;
1025
1026 /* non-empty DATA stage */
1027 } else if (is_in) {
1028 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1029 } else {
1030 if (udc->ep0_setup)
1031 goto irq_wait;
1032 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1033 }
1034 } else {
1035 is_in = ep->bEndpointAddress & USB_DIR_IN;
1036 if (!ep->has_dma)
1037 use_ep(ep, UDC_EP_SEL);
1038 /* if ISO: SOF IRQs must be enabled/disabled! */
1039 }
1040
1041 if (ep->has_dma)
1042 (is_in ? next_in_dma : next_out_dma)(ep, req);
1043 else if (req) {
1044 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1045 req = NULL;
1046 deselect_ep();
1047 if (!is_in) {
1048 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1049 ep->ackwait = 1 + ep->double_buf;
1050 }
1051 /* IN: 6 wait states before it'll tx */
1052 }
1053 }
1054
1055 irq_wait:
1056 /* irq handler advances the queue */
1057 if (req != NULL)
1058 list_add_tail(&req->queue, &ep->queue);
1059 spin_unlock_irqrestore(&udc->lock, flags);
1060
1061 return 0;
1062 }
1063
1064 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1065 {
1066 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1067 struct omap_req *req;
1068 unsigned long flags;
1069
1070 if (!_ep || !_req)
1071 return -EINVAL;
1072
1073 spin_lock_irqsave(&ep->udc->lock, flags);
1074
1075 /* make sure it's actually queued on this endpoint */
1076 list_for_each_entry (req, &ep->queue, queue) {
1077 if (&req->req == _req)
1078 break;
1079 }
1080 if (&req->req != _req) {
1081 spin_unlock_irqrestore(&ep->udc->lock, flags);
1082 return -EINVAL;
1083 }
1084
1085 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1086 int channel = ep->dma_channel;
1087
1088 /* releasing the channel cancels the request,
1089 * reclaiming the channel restarts the queue
1090 */
1091 dma_channel_release(ep);
1092 dma_channel_claim(ep, channel);
1093 } else
1094 done(ep, req, -ECONNRESET);
1095 spin_unlock_irqrestore(&ep->udc->lock, flags);
1096 return 0;
1097 }
1098
1099 /*-------------------------------------------------------------------------*/
1100
1101 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1102 {
1103 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1104 unsigned long flags;
1105 int status = -EOPNOTSUPP;
1106
1107 spin_lock_irqsave(&ep->udc->lock, flags);
1108
1109 /* just use protocol stalls for ep0; real halts are annoying */
1110 if (ep->bEndpointAddress == 0) {
1111 if (!ep->udc->ep0_pending)
1112 status = -EINVAL;
1113 else if (value) {
1114 if (ep->udc->ep0_set_config) {
1115 WARNING("error changing config?\n");
1116 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1117 }
1118 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1119 ep->udc->ep0_pending = 0;
1120 status = 0;
1121 } else /* NOP */
1122 status = 0;
1123
1124 /* otherwise, all active non-ISO endpoints can halt */
1125 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1126
1127 /* IN endpoints must already be idle */
1128 if ((ep->bEndpointAddress & USB_DIR_IN)
1129 && !list_empty(&ep->queue)) {
1130 status = -EAGAIN;
1131 goto done;
1132 }
1133
1134 if (value) {
1135 int channel;
1136
1137 if (use_dma && ep->dma_channel
1138 && !list_empty(&ep->queue)) {
1139 channel = ep->dma_channel;
1140 dma_channel_release(ep);
1141 } else
1142 channel = 0;
1143
1144 use_ep(ep, UDC_EP_SEL);
1145 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1146 omap_writew(UDC_SET_HALT, UDC_CTRL);
1147 status = 0;
1148 } else
1149 status = -EAGAIN;
1150 deselect_ep();
1151
1152 if (channel)
1153 dma_channel_claim(ep, channel);
1154 } else {
1155 use_ep(ep, 0);
1156 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1157 ep->ackwait = 0;
1158 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1159 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1160 ep->ackwait = 1 + ep->double_buf;
1161 }
1162 }
1163 }
1164 done:
1165 VDBG("%s %s halt stat %d\n", ep->ep.name,
1166 value ? "set" : "clear", status);
1167
1168 spin_unlock_irqrestore(&ep->udc->lock, flags);
1169 return status;
1170 }
1171
1172 static struct usb_ep_ops omap_ep_ops = {
1173 .enable = omap_ep_enable,
1174 .disable = omap_ep_disable,
1175
1176 .alloc_request = omap_alloc_request,
1177 .free_request = omap_free_request,
1178
1179 .queue = omap_ep_queue,
1180 .dequeue = omap_ep_dequeue,
1181
1182 .set_halt = omap_ep_set_halt,
1183 // fifo_status ... report bytes in fifo
1184 // fifo_flush ... flush fifo
1185 };
1186
1187 /*-------------------------------------------------------------------------*/
1188
1189 static int omap_get_frame(struct usb_gadget *gadget)
1190 {
1191 u16 sof = omap_readw(UDC_SOF);
1192 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1193 }
1194
1195 static int omap_wakeup(struct usb_gadget *gadget)
1196 {
1197 struct omap_udc *udc;
1198 unsigned long flags;
1199 int retval = -EHOSTUNREACH;
1200
1201 udc = container_of(gadget, struct omap_udc, gadget);
1202
1203 spin_lock_irqsave(&udc->lock, flags);
1204 if (udc->devstat & UDC_SUS) {
1205 /* NOTE: OTG spec erratum says that OTG devices may
1206 * issue wakeups without host enable.
1207 */
1208 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1209 DBG("remote wakeup...\n");
1210 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1211 retval = 0;
1212 }
1213
1214 /* NOTE: non-OTG systems may use SRP TOO... */
1215 } else if (!(udc->devstat & UDC_ATT)) {
1216 if (udc->transceiver)
1217 retval = otg_start_srp(udc->transceiver);
1218 }
1219 spin_unlock_irqrestore(&udc->lock, flags);
1220
1221 return retval;
1222 }
1223
1224 static int
1225 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1226 {
1227 struct omap_udc *udc;
1228 unsigned long flags;
1229 u16 syscon1;
1230
1231 udc = container_of(gadget, struct omap_udc, gadget);
1232 spin_lock_irqsave(&udc->lock, flags);
1233 syscon1 = omap_readw(UDC_SYSCON1);
1234 if (is_selfpowered)
1235 syscon1 |= UDC_SELF_PWR;
1236 else
1237 syscon1 &= ~UDC_SELF_PWR;
1238 omap_writew(syscon1, UDC_SYSCON1);
1239 spin_unlock_irqrestore(&udc->lock, flags);
1240
1241 return 0;
1242 }
1243
1244 static int can_pullup(struct omap_udc *udc)
1245 {
1246 return udc->driver && udc->softconnect && udc->vbus_active;
1247 }
1248
1249 static void pullup_enable(struct omap_udc *udc)
1250 {
1251 u16 w;
1252
1253 w = omap_readw(UDC_SYSCON1);
1254 w |= UDC_PULLUP_EN;
1255 omap_writew(w, UDC_SYSCON1);
1256 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1257 u32 l;
1258
1259 l = omap_readl(OTG_CTRL);
1260 l |= OTG_BSESSVLD;
1261 omap_writel(l, OTG_CTRL);
1262 }
1263 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1264 }
1265
1266 static void pullup_disable(struct omap_udc *udc)
1267 {
1268 u16 w;
1269
1270 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1271 u32 l;
1272
1273 l = omap_readl(OTG_CTRL);
1274 l &= ~OTG_BSESSVLD;
1275 omap_writel(l, OTG_CTRL);
1276 }
1277 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1278 w = omap_readw(UDC_SYSCON1);
1279 w &= ~UDC_PULLUP_EN;
1280 omap_writew(w, UDC_SYSCON1);
1281 }
1282
1283 static struct omap_udc *udc;
1284
1285 static void omap_udc_enable_clock(int enable)
1286 {
1287 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1288 return;
1289
1290 if (enable) {
1291 clk_enable(udc->dc_clk);
1292 clk_enable(udc->hhc_clk);
1293 udelay(100);
1294 } else {
1295 clk_disable(udc->hhc_clk);
1296 clk_disable(udc->dc_clk);
1297 }
1298 }
1299
1300 /*
1301 * Called by whatever detects VBUS sessions: external transceiver
1302 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1303 */
1304 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1305 {
1306 struct omap_udc *udc;
1307 unsigned long flags;
1308 u32 l;
1309
1310 udc = container_of(gadget, struct omap_udc, gadget);
1311 spin_lock_irqsave(&udc->lock, flags);
1312 VDBG("VBUS %s\n", is_active ? "on" : "off");
1313 udc->vbus_active = (is_active != 0);
1314 if (cpu_is_omap15xx()) {
1315 /* "software" detect, ignored if !VBUS_MODE_1510 */
1316 l = omap_readl(FUNC_MUX_CTRL_0);
1317 if (is_active)
1318 l |= VBUS_CTRL_1510;
1319 else
1320 l &= ~VBUS_CTRL_1510;
1321 omap_writel(l, FUNC_MUX_CTRL_0);
1322 }
1323 if (udc->dc_clk != NULL && is_active) {
1324 if (!udc->clk_requested) {
1325 omap_udc_enable_clock(1);
1326 udc->clk_requested = 1;
1327 }
1328 }
1329 if (can_pullup(udc))
1330 pullup_enable(udc);
1331 else
1332 pullup_disable(udc);
1333 if (udc->dc_clk != NULL && !is_active) {
1334 if (udc->clk_requested) {
1335 omap_udc_enable_clock(0);
1336 udc->clk_requested = 0;
1337 }
1338 }
1339 spin_unlock_irqrestore(&udc->lock, flags);
1340 return 0;
1341 }
1342
1343 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1344 {
1345 struct omap_udc *udc;
1346
1347 udc = container_of(gadget, struct omap_udc, gadget);
1348 if (udc->transceiver)
1349 return otg_set_power(udc->transceiver, mA);
1350 return -EOPNOTSUPP;
1351 }
1352
1353 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1354 {
1355 struct omap_udc *udc;
1356 unsigned long flags;
1357
1358 udc = container_of(gadget, struct omap_udc, gadget);
1359 spin_lock_irqsave(&udc->lock, flags);
1360 udc->softconnect = (is_on != 0);
1361 if (can_pullup(udc))
1362 pullup_enable(udc);
1363 else
1364 pullup_disable(udc);
1365 spin_unlock_irqrestore(&udc->lock, flags);
1366 return 0;
1367 }
1368
1369 static int omap_udc_start(struct usb_gadget_driver *driver,
1370 int (*bind)(struct usb_gadget *));
1371 static int omap_udc_stop(struct usb_gadget_driver *driver);
1372
1373 static struct usb_gadget_ops omap_gadget_ops = {
1374 .get_frame = omap_get_frame,
1375 .wakeup = omap_wakeup,
1376 .set_selfpowered = omap_set_selfpowered,
1377 .vbus_session = omap_vbus_session,
1378 .vbus_draw = omap_vbus_draw,
1379 .pullup = omap_pullup,
1380 .start = omap_udc_start,
1381 .stop = omap_udc_stop,
1382 };
1383
1384 /*-------------------------------------------------------------------------*/
1385
1386 /* dequeue ALL requests; caller holds udc->lock */
1387 static void nuke(struct omap_ep *ep, int status)
1388 {
1389 struct omap_req *req;
1390
1391 ep->stopped = 1;
1392
1393 if (use_dma && ep->dma_channel)
1394 dma_channel_release(ep);
1395
1396 use_ep(ep, 0);
1397 omap_writew(UDC_CLR_EP, UDC_CTRL);
1398 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1399 omap_writew(UDC_SET_HALT, UDC_CTRL);
1400
1401 while (!list_empty(&ep->queue)) {
1402 req = list_entry(ep->queue.next, struct omap_req, queue);
1403 done(ep, req, status);
1404 }
1405 }
1406
1407 /* caller holds udc->lock */
1408 static void udc_quiesce(struct omap_udc *udc)
1409 {
1410 struct omap_ep *ep;
1411
1412 udc->gadget.speed = USB_SPEED_UNKNOWN;
1413 nuke(&udc->ep[0], -ESHUTDOWN);
1414 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1415 nuke(ep, -ESHUTDOWN);
1416 }
1417
1418 /*-------------------------------------------------------------------------*/
1419
1420 static void update_otg(struct omap_udc *udc)
1421 {
1422 u16 devstat;
1423
1424 if (!gadget_is_otg(&udc->gadget))
1425 return;
1426
1427 if (omap_readl(OTG_CTRL) & OTG_ID)
1428 devstat = omap_readw(UDC_DEVSTAT);
1429 else
1430 devstat = 0;
1431
1432 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1433 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1434 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1435
1436 /* Enable HNP early, avoiding races on suspend irq path.
1437 * ASSUMES OTG state machine B_BUS_REQ input is true.
1438 */
1439 if (udc->gadget.b_hnp_enable) {
1440 u32 l;
1441
1442 l = omap_readl(OTG_CTRL);
1443 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1444 l &= ~OTG_PULLUP;
1445 omap_writel(l, OTG_CTRL);
1446 }
1447 }
1448
1449 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1450 {
1451 struct omap_ep *ep0 = &udc->ep[0];
1452 struct omap_req *req = NULL;
1453
1454 ep0->irqs++;
1455
1456 /* Clear any pending requests and then scrub any rx/tx state
1457 * before starting to handle the SETUP request.
1458 */
1459 if (irq_src & UDC_SETUP) {
1460 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1461
1462 nuke(ep0, 0);
1463 if (ack) {
1464 omap_writew(ack, UDC_IRQ_SRC);
1465 irq_src = UDC_SETUP;
1466 }
1467 }
1468
1469 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1470 * This driver uses only uses protocol stalls (ep0 never halts),
1471 * and if we got this far the gadget driver already had a
1472 * chance to stall. Tries to be forgiving of host oddities.
1473 *
1474 * NOTE: the last chance gadget drivers have to stall control
1475 * requests is during their request completion callback.
1476 */
1477 if (!list_empty(&ep0->queue))
1478 req = container_of(ep0->queue.next, struct omap_req, queue);
1479
1480 /* IN == TX to host */
1481 if (irq_src & UDC_EP0_TX) {
1482 int stat;
1483
1484 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1485 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1486 stat = omap_readw(UDC_STAT_FLG);
1487 if (stat & UDC_ACK) {
1488 if (udc->ep0_in) {
1489 /* write next IN packet from response,
1490 * or set up the status stage.
1491 */
1492 if (req)
1493 stat = write_fifo(ep0, req);
1494 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1495 if (!req && udc->ep0_pending) {
1496 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1497 omap_writew(UDC_CLR_EP, UDC_CTRL);
1498 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1499 omap_writew(0, UDC_EP_NUM);
1500 udc->ep0_pending = 0;
1501 } /* else: 6 wait states before it'll tx */
1502 } else {
1503 /* ack status stage of OUT transfer */
1504 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1505 if (req)
1506 done(ep0, req, 0);
1507 }
1508 req = NULL;
1509 } else if (stat & UDC_STALL) {
1510 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1511 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1512 } else {
1513 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1514 }
1515 }
1516
1517 /* OUT == RX from host */
1518 if (irq_src & UDC_EP0_RX) {
1519 int stat;
1520
1521 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1522 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1523 stat = omap_readw(UDC_STAT_FLG);
1524 if (stat & UDC_ACK) {
1525 if (!udc->ep0_in) {
1526 stat = 0;
1527 /* read next OUT packet of request, maybe
1528 * reactiviting the fifo; stall on errors.
1529 */
1530 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1531 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1532 udc->ep0_pending = 0;
1533 stat = 0;
1534 } else if (stat == 0)
1535 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1536 omap_writew(0, UDC_EP_NUM);
1537
1538 /* activate status stage */
1539 if (stat == 1) {
1540 done(ep0, req, 0);
1541 /* that may have STALLed ep0... */
1542 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1543 UDC_EP_NUM);
1544 omap_writew(UDC_CLR_EP, UDC_CTRL);
1545 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1546 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1547 udc->ep0_pending = 0;
1548 }
1549 } else {
1550 /* ack status stage of IN transfer */
1551 omap_writew(0, UDC_EP_NUM);
1552 if (req)
1553 done(ep0, req, 0);
1554 }
1555 } else if (stat & UDC_STALL) {
1556 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1557 omap_writew(0, UDC_EP_NUM);
1558 } else {
1559 omap_writew(0, UDC_EP_NUM);
1560 }
1561 }
1562
1563 /* SETUP starts all control transfers */
1564 if (irq_src & UDC_SETUP) {
1565 union u {
1566 u16 word[4];
1567 struct usb_ctrlrequest r;
1568 } u;
1569 int status = -EINVAL;
1570 struct omap_ep *ep;
1571
1572 /* read the (latest) SETUP message */
1573 do {
1574 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1575 /* two bytes at a time */
1576 u.word[0] = omap_readw(UDC_DATA);
1577 u.word[1] = omap_readw(UDC_DATA);
1578 u.word[2] = omap_readw(UDC_DATA);
1579 u.word[3] = omap_readw(UDC_DATA);
1580 omap_writew(0, UDC_EP_NUM);
1581 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1582
1583 #define w_value le16_to_cpu(u.r.wValue)
1584 #define w_index le16_to_cpu(u.r.wIndex)
1585 #define w_length le16_to_cpu(u.r.wLength)
1586
1587 /* Delegate almost all control requests to the gadget driver,
1588 * except for a handful of ch9 status/feature requests that
1589 * hardware doesn't autodecode _and_ the gadget API hides.
1590 */
1591 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1592 udc->ep0_set_config = 0;
1593 udc->ep0_pending = 1;
1594 ep0->stopped = 0;
1595 ep0->ackwait = 0;
1596 switch (u.r.bRequest) {
1597 case USB_REQ_SET_CONFIGURATION:
1598 /* udc needs to know when ep != 0 is valid */
1599 if (u.r.bRequestType != USB_RECIP_DEVICE)
1600 goto delegate;
1601 if (w_length != 0)
1602 goto do_stall;
1603 udc->ep0_set_config = 1;
1604 udc->ep0_reset_config = (w_value == 0);
1605 VDBG("set config %d\n", w_value);
1606
1607 /* update udc NOW since gadget driver may start
1608 * queueing requests immediately; clear config
1609 * later if it fails the request.
1610 */
1611 if (udc->ep0_reset_config)
1612 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1613 else
1614 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1615 update_otg(udc);
1616 goto delegate;
1617 case USB_REQ_CLEAR_FEATURE:
1618 /* clear endpoint halt */
1619 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1620 goto delegate;
1621 if (w_value != USB_ENDPOINT_HALT
1622 || w_length != 0)
1623 goto do_stall;
1624 ep = &udc->ep[w_index & 0xf];
1625 if (ep != ep0) {
1626 if (w_index & USB_DIR_IN)
1627 ep += 16;
1628 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1629 || !ep->desc)
1630 goto do_stall;
1631 use_ep(ep, 0);
1632 omap_writew(udc->clr_halt, UDC_CTRL);
1633 ep->ackwait = 0;
1634 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1635 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1636 ep->ackwait = 1 + ep->double_buf;
1637 }
1638 /* NOTE: assumes the host behaves sanely,
1639 * only clearing real halts. Else we may
1640 * need to kill pending transfers and then
1641 * restart the queue... very messy for DMA!
1642 */
1643 }
1644 VDBG("%s halt cleared by host\n", ep->name);
1645 goto ep0out_status_stage;
1646 case USB_REQ_SET_FEATURE:
1647 /* set endpoint halt */
1648 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1649 goto delegate;
1650 if (w_value != USB_ENDPOINT_HALT
1651 || w_length != 0)
1652 goto do_stall;
1653 ep = &udc->ep[w_index & 0xf];
1654 if (w_index & USB_DIR_IN)
1655 ep += 16;
1656 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1657 || ep == ep0 || !ep->desc)
1658 goto do_stall;
1659 if (use_dma && ep->has_dma) {
1660 /* this has rude side-effects (aborts) and
1661 * can't really work if DMA-IN is active
1662 */
1663 DBG("%s host set_halt, NYET \n", ep->name);
1664 goto do_stall;
1665 }
1666 use_ep(ep, 0);
1667 /* can't halt if fifo isn't empty... */
1668 omap_writew(UDC_CLR_EP, UDC_CTRL);
1669 omap_writew(UDC_SET_HALT, UDC_CTRL);
1670 VDBG("%s halted by host\n", ep->name);
1671 ep0out_status_stage:
1672 status = 0;
1673 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1674 omap_writew(UDC_CLR_EP, UDC_CTRL);
1675 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1676 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1677 udc->ep0_pending = 0;
1678 break;
1679 case USB_REQ_GET_STATUS:
1680 /* USB_ENDPOINT_HALT status? */
1681 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1682 goto intf_status;
1683
1684 /* ep0 never stalls */
1685 if (!(w_index & 0xf))
1686 goto zero_status;
1687
1688 /* only active endpoints count */
1689 ep = &udc->ep[w_index & 0xf];
1690 if (w_index & USB_DIR_IN)
1691 ep += 16;
1692 if (!ep->desc)
1693 goto do_stall;
1694
1695 /* iso never stalls */
1696 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1697 goto zero_status;
1698
1699 /* FIXME don't assume non-halted endpoints!! */
1700 ERR("%s status, can't report\n", ep->ep.name);
1701 goto do_stall;
1702
1703 intf_status:
1704 /* return interface status. if we were pedantic,
1705 * we'd detect non-existent interfaces, and stall.
1706 */
1707 if (u.r.bRequestType
1708 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1709 goto delegate;
1710
1711 zero_status:
1712 /* return two zero bytes */
1713 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1714 omap_writew(0, UDC_DATA);
1715 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1716 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1717 status = 0;
1718 VDBG("GET_STATUS, interface %d\n", w_index);
1719 /* next, status stage */
1720 break;
1721 default:
1722 delegate:
1723 /* activate the ep0out fifo right away */
1724 if (!udc->ep0_in && w_length) {
1725 omap_writew(0, UDC_EP_NUM);
1726 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1727 }
1728
1729 /* gadget drivers see class/vendor specific requests,
1730 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1731 * and more
1732 */
1733 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1734 u.r.bRequestType, u.r.bRequest,
1735 w_value, w_index, w_length);
1736
1737 #undef w_value
1738 #undef w_index
1739 #undef w_length
1740
1741 /* The gadget driver may return an error here,
1742 * causing an immediate protocol stall.
1743 *
1744 * Else it must issue a response, either queueing a
1745 * response buffer for the DATA stage, or halting ep0
1746 * (causing a protocol stall, not a real halt). A
1747 * zero length buffer means no DATA stage.
1748 *
1749 * It's fine to issue that response after the setup()
1750 * call returns, and this IRQ was handled.
1751 */
1752 udc->ep0_setup = 1;
1753 spin_unlock(&udc->lock);
1754 status = udc->driver->setup (&udc->gadget, &u.r);
1755 spin_lock(&udc->lock);
1756 udc->ep0_setup = 0;
1757 }
1758
1759 if (status < 0) {
1760 do_stall:
1761 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1762 u.r.bRequestType, u.r.bRequest, status);
1763 if (udc->ep0_set_config) {
1764 if (udc->ep0_reset_config)
1765 WARNING("error resetting config?\n");
1766 else
1767 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1768 }
1769 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1770 udc->ep0_pending = 0;
1771 }
1772 }
1773 }
1774
1775 /*-------------------------------------------------------------------------*/
1776
1777 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1778
1779 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1780 {
1781 u16 devstat, change;
1782
1783 devstat = omap_readw(UDC_DEVSTAT);
1784 change = devstat ^ udc->devstat;
1785 udc->devstat = devstat;
1786
1787 if (change & (UDC_USB_RESET|UDC_ATT)) {
1788 udc_quiesce(udc);
1789
1790 if (change & UDC_ATT) {
1791 /* driver for any external transceiver will
1792 * have called omap_vbus_session() already
1793 */
1794 if (devstat & UDC_ATT) {
1795 udc->gadget.speed = USB_SPEED_FULL;
1796 VDBG("connect\n");
1797 if (!udc->transceiver)
1798 pullup_enable(udc);
1799 // if (driver->connect) call it
1800 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1801 udc->gadget.speed = USB_SPEED_UNKNOWN;
1802 if (!udc->transceiver)
1803 pullup_disable(udc);
1804 DBG("disconnect, gadget %s\n",
1805 udc->driver->driver.name);
1806 if (udc->driver->disconnect) {
1807 spin_unlock(&udc->lock);
1808 udc->driver->disconnect(&udc->gadget);
1809 spin_lock(&udc->lock);
1810 }
1811 }
1812 change &= ~UDC_ATT;
1813 }
1814
1815 if (change & UDC_USB_RESET) {
1816 if (devstat & UDC_USB_RESET) {
1817 VDBG("RESET=1\n");
1818 } else {
1819 udc->gadget.speed = USB_SPEED_FULL;
1820 INFO("USB reset done, gadget %s\n",
1821 udc->driver->driver.name);
1822 /* ep0 traffic is legal from now on */
1823 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1824 UDC_IRQ_EN);
1825 }
1826 change &= ~UDC_USB_RESET;
1827 }
1828 }
1829 if (change & UDC_SUS) {
1830 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1831 // FIXME tell isp1301 to suspend/resume (?)
1832 if (devstat & UDC_SUS) {
1833 VDBG("suspend\n");
1834 update_otg(udc);
1835 /* HNP could be under way already */
1836 if (udc->gadget.speed == USB_SPEED_FULL
1837 && udc->driver->suspend) {
1838 spin_unlock(&udc->lock);
1839 udc->driver->suspend(&udc->gadget);
1840 spin_lock(&udc->lock);
1841 }
1842 if (udc->transceiver)
1843 otg_set_suspend(udc->transceiver, 1);
1844 } else {
1845 VDBG("resume\n");
1846 if (udc->transceiver)
1847 otg_set_suspend(udc->transceiver, 0);
1848 if (udc->gadget.speed == USB_SPEED_FULL
1849 && udc->driver->resume) {
1850 spin_unlock(&udc->lock);
1851 udc->driver->resume(&udc->gadget);
1852 spin_lock(&udc->lock);
1853 }
1854 }
1855 }
1856 change &= ~UDC_SUS;
1857 }
1858 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1859 update_otg(udc);
1860 change &= ~OTG_FLAGS;
1861 }
1862
1863 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1864 if (change)
1865 VDBG("devstat %03x, ignore change %03x\n",
1866 devstat, change);
1867
1868 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1869 }
1870
1871 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1872 {
1873 struct omap_udc *udc = _udc;
1874 u16 irq_src;
1875 irqreturn_t status = IRQ_NONE;
1876 unsigned long flags;
1877
1878 spin_lock_irqsave(&udc->lock, flags);
1879 irq_src = omap_readw(UDC_IRQ_SRC);
1880
1881 /* Device state change (usb ch9 stuff) */
1882 if (irq_src & UDC_DS_CHG) {
1883 devstate_irq(_udc, irq_src);
1884 status = IRQ_HANDLED;
1885 irq_src &= ~UDC_DS_CHG;
1886 }
1887
1888 /* EP0 control transfers */
1889 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1890 ep0_irq(_udc, irq_src);
1891 status = IRQ_HANDLED;
1892 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1893 }
1894
1895 /* DMA transfer completion */
1896 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1897 dma_irq(_udc, irq_src);
1898 status = IRQ_HANDLED;
1899 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1900 }
1901
1902 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1903 if (irq_src)
1904 DBG("udc_irq, unhandled %03x\n", irq_src);
1905 spin_unlock_irqrestore(&udc->lock, flags);
1906
1907 return status;
1908 }
1909
1910 /* workaround for seemingly-lost IRQs for RX ACKs... */
1911 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1912 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1913
1914 static void pio_out_timer(unsigned long _ep)
1915 {
1916 struct omap_ep *ep = (void *) _ep;
1917 unsigned long flags;
1918 u16 stat_flg;
1919
1920 spin_lock_irqsave(&ep->udc->lock, flags);
1921 if (!list_empty(&ep->queue) && ep->ackwait) {
1922 use_ep(ep, UDC_EP_SEL);
1923 stat_flg = omap_readw(UDC_STAT_FLG);
1924
1925 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1926 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1927 struct omap_req *req;
1928
1929 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1930 req = container_of(ep->queue.next,
1931 struct omap_req, queue);
1932 (void) read_fifo(ep, req);
1933 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1934 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1935 ep->ackwait = 1 + ep->double_buf;
1936 } else
1937 deselect_ep();
1938 }
1939 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1940 spin_unlock_irqrestore(&ep->udc->lock, flags);
1941 }
1942
1943 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1944 {
1945 u16 epn_stat, irq_src;
1946 irqreturn_t status = IRQ_NONE;
1947 struct omap_ep *ep;
1948 int epnum;
1949 struct omap_udc *udc = _dev;
1950 struct omap_req *req;
1951 unsigned long flags;
1952
1953 spin_lock_irqsave(&udc->lock, flags);
1954 epn_stat = omap_readw(UDC_EPN_STAT);
1955 irq_src = omap_readw(UDC_IRQ_SRC);
1956
1957 /* handle OUT first, to avoid some wasteful NAKs */
1958 if (irq_src & UDC_EPN_RX) {
1959 epnum = (epn_stat >> 8) & 0x0f;
1960 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1961 status = IRQ_HANDLED;
1962 ep = &udc->ep[epnum];
1963 ep->irqs++;
1964
1965 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1966 ep->fnf = 0;
1967 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1968 ep->ackwait--;
1969 if (!list_empty(&ep->queue)) {
1970 int stat;
1971 req = container_of(ep->queue.next,
1972 struct omap_req, queue);
1973 stat = read_fifo(ep, req);
1974 if (!ep->double_buf)
1975 ep->fnf = 1;
1976 }
1977 }
1978 /* min 6 clock delay before clearing EP_SEL ... */
1979 epn_stat = omap_readw(UDC_EPN_STAT);
1980 epn_stat = omap_readw(UDC_EPN_STAT);
1981 omap_writew(epnum, UDC_EP_NUM);
1982
1983 /* enabling fifo _after_ clearing ACK, contrary to docs,
1984 * reduces lossage; timer still needed though (sigh).
1985 */
1986 if (ep->fnf) {
1987 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1988 ep->ackwait = 1 + ep->double_buf;
1989 }
1990 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1991 }
1992
1993 /* then IN transfers */
1994 else if (irq_src & UDC_EPN_TX) {
1995 epnum = epn_stat & 0x0f;
1996 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1997 status = IRQ_HANDLED;
1998 ep = &udc->ep[16 + epnum];
1999 ep->irqs++;
2000
2001 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2002 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
2003 ep->ackwait = 0;
2004 if (!list_empty(&ep->queue)) {
2005 req = container_of(ep->queue.next,
2006 struct omap_req, queue);
2007 (void) write_fifo(ep, req);
2008 }
2009 }
2010 /* min 6 clock delay before clearing EP_SEL ... */
2011 epn_stat = omap_readw(UDC_EPN_STAT);
2012 epn_stat = omap_readw(UDC_EPN_STAT);
2013 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
2014 /* then 6 clocks before it'd tx */
2015 }
2016
2017 spin_unlock_irqrestore(&udc->lock, flags);
2018 return status;
2019 }
2020
2021 #ifdef USE_ISO
2022 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2023 {
2024 struct omap_udc *udc = _dev;
2025 struct omap_ep *ep;
2026 int pending = 0;
2027 unsigned long flags;
2028
2029 spin_lock_irqsave(&udc->lock, flags);
2030
2031 /* handle all non-DMA ISO transfers */
2032 list_for_each_entry (ep, &udc->iso, iso) {
2033 u16 stat;
2034 struct omap_req *req;
2035
2036 if (ep->has_dma || list_empty(&ep->queue))
2037 continue;
2038 req = list_entry(ep->queue.next, struct omap_req, queue);
2039
2040 use_ep(ep, UDC_EP_SEL);
2041 stat = omap_readw(UDC_STAT_FLG);
2042
2043 /* NOTE: like the other controller drivers, this isn't
2044 * currently reporting lost or damaged frames.
2045 */
2046 if (ep->bEndpointAddress & USB_DIR_IN) {
2047 if (stat & UDC_MISS_IN)
2048 /* done(ep, req, -EPROTO) */;
2049 else
2050 write_fifo(ep, req);
2051 } else {
2052 int status = 0;
2053
2054 if (stat & UDC_NO_RXPACKET)
2055 status = -EREMOTEIO;
2056 else if (stat & UDC_ISO_ERR)
2057 status = -EILSEQ;
2058 else if (stat & UDC_DATA_FLUSH)
2059 status = -ENOSR;
2060
2061 if (status)
2062 /* done(ep, req, status) */;
2063 else
2064 read_fifo(ep, req);
2065 }
2066 deselect_ep();
2067 /* 6 wait states before next EP */
2068
2069 ep->irqs++;
2070 if (!list_empty(&ep->queue))
2071 pending = 1;
2072 }
2073 if (!pending) {
2074 u16 w;
2075
2076 w = omap_readw(UDC_IRQ_EN);
2077 w &= ~UDC_SOF_IE;
2078 omap_writew(w, UDC_IRQ_EN);
2079 }
2080 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2081
2082 spin_unlock_irqrestore(&udc->lock, flags);
2083 return IRQ_HANDLED;
2084 }
2085 #endif
2086
2087 /*-------------------------------------------------------------------------*/
2088
2089 static inline int machine_without_vbus_sense(void)
2090 {
2091 return (machine_is_omap_innovator()
2092 || machine_is_omap_osk()
2093 || machine_is_omap_apollon()
2094 #ifndef CONFIG_MACH_OMAP_H4_OTG
2095 || machine_is_omap_h4()
2096 #endif
2097 || machine_is_sx1()
2098 || cpu_is_omap7xx() /* No known omap7xx boards with vbus sense */
2099 );
2100 }
2101
2102 static int omap_udc_start(struct usb_gadget_driver *driver,
2103 int (*bind)(struct usb_gadget *))
2104 {
2105 int status = -ENODEV;
2106 struct omap_ep *ep;
2107 unsigned long flags;
2108
2109 /* basic sanity tests */
2110 if (!udc)
2111 return -ENODEV;
2112 if (!driver
2113 // FIXME if otg, check: driver->is_otg
2114 || driver->max_speed < USB_SPEED_FULL
2115 || !bind || !driver->setup)
2116 return -EINVAL;
2117
2118 spin_lock_irqsave(&udc->lock, flags);
2119 if (udc->driver) {
2120 spin_unlock_irqrestore(&udc->lock, flags);
2121 return -EBUSY;
2122 }
2123
2124 /* reset state */
2125 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2126 ep->irqs = 0;
2127 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2128 continue;
2129 use_ep(ep, 0);
2130 omap_writew(UDC_SET_HALT, UDC_CTRL);
2131 }
2132 udc->ep0_pending = 0;
2133 udc->ep[0].irqs = 0;
2134 udc->softconnect = 1;
2135
2136 /* hook up the driver */
2137 driver->driver.bus = NULL;
2138 udc->driver = driver;
2139 udc->gadget.dev.driver = &driver->driver;
2140 spin_unlock_irqrestore(&udc->lock, flags);
2141
2142 if (udc->dc_clk != NULL)
2143 omap_udc_enable_clock(1);
2144
2145 status = bind(&udc->gadget);
2146 if (status) {
2147 DBG("bind to %s --> %d\n", driver->driver.name, status);
2148 udc->gadget.dev.driver = NULL;
2149 udc->driver = NULL;
2150 goto done;
2151 }
2152 DBG("bound to driver %s\n", driver->driver.name);
2153
2154 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2155
2156 /* connect to bus through transceiver */
2157 if (udc->transceiver) {
2158 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2159 if (status < 0) {
2160 ERR("can't bind to transceiver\n");
2161 if (driver->unbind) {
2162 driver->unbind (&udc->gadget);
2163 udc->gadget.dev.driver = NULL;
2164 udc->driver = NULL;
2165 }
2166 goto done;
2167 }
2168 } else {
2169 if (can_pullup(udc))
2170 pullup_enable (udc);
2171 else
2172 pullup_disable (udc);
2173 }
2174
2175 /* boards that don't have VBUS sensing can't autogate 48MHz;
2176 * can't enter deep sleep while a gadget driver is active.
2177 */
2178 if (machine_without_vbus_sense())
2179 omap_vbus_session(&udc->gadget, 1);
2180
2181 done:
2182 if (udc->dc_clk != NULL)
2183 omap_udc_enable_clock(0);
2184 return status;
2185 }
2186
2187 static int omap_udc_stop(struct usb_gadget_driver *driver)
2188 {
2189 unsigned long flags;
2190 int status = -ENODEV;
2191
2192 if (!udc)
2193 return -ENODEV;
2194 if (!driver || driver != udc->driver || !driver->unbind)
2195 return -EINVAL;
2196
2197 if (udc->dc_clk != NULL)
2198 omap_udc_enable_clock(1);
2199
2200 if (machine_without_vbus_sense())
2201 omap_vbus_session(&udc->gadget, 0);
2202
2203 if (udc->transceiver)
2204 (void) otg_set_peripheral(udc->transceiver, NULL);
2205 else
2206 pullup_disable(udc);
2207
2208 spin_lock_irqsave(&udc->lock, flags);
2209 udc_quiesce(udc);
2210 spin_unlock_irqrestore(&udc->lock, flags);
2211
2212 driver->unbind(&udc->gadget);
2213 udc->gadget.dev.driver = NULL;
2214 udc->driver = NULL;
2215
2216 if (udc->dc_clk != NULL)
2217 omap_udc_enable_clock(0);
2218 DBG("unregistered driver '%s'\n", driver->driver.name);
2219 return status;
2220 }
2221
2222 /*-------------------------------------------------------------------------*/
2223
2224 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2225
2226 #include <linux/seq_file.h>
2227
2228 static const char proc_filename[] = "driver/udc";
2229
2230 #define FOURBITS "%s%s%s%s"
2231 #define EIGHTBITS FOURBITS FOURBITS
2232
2233 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2234 {
2235 u16 stat_flg;
2236 struct omap_req *req;
2237 char buf[20];
2238
2239 use_ep(ep, 0);
2240
2241 if (use_dma && ep->has_dma)
2242 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2243 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2244 ep->dma_channel - 1, ep->lch);
2245 else
2246 buf[0] = 0;
2247
2248 stat_flg = omap_readw(UDC_STAT_FLG);
2249 seq_printf(s,
2250 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2251 ep->name, buf,
2252 ep->double_buf ? "dbuf " : "",
2253 ({char *s; switch(ep->ackwait){
2254 case 0: s = ""; break;
2255 case 1: s = "(ackw) "; break;
2256 case 2: s = "(ackw2) "; break;
2257 default: s = "(?) "; break;
2258 } s;}),
2259 ep->irqs, stat_flg,
2260 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2261 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2262 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2263 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2264 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2265 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2266 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2267 (stat_flg & UDC_STALL) ? "STALL " : "",
2268 (stat_flg & UDC_NAK) ? "NAK " : "",
2269 (stat_flg & UDC_ACK) ? "ACK " : "",
2270 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2271 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2272 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2273
2274 if (list_empty (&ep->queue))
2275 seq_printf(s, "\t(queue empty)\n");
2276 else
2277 list_for_each_entry (req, &ep->queue, queue) {
2278 unsigned length = req->req.actual;
2279
2280 if (use_dma && buf[0]) {
2281 length += ((ep->bEndpointAddress & USB_DIR_IN)
2282 ? dma_src_len : dma_dest_len)
2283 (ep, req->req.dma + length);
2284 buf[0] = 0;
2285 }
2286 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2287 &req->req, length,
2288 req->req.length, req->req.buf);
2289 }
2290 }
2291
2292 static char *trx_mode(unsigned m, int enabled)
2293 {
2294 switch (m) {
2295 case 0: return enabled ? "*6wire" : "unused";
2296 case 1: return "4wire";
2297 case 2: return "3wire";
2298 case 3: return "6wire";
2299 default: return "unknown";
2300 }
2301 }
2302
2303 static int proc_otg_show(struct seq_file *s)
2304 {
2305 u32 tmp;
2306 u32 trans = 0;
2307 char *ctrl_name = "(UNKNOWN)";
2308
2309 /* XXX This needs major revision for OMAP2+ */
2310 tmp = omap_readl(OTG_REV);
2311 if (cpu_class_is_omap1()) {
2312 ctrl_name = "tranceiver_ctrl";
2313 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2314 }
2315 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2316 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2317 tmp = omap_readw(OTG_SYSCON_1);
2318 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2319 FOURBITS "\n", tmp,
2320 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2321 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2322 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2323 ? "internal"
2324 : trx_mode(USB0_TRX_MODE(tmp), 1),
2325 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2326 (tmp & HST_IDLE_EN) ? " !host" : "",
2327 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2328 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2329 tmp = omap_readl(OTG_SYSCON_2);
2330 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2331 " b_ase_brst=%d hmc=%d\n", tmp,
2332 (tmp & OTG_EN) ? " otg_en" : "",
2333 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2334 // much more SRP stuff
2335 (tmp & SRP_DATA) ? " srp_data" : "",
2336 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2337 (tmp & OTG_PADEN) ? " otg_paden" : "",
2338 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2339 (tmp & UHOST_EN) ? " uhost_en" : "",
2340 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2341 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2342 B_ASE_BRST(tmp),
2343 OTG_HMC(tmp));
2344 tmp = omap_readl(OTG_CTRL);
2345 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2346 (tmp & OTG_ASESSVLD) ? " asess" : "",
2347 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2348 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2349 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2350 (tmp & OTG_ID) ? " id" : "",
2351 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2352 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2353 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2354 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2355 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2356 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2357 (tmp & OTG_PULLDOWN) ? " down" : "",
2358 (tmp & OTG_PULLUP) ? " up" : "",
2359 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2360 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2361 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2362 (tmp & OTG_PU_ID) ? " pu_id" : ""
2363 );
2364 tmp = omap_readw(OTG_IRQ_EN);
2365 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2366 tmp = omap_readw(OTG_IRQ_SRC);
2367 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2368 tmp = omap_readw(OTG_OUTCTRL);
2369 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2370 tmp = omap_readw(OTG_TEST);
2371 seq_printf(s, "otg_test %04x" "\n", tmp);
2372 return 0;
2373 }
2374
2375 static int proc_udc_show(struct seq_file *s, void *_)
2376 {
2377 u32 tmp;
2378 struct omap_ep *ep;
2379 unsigned long flags;
2380
2381 spin_lock_irqsave(&udc->lock, flags);
2382
2383 seq_printf(s, "%s, version: " DRIVER_VERSION
2384 #ifdef USE_ISO
2385 " (iso)"
2386 #endif
2387 "%s\n",
2388 driver_desc,
2389 use_dma ? " (dma)" : "");
2390
2391 tmp = omap_readw(UDC_REV) & 0xff;
2392 seq_printf(s,
2393 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2394 "hmc %d, transceiver %s\n",
2395 tmp >> 4, tmp & 0xf,
2396 fifo_mode,
2397 udc->driver ? udc->driver->driver.name : "(none)",
2398 HMC,
2399 udc->transceiver
2400 ? udc->transceiver->label
2401 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2402 ? "external" : "(none)"));
2403 if (cpu_class_is_omap1()) {
2404 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2405 omap_readw(ULPD_CLOCK_CTRL),
2406 omap_readw(ULPD_SOFT_REQ),
2407 omap_readw(ULPD_STATUS_REQ));
2408 }
2409
2410 /* OTG controller registers */
2411 if (!cpu_is_omap15xx())
2412 proc_otg_show(s);
2413
2414 tmp = omap_readw(UDC_SYSCON1);
2415 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2416 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2417 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2418 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2419 (tmp & UDC_NAK_EN) ? " nak" : "",
2420 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2421 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2422 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2423 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2424 // syscon2 is write-only
2425
2426 /* UDC controller registers */
2427 if (!(tmp & UDC_PULLUP_EN)) {
2428 seq_printf(s, "(suspended)\n");
2429 spin_unlock_irqrestore(&udc->lock, flags);
2430 return 0;
2431 }
2432
2433 tmp = omap_readw(UDC_DEVSTAT);
2434 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2435 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2436 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2437 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2438 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2439 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2440 (tmp & UDC_SUS) ? " SUS" : "",
2441 (tmp & UDC_CFG) ? " CFG" : "",
2442 (tmp & UDC_ADD) ? " ADD" : "",
2443 (tmp & UDC_DEF) ? " DEF" : "",
2444 (tmp & UDC_ATT) ? " ATT" : "");
2445 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2446 tmp = omap_readw(UDC_IRQ_EN);
2447 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2448 (tmp & UDC_SOF_IE) ? " sof" : "",
2449 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2450 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2451 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2452 (tmp & UDC_EP0_IE) ? " ep0" : "");
2453 tmp = omap_readw(UDC_IRQ_SRC);
2454 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2455 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2456 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2457 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2458 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2459 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2460 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2461 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2462 (tmp & UDC_SETUP) ? " setup" : "",
2463 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2464 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2465 if (use_dma) {
2466 unsigned i;
2467
2468 tmp = omap_readw(UDC_DMA_IRQ_EN);
2469 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2470 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2471 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2472 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2473
2474 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2475 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2476 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2477
2478 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2479 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2480 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2481
2482 tmp = omap_readw(UDC_RXDMA_CFG);
2483 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2484 if (tmp) {
2485 for (i = 0; i < 3; i++) {
2486 if ((tmp & (0x0f << (i * 4))) == 0)
2487 continue;
2488 seq_printf(s, "rxdma[%d] %04x\n", i,
2489 omap_readw(UDC_RXDMA(i + 1)));
2490 }
2491 }
2492 tmp = omap_readw(UDC_TXDMA_CFG);
2493 seq_printf(s, "txdma_cfg %04x\n", tmp);
2494 if (tmp) {
2495 for (i = 0; i < 3; i++) {
2496 if (!(tmp & (0x0f << (i * 4))))
2497 continue;
2498 seq_printf(s, "txdma[%d] %04x\n", i,
2499 omap_readw(UDC_TXDMA(i + 1)));
2500 }
2501 }
2502 }
2503
2504 tmp = omap_readw(UDC_DEVSTAT);
2505 if (tmp & UDC_ATT) {
2506 proc_ep_show(s, &udc->ep[0]);
2507 if (tmp & UDC_ADD) {
2508 list_for_each_entry (ep, &udc->gadget.ep_list,
2509 ep.ep_list) {
2510 if (ep->desc)
2511 proc_ep_show(s, ep);
2512 }
2513 }
2514 }
2515 spin_unlock_irqrestore(&udc->lock, flags);
2516 return 0;
2517 }
2518
2519 static int proc_udc_open(struct inode *inode, struct file *file)
2520 {
2521 return single_open(file, proc_udc_show, NULL);
2522 }
2523
2524 static const struct file_operations proc_ops = {
2525 .owner = THIS_MODULE,
2526 .open = proc_udc_open,
2527 .read = seq_read,
2528 .llseek = seq_lseek,
2529 .release = single_release,
2530 };
2531
2532 static void create_proc_file(void)
2533 {
2534 proc_create(proc_filename, 0, NULL, &proc_ops);
2535 }
2536
2537 static void remove_proc_file(void)
2538 {
2539 remove_proc_entry(proc_filename, NULL);
2540 }
2541
2542 #else
2543
2544 static inline void create_proc_file(void) {}
2545 static inline void remove_proc_file(void) {}
2546
2547 #endif
2548
2549 /*-------------------------------------------------------------------------*/
2550
2551 /* Before this controller can enumerate, we need to pick an endpoint
2552 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2553 * buffer space among the endpoints we'll be operating.
2554 *
2555 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2556 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2557 * capability yet though.
2558 */
2559 static unsigned __init
2560 omap_ep_setup(char *name, u8 addr, u8 type,
2561 unsigned buf, unsigned maxp, int dbuf)
2562 {
2563 struct omap_ep *ep;
2564 u16 epn_rxtx = 0;
2565
2566 /* OUT endpoints first, then IN */
2567 ep = &udc->ep[addr & 0xf];
2568 if (addr & USB_DIR_IN)
2569 ep += 16;
2570
2571 /* in case of ep init table bugs */
2572 BUG_ON(ep->name[0]);
2573
2574 /* chip setup ... bit values are same for IN, OUT */
2575 if (type == USB_ENDPOINT_XFER_ISOC) {
2576 switch (maxp) {
2577 case 8: epn_rxtx = 0 << 12; break;
2578 case 16: epn_rxtx = 1 << 12; break;
2579 case 32: epn_rxtx = 2 << 12; break;
2580 case 64: epn_rxtx = 3 << 12; break;
2581 case 128: epn_rxtx = 4 << 12; break;
2582 case 256: epn_rxtx = 5 << 12; break;
2583 case 512: epn_rxtx = 6 << 12; break;
2584 default: BUG();
2585 }
2586 epn_rxtx |= UDC_EPN_RX_ISO;
2587 dbuf = 1;
2588 } else {
2589 /* double-buffering "not supported" on 15xx,
2590 * and ignored for PIO-IN on newer chips
2591 * (for more reliable behavior)
2592 */
2593 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2594 dbuf = 0;
2595
2596 switch (maxp) {
2597 case 8: epn_rxtx = 0 << 12; break;
2598 case 16: epn_rxtx = 1 << 12; break;
2599 case 32: epn_rxtx = 2 << 12; break;
2600 case 64: epn_rxtx = 3 << 12; break;
2601 default: BUG();
2602 }
2603 if (dbuf && addr)
2604 epn_rxtx |= UDC_EPN_RX_DB;
2605 init_timer(&ep->timer);
2606 ep->timer.function = pio_out_timer;
2607 ep->timer.data = (unsigned long) ep;
2608 }
2609 if (addr)
2610 epn_rxtx |= UDC_EPN_RX_VALID;
2611 BUG_ON(buf & 0x07);
2612 epn_rxtx |= buf >> 3;
2613
2614 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2615 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2616
2617 if (addr & USB_DIR_IN)
2618 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2619 else
2620 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2621
2622 /* next endpoint's buffer starts after this one's */
2623 buf += maxp;
2624 if (dbuf)
2625 buf += maxp;
2626 BUG_ON(buf > 2048);
2627
2628 /* set up driver data structures */
2629 BUG_ON(strlen(name) >= sizeof ep->name);
2630 strlcpy(ep->name, name, sizeof ep->name);
2631 INIT_LIST_HEAD(&ep->queue);
2632 INIT_LIST_HEAD(&ep->iso);
2633 ep->bEndpointAddress = addr;
2634 ep->bmAttributes = type;
2635 ep->double_buf = dbuf;
2636 ep->udc = udc;
2637
2638 ep->ep.name = ep->name;
2639 ep->ep.ops = &omap_ep_ops;
2640 ep->ep.maxpacket = ep->maxpacket = maxp;
2641 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2642
2643 return buf;
2644 }
2645
2646 static void omap_udc_release(struct device *dev)
2647 {
2648 complete(udc->done);
2649 kfree (udc);
2650 udc = NULL;
2651 }
2652
2653 static int __init
2654 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2655 {
2656 unsigned tmp, buf;
2657
2658 /* abolish any previous hardware state */
2659 omap_writew(0, UDC_SYSCON1);
2660 omap_writew(0, UDC_IRQ_EN);
2661 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2662 omap_writew(0, UDC_DMA_IRQ_EN);
2663 omap_writew(0, UDC_RXDMA_CFG);
2664 omap_writew(0, UDC_TXDMA_CFG);
2665
2666 /* UDC_PULLUP_EN gates the chip clock */
2667 // OTG_SYSCON_1 |= DEV_IDLE_EN;
2668
2669 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2670 if (!udc)
2671 return -ENOMEM;
2672
2673 spin_lock_init (&udc->lock);
2674
2675 udc->gadget.ops = &omap_gadget_ops;
2676 udc->gadget.ep0 = &udc->ep[0].ep;
2677 INIT_LIST_HEAD(&udc->gadget.ep_list);
2678 INIT_LIST_HEAD(&udc->iso);
2679 udc->gadget.speed = USB_SPEED_UNKNOWN;
2680 udc->gadget.max_speed = USB_SPEED_FULL;
2681 udc->gadget.name = driver_name;
2682
2683 device_initialize(&udc->gadget.dev);
2684 dev_set_name(&udc->gadget.dev, "gadget");
2685 udc->gadget.dev.release = omap_udc_release;
2686 udc->gadget.dev.parent = &odev->dev;
2687 if (use_dma)
2688 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2689
2690 udc->transceiver = xceiv;
2691
2692 /* ep0 is special; put it right after the SETUP buffer */
2693 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2694 8 /* after SETUP */, 64 /* maxpacket */, 0);
2695 list_del_init(&udc->ep[0].ep.ep_list);
2696
2697 /* initially disable all non-ep0 endpoints */
2698 for (tmp = 1; tmp < 15; tmp++) {
2699 omap_writew(0, UDC_EP_RX(tmp));
2700 omap_writew(0, UDC_EP_TX(tmp));
2701 }
2702
2703 #define OMAP_BULK_EP(name,addr) \
2704 buf = omap_ep_setup(name "-bulk", addr, \
2705 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2706 #define OMAP_INT_EP(name,addr, maxp) \
2707 buf = omap_ep_setup(name "-int", addr, \
2708 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2709 #define OMAP_ISO_EP(name,addr, maxp) \
2710 buf = omap_ep_setup(name "-iso", addr, \
2711 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2712
2713 switch (fifo_mode) {
2714 case 0:
2715 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2716 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2717 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2718 break;
2719 case 1:
2720 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2721 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2722 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2723
2724 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2725 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2726 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2727
2728 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2729 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2730 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2731
2732 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2733 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2734 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2735
2736 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2737 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2738 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2739 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2740
2741 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2742 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2743 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2744 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2745
2746 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2747 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2748
2749 break;
2750
2751 #ifdef USE_ISO
2752 case 2: /* mixed iso/bulk */
2753 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2754 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2755 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2756 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2757
2758 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2759
2760 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2761 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2762 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2763 break;
2764 case 3: /* mixed bulk/iso */
2765 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2766 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2767 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2768
2769 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2770 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2771 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2772
2773 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2774 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2775 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2776 break;
2777 #endif
2778
2779 /* add more modes as needed */
2780
2781 default:
2782 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2783 return -ENODEV;
2784 }
2785 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2786 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2787 return 0;
2788 }
2789
2790 static int __init omap_udc_probe(struct platform_device *pdev)
2791 {
2792 int status = -ENODEV;
2793 int hmc;
2794 struct otg_transceiver *xceiv = NULL;
2795 const char *type = NULL;
2796 struct omap_usb_config *config = pdev->dev.platform_data;
2797 struct clk *dc_clk;
2798 struct clk *hhc_clk;
2799
2800 /* NOTE: "knows" the order of the resources! */
2801 if (!request_mem_region(pdev->resource[0].start,
2802 pdev->resource[0].end - pdev->resource[0].start + 1,
2803 driver_name)) {
2804 DBG("request_mem_region failed\n");
2805 return -EBUSY;
2806 }
2807
2808 if (cpu_is_omap16xx()) {
2809 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2810 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2811 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2812 /* can't use omap_udc_enable_clock yet */
2813 clk_enable(dc_clk);
2814 clk_enable(hhc_clk);
2815 udelay(100);
2816 }
2817
2818 if (cpu_is_omap24xx()) {
2819 dc_clk = clk_get(&pdev->dev, "usb_fck");
2820 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2821 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2822 /* can't use omap_udc_enable_clock yet */
2823 clk_enable(dc_clk);
2824 clk_enable(hhc_clk);
2825 udelay(100);
2826 }
2827
2828 if (cpu_is_omap7xx()) {
2829 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2830 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2831 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2832 /* can't use omap_udc_enable_clock yet */
2833 clk_enable(dc_clk);
2834 clk_enable(hhc_clk);
2835 udelay(100);
2836 }
2837
2838 INFO("OMAP UDC rev %d.%d%s\n",
2839 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2840 config->otg ? ", Mini-AB" : "");
2841
2842 /* use the mode given to us by board init code */
2843 if (cpu_is_omap15xx()) {
2844 hmc = HMC_1510;
2845 type = "(unknown)";
2846
2847 if (machine_without_vbus_sense()) {
2848 /* just set up software VBUS detect, and then
2849 * later rig it so we always report VBUS.
2850 * FIXME without really sensing VBUS, we can't
2851 * know when to turn PULLUP_EN on/off; and that
2852 * means we always "need" the 48MHz clock.
2853 */
2854 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2855 tmp &= ~VBUS_CTRL_1510;
2856 omap_writel(tmp, FUNC_MUX_CTRL_0);
2857 tmp |= VBUS_MODE_1510;
2858 tmp &= ~VBUS_CTRL_1510;
2859 omap_writel(tmp, FUNC_MUX_CTRL_0);
2860 }
2861 } else {
2862 /* The transceiver may package some GPIO logic or handle
2863 * loopback and/or transceiverless setup; if we find one,
2864 * use it. Except for OTG, we don't _need_ to talk to one;
2865 * but not having one probably means no VBUS detection.
2866 */
2867 xceiv = otg_get_transceiver();
2868 if (xceiv)
2869 type = xceiv->label;
2870 else if (config->otg) {
2871 DBG("OTG requires external transceiver!\n");
2872 goto cleanup0;
2873 }
2874
2875 hmc = HMC_1610;
2876
2877 if (cpu_is_omap24xx()) {
2878 /* this could be transceiverless in one of the
2879 * "we don't need to know" modes.
2880 */
2881 type = "external";
2882 goto known;
2883 }
2884
2885 switch (hmc) {
2886 case 0: /* POWERUP DEFAULT == 0 */
2887 case 4:
2888 case 12:
2889 case 20:
2890 if (!cpu_is_omap1710()) {
2891 type = "integrated";
2892 break;
2893 }
2894 /* FALL THROUGH */
2895 case 3:
2896 case 11:
2897 case 16:
2898 case 19:
2899 case 25:
2900 if (!xceiv) {
2901 DBG("external transceiver not registered!\n");
2902 type = "unknown";
2903 }
2904 break;
2905 case 21: /* internal loopback */
2906 type = "loopback";
2907 break;
2908 case 14: /* transceiverless */
2909 if (cpu_is_omap1710())
2910 goto bad_on_1710;
2911 /* FALL THROUGH */
2912 case 13:
2913 case 15:
2914 type = "no";
2915 break;
2916
2917 default:
2918 bad_on_1710:
2919 ERR("unrecognized UDC HMC mode %d\n", hmc);
2920 goto cleanup0;
2921 }
2922 }
2923 known:
2924 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2925
2926 /* a "gadget" abstracts/virtualizes the controller */
2927 status = omap_udc_setup(pdev, xceiv);
2928 if (status) {
2929 goto cleanup0;
2930 }
2931 xceiv = NULL;
2932 // "udc" is now valid
2933 pullup_disable(udc);
2934 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2935 udc->gadget.is_otg = (config->otg != 0);
2936 #endif
2937
2938 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2939 if (omap_readw(UDC_REV) >= 0x61)
2940 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2941 else
2942 udc->clr_halt = UDC_RESET_EP;
2943
2944 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2945 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2946 IRQF_SAMPLE_RANDOM, driver_name, udc);
2947 if (status != 0) {
2948 ERR("can't get irq %d, err %d\n",
2949 (int) pdev->resource[1].start, status);
2950 goto cleanup1;
2951 }
2952
2953 /* USB "non-iso" IRQ (PIO for all but ep0) */
2954 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2955 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2956 if (status != 0) {
2957 ERR("can't get irq %d, err %d\n",
2958 (int) pdev->resource[2].start, status);
2959 goto cleanup2;
2960 }
2961 #ifdef USE_ISO
2962 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2963 0, "omap_udc iso", udc);
2964 if (status != 0) {
2965 ERR("can't get irq %d, err %d\n",
2966 (int) pdev->resource[3].start, status);
2967 goto cleanup3;
2968 }
2969 #endif
2970 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2971 udc->dc_clk = dc_clk;
2972 udc->hhc_clk = hhc_clk;
2973 clk_disable(hhc_clk);
2974 clk_disable(dc_clk);
2975 }
2976
2977 if (cpu_is_omap24xx()) {
2978 udc->dc_clk = dc_clk;
2979 udc->hhc_clk = hhc_clk;
2980 /* FIXME OMAP2 don't release hhc & dc clock */
2981 #if 0
2982 clk_disable(hhc_clk);
2983 clk_disable(dc_clk);
2984 #endif
2985 }
2986
2987 create_proc_file();
2988 status = device_add(&udc->gadget.dev);
2989 if (status)
2990 goto cleanup4;
2991
2992 status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2993 if (!status)
2994 return status;
2995 /* If fail, fall through */
2996 cleanup4:
2997 remove_proc_file();
2998
2999 #ifdef USE_ISO
3000 cleanup3:
3001 free_irq(pdev->resource[2].start, udc);
3002 #endif
3003
3004 cleanup2:
3005 free_irq(pdev->resource[1].start, udc);
3006
3007 cleanup1:
3008 kfree (udc);
3009 udc = NULL;
3010
3011 cleanup0:
3012 if (xceiv)
3013 otg_put_transceiver(xceiv);
3014
3015 if (cpu_is_omap16xx() || cpu_is_omap24xx() || cpu_is_omap7xx()) {
3016 clk_disable(hhc_clk);
3017 clk_disable(dc_clk);
3018 clk_put(hhc_clk);
3019 clk_put(dc_clk);
3020 }
3021
3022 release_mem_region(pdev->resource[0].start,
3023 pdev->resource[0].end - pdev->resource[0].start + 1);
3024
3025 return status;
3026 }
3027
3028 static int __exit omap_udc_remove(struct platform_device *pdev)
3029 {
3030 DECLARE_COMPLETION_ONSTACK(done);
3031
3032 if (!udc)
3033 return -ENODEV;
3034
3035 usb_del_gadget_udc(&udc->gadget);
3036 if (udc->driver)
3037 return -EBUSY;
3038
3039 udc->done = &done;
3040
3041 pullup_disable(udc);
3042 if (udc->transceiver) {
3043 otg_put_transceiver(udc->transceiver);
3044 udc->transceiver = NULL;
3045 }
3046 omap_writew(0, UDC_SYSCON1);
3047
3048 remove_proc_file();
3049
3050 #ifdef USE_ISO
3051 free_irq(pdev->resource[3].start, udc);
3052 #endif
3053 free_irq(pdev->resource[2].start, udc);
3054 free_irq(pdev->resource[1].start, udc);
3055
3056 if (udc->dc_clk) {
3057 if (udc->clk_requested)
3058 omap_udc_enable_clock(0);
3059 clk_put(udc->hhc_clk);
3060 clk_put(udc->dc_clk);
3061 }
3062
3063 release_mem_region(pdev->resource[0].start,
3064 pdev->resource[0].end - pdev->resource[0].start + 1);
3065
3066 device_unregister(&udc->gadget.dev);
3067 wait_for_completion(&done);
3068
3069 return 0;
3070 }
3071
3072 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3073 * system is forced into deep sleep
3074 *
3075 * REVISIT we should probably reject suspend requests when there's a host
3076 * session active, rather than disconnecting, at least on boards that can
3077 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3078 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3079 * may involve talking to an external transceiver (e.g. isp1301).
3080 */
3081
3082 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3083 {
3084 u32 devstat;
3085
3086 devstat = omap_readw(UDC_DEVSTAT);
3087
3088 /* we're requesting 48 MHz clock if the pullup is enabled
3089 * (== we're attached to the host) and we're not suspended,
3090 * which would prevent entry to deep sleep...
3091 */
3092 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3093 WARNING("session active; suspend requires disconnect\n");
3094 omap_pullup(&udc->gadget, 0);
3095 }
3096
3097 return 0;
3098 }
3099
3100 static int omap_udc_resume(struct platform_device *dev)
3101 {
3102 DBG("resume + wakeup/SRP\n");
3103 omap_pullup(&udc->gadget, 1);
3104
3105 /* maybe the host would enumerate us if we nudged it */
3106 msleep(100);
3107 return omap_wakeup(&udc->gadget);
3108 }
3109
3110 /*-------------------------------------------------------------------------*/
3111
3112 static struct platform_driver udc_driver = {
3113 .remove = __exit_p(omap_udc_remove),
3114 .suspend = omap_udc_suspend,
3115 .resume = omap_udc_resume,
3116 .driver = {
3117 .owner = THIS_MODULE,
3118 .name = (char *) driver_name,
3119 },
3120 };
3121
3122 static int __init udc_init(void)
3123 {
3124 /* Disable DMA for omap7xx -- it doesn't work right. */
3125 if (cpu_is_omap7xx())
3126 use_dma = 0;
3127
3128 INFO("%s, version: " DRIVER_VERSION
3129 #ifdef USE_ISO
3130 " (iso)"
3131 #endif
3132 "%s\n", driver_desc,
3133 use_dma ? " (dma)" : "");
3134 return platform_driver_probe(&udc_driver, omap_udc_probe);
3135 }
3136 module_init(udc_init);
3137
3138 static void __exit udc_exit(void)
3139 {
3140 platform_driver_unregister(&udc_driver);
3141 }
3142 module_exit(udc_exit);
3143
3144 MODULE_DESCRIPTION(DRIVER_DESC);
3145 MODULE_LICENSE("GPL");
3146 MODULE_ALIAS("platform:omap_udc");