tty/serial: atmel_serial: whitespace and braces modifications
[zen-stable.git] / drivers / staging / ath6kl / miscdrv / miscdrv.h
blob41be5670db42d2709fbe7388ac1837e23051d328
1 //------------------------------------------------------------------------------
2 // <copyright file="miscdrv.h" company="Atheros">
3 // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
4 //
5 //
6 // Permission to use, copy, modify, and/or distribute this software for any
7 // purpose with or without fee is hereby granted, provided that the above
8 // copyright notice and this permission notice appear in all copies.
9 //
10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 //------------------------------------------------------------------------------
20 //==============================================================================
21 // Author(s): ="Atheros"
22 //==============================================================================
23 #ifndef _MISCDRV_H
24 #define _MISCDRV_H
27 #define HOST_INTEREST_ITEM_ADDRESS(target, item) \
28 AR6002_HOST_INTEREST_ITEM_ADDRESS(item)
30 u32 ar6kRev2Array[][128] = {
31 {0xFFFF, 0xFFFF}, // No Patches
34 #define CFG_REV2_ITEMS 0 // no patches so far
35 #define AR6K_RESET_ADDR 0x4000
36 #define AR6K_RESET_VAL 0x100
38 #define EEPROM_SZ 768
39 #define EEPROM_WAIT_LIMIT 4
41 #endif