drivers/edac/i3200_edac.c

   1 /*
   2  * Intel 3200/3210 Memory Controller kernel module
   3  * Copyright (C) 2008-2009 Akamai Technologies, Inc.
   4  * Portions by Hitoshi Mitake <h.mitake@gmail.com>.
   5  *
   6  * This file may be distributed under the terms of the
   7  * GNU General Public License.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/init.h>
  12 #include <linux/pci.h>
  13 #include <linux/pci_ids.h>
  14 #include <linux/edac.h>
  15 #include <linux/io.h>
  16 #include "edac_core.h"
  17
  18 #define I3200_REVISION        "1.1"
  19
  20 #define EDAC_MOD_STR        "i3200_edac"
  21
  22 #define PCI_DEVICE_ID_INTEL_3200_HB    0x29f0
  23
  24 #define I3200_RANKS             8
  25 #define I3200_RANKS_PER_CHANNEL 4
  26 #define I3200_CHANNELS          2
  27
  28 /* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
  29
  30 #define I3200_MCHBAR_LOW        0x48    /* MCH Memory Mapped Register BAR */
  31 #define I3200_MCHBAR_HIGH       0x4c
  32 #define I3200_MCHBAR_MASK       0xfffffc000ULL  /* bits 35:14 */
  33 #define I3200_MMR_WINDOW_SIZE   16384
  34
  35 #define I3200_TOM               0xa0    /* Top of Memory (16b)
  36                  *
  37                  * 15:10 reserved
  38                  *  9:0  total populated physical memory
  39                  */
  40 #define I3200_TOM_MASK          0x3ff   /* bits 9:0 */
  41 #define I3200_TOM_SHIFT         26      /* 64MiB grain */
  42
  43 #define I3200_ERRSTS            0xc8    /* Error Status Register (16b)
  44                  *
  45                  * 15    reserved
  46                  * 14    Isochronous TBWRR Run Behind FIFO Full
  47                  *       (ITCV)
  48                  * 13    Isochronous TBWRR Run Behind FIFO Put
  49                  *       (ITSTV)
  50                  * 12    reserved
  51                  * 11    MCH Thermal Sensor Event
  52                  *       for SMI/SCI/SERR (GTSE)
  53                  * 10    reserved
  54                  *  9    LOCK to non-DRAM Memory Flag (LCKF)
  55                  *  8    reserved
  56                  *  7    DRAM Throttle Flag (DTF)
  57                  *  6:2  reserved
  58                  *  1    Multi-bit DRAM ECC Error Flag (DMERR)
  59                  *  0    Single-bit DRAM ECC Error Flag (DSERR)
  60                  */
  61 #define I3200_ERRSTS_UE         0x0002
  62 #define I3200_ERRSTS_CE         0x0001
  63 #define I3200_ERRSTS_BITS       (I3200_ERRSTS_UE | I3200_ERRSTS_CE)
  64
  65
  66 /* Intel  MMIO register space - device 0 function 0 - MMR space */
  67
  68 #define I3200_C0DRB     0x200   /* Channel 0 DRAM Rank Boundary (16b x 4)
  69                  *
  70                  * 15:10 reserved
  71                  *  9:0  Channel 0 DRAM Rank Boundary Address
  72                  */
  73 #define I3200_C1DRB     0x600   /* Channel 1 DRAM Rank Boundary (16b x 4) */
  74 #define I3200_DRB_MASK  0x3ff   /* bits 9:0 */
  75 #define I3200_DRB_SHIFT 26      /* 64MiB grain */
  76
  77 #define I3200_C0ECCERRLOG       0x280   /* Channel 0 ECC Error Log (64b)
  78                  *
  79                  * 63:48 Error Column Address (ERRCOL)
  80                  * 47:32 Error Row Address (ERRROW)
  81                  * 31:29 Error Bank Address (ERRBANK)
  82                  * 28:27 Error Rank Address (ERRRANK)
  83                  * 26:24 reserved
  84                  * 23:16 Error Syndrome (ERRSYND)
  85                  * 15: 2 reserved
  86                  *    1  Multiple Bit Error Status (MERRSTS)
  87                  *    0  Correctable Error Status (CERRSTS)
  88                  */
  89 #define I3200_C1ECCERRLOG               0x680   /* Chan 1 ECC Error Log (64b) */
  90 #define I3200_ECCERRLOG_CE              0x1
  91 #define I3200_ECCERRLOG_UE              0x2
  92 #define I3200_ECCERRLOG_RANK_BITS       0x18000000
  93 #define I3200_ECCERRLOG_RANK_SHIFT      27
  94 #define I3200_ECCERRLOG_SYNDROME_BITS   0xff0000
  95 #define I3200_ECCERRLOG_SYNDROME_SHIFT  16
  96 #define I3200_CAPID0                    0xe0    /* P.95 of spec for details */
  97
  98 struct i3200_priv {
  99         void __iomem *window;
 100 };
 101
 102 static int nr_channels;
 103
 104 #ifndef readq
 105 static inline __u64 readq(const volatile void __iomem *addr)
 106 {
 107         const volatile u32 __iomem *p = addr;
 108         u32 low, high;
 109
 110         low = readl(p);
 111         high = readl(p + 1);
 112
 113         return low + ((u64)high << 32);
 114 }
 115 #endif
 116
 117 static int how_many_channels(struct pci_dev *pdev)
 118 {
 119         unsigned char capid0_8b; /* 8th byte of CAPID0 */
 120
 121         pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
 122         if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
 123                 debugf0("In single channel mode.\n");
 124                 return 1;
 125         } else {
 126                 debugf0("In dual channel mode.\n");
 127                 return 2;
 128         }
 129 }
 130
 131 static unsigned long eccerrlog_syndrome(u64 log)
 132 {
 133         return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
 134                 I3200_ECCERRLOG_SYNDROME_SHIFT;
 135 }
 136
 137 static int eccerrlog_row(int channel, u64 log)
 138 {
 139         u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
 140                 I3200_ECCERRLOG_RANK_SHIFT);
 141         return rank | (channel * I3200_RANKS_PER_CHANNEL);
 142 }
 143
 144 enum i3200_chips {
 145         I3200 = 0,
 146 };
 147
 148 struct i3200_dev_info {
 149         const char *ctl_name;
 150 };
 151
 152 struct i3200_error_info {
 153         u16 errsts;
 154         u16 errsts2;
 155         u64 eccerrlog[I3200_CHANNELS];
 156 };
 157
 158 static const struct i3200_dev_info i3200_devs[] = {
 159         [I3200] = {
 160                 .ctl_name = "i3200"
 161         },
 162 };
 163
 164 static struct pci_dev *mci_pdev;
 165 static int i3200_registered = 1;
 166
 167
 168 static void i3200_clear_error_info(struct mem_ctl_info *mci)
 169 {
 170         struct pci_dev *pdev;
 171
 172         pdev = to_pci_dev(mci->dev);
 173
 174         /*
 175          * Clear any error bits.
 176          * (Yes, we really clear bits by writing 1 to them.)
 177          */
 178         pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
 179                 I3200_ERRSTS_BITS);
 180 }
 181
 182 static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
 183                 struct i3200_error_info *info)
 184 {
 185         struct pci_dev *pdev;
 186         struct i3200_priv *priv = mci->pvt_info;
 187         void __iomem *window = priv->window;
 188
 189         pdev = to_pci_dev(mci->dev);
 190
 191         /*
 192          * This is a mess because there is no atomic way to read all the
 193          * registers at once and the registers can transition from CE being
 194          * overwritten by UE.
 195          */
 196         pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
 197         if (!(info->errsts & I3200_ERRSTS_BITS))
 198                 return;
 199
 200         info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
 201         if (nr_channels == 2)
 202                 info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
 203
 204         pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);
 205
 206         /*
 207          * If the error is the same for both reads then the first set
 208          * of reads is valid.  If there is a change then there is a CE
 209          * with no info and the second set of reads is valid and
 210          * should be UE info.
 211          */
 212         if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
 213                 info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
 214                 if (nr_channels == 2)
 215                         info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
 216         }
 217
 218         i3200_clear_error_info(mci);
 219 }
 220
 221 static void i3200_process_error_info(struct mem_ctl_info *mci,
 222                 struct i3200_error_info *info)
 223 {
 224         int channel;
 225         u64 log;
 226
 227         if (!(info->errsts & I3200_ERRSTS_BITS))
 228                 return;
 229
 230         if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
 231                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
 232                 info->errsts = info->errsts2;
 233         }
 234
 235         for (channel = 0; channel < nr_channels; channel++) {
 236                 log = info->eccerrlog[channel];
 237                 if (log & I3200_ECCERRLOG_UE) {
 238                         edac_mc_handle_ue(mci, 0, 0,
 239                                 eccerrlog_row(channel, log),
 240                                 "i3200 UE");
 241                 } else if (log & I3200_ECCERRLOG_CE) {
 242                         edac_mc_handle_ce(mci, 0, 0,
 243                                 eccerrlog_syndrome(log),
 244                                 eccerrlog_row(channel, log), 0,
 245                                 "i3200 CE");
 246                 }
 247         }
 248 }
 249
 250 static void i3200_check(struct mem_ctl_info *mci)
 251 {
 252         struct i3200_error_info info;
 253
 254         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 255         i3200_get_and_clear_error_info(mci, &info);
 256         i3200_process_error_info(mci, &info);
 257 }
 258
 259
 260 void __iomem *i3200_map_mchbar(struct pci_dev *pdev)
 261 {
 262         union {
 263                 u64 mchbar;
 264                 struct {
 265                         u32 mchbar_low;
 266                         u32 mchbar_high;
 267                 };
 268         } u;
 269         void __iomem *window;
 270
 271         pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
 272         pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
 273         u.mchbar &= I3200_MCHBAR_MASK;
 274
 275         if (u.mchbar != (resource_size_t)u.mchbar) {
 276                 printk(KERN_ERR
 277                         "i3200: mmio space beyond accessible range (0x%llx)\n",
 278                         (unsigned long long)u.mchbar);
 279                 return NULL;
 280         }
 281
 282         window = ioremap_nocache(u.mchbar, I3200_MMR_WINDOW_SIZE);
 283         if (!window)
 284                 printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
 285                         (unsigned long long)u.mchbar);
 286
 287         return window;
 288 }
 289
 290
 291 static void i3200_get_drbs(void __iomem *window,
 292         u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
 293 {
 294         int i;
 295
 296         for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
 297                 drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
 298                 drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
 299         }
 300 }
 301
 302 static bool i3200_is_stacked(struct pci_dev *pdev,
 303         u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
 304 {
 305         u16 tom;
 306
 307         pci_read_config_word(pdev, I3200_TOM, &tom);
 308         tom &= I3200_TOM_MASK;
 309
 310         return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
 311 }
 312
 313 static unsigned long drb_to_nr_pages(
 314         u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
 315         int channel, int rank)
 316 {
 317         int n;
 318
 319         n = drbs[channel][rank];
 320         if (rank > 0)
 321                 n -= drbs[channel][rank - 1];
 322         if (stacked && (channel == 1) &&
 323         drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
 324                 n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];
 325
 326         n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
 327         return n;
 328 }
 329
 330 static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
 331 {
 332         int rc;
 333         int i;
 334         struct mem_ctl_info *mci = NULL;
 335         unsigned long last_page;
 336         u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
 337         bool stacked;
 338         void __iomem *window;
 339         struct i3200_priv *priv;
 340
 341         debugf0("MC: %s()\n", __func__);
 342
 343         window = i3200_map_mchbar(pdev);
 344         if (!window)
 345                 return -ENODEV;
 346
 347         i3200_get_drbs(window, drbs);
 348         nr_channels = how_many_channels(pdev);
 349
 350         mci = edac_mc_alloc(sizeof(struct i3200_priv), I3200_RANKS,
 351                 nr_channels, 0);
 352         if (!mci)
 353                 return -ENOMEM;
 354
 355         debugf3("MC: %s(): init mci\n", __func__);
 356
 357         mci->dev = &pdev->dev;
 358         mci->mtype_cap = MEM_FLAG_DDR2;
 359
 360         mci->edac_ctl_cap = EDAC_FLAG_SECDED;
 361         mci->edac_cap = EDAC_FLAG_SECDED;
 362
 363         mci->mod_name = EDAC_MOD_STR;
 364         mci->mod_ver = I3200_REVISION;
 365         mci->ctl_name = i3200_devs[dev_idx].ctl_name;
 366         mci->dev_name = pci_name(pdev);
 367         mci->edac_check = i3200_check;
 368         mci->ctl_page_to_phys = NULL;
 369         priv = mci->pvt_info;
 370         priv->window = window;
 371
 372         stacked = i3200_is_stacked(pdev, drbs);
 373
 374         /*
 375          * The dram rank boundary (DRB) reg values are boundary addresses
 376          * for each DRAM rank with a granularity of 64MB.  DRB regs are
 377          * cumulative; the last one will contain the total memory
 378          * contained in all ranks.
 379          */
 380         last_page = -1UL;
 381         for (i = 0; i < mci->nr_csrows; i++) {
 382                 unsigned long nr_pages;
 383                 struct csrow_info *csrow = &mci->csrows[i];
 384
 385                 nr_pages = drb_to_nr_pages(drbs, stacked,
 386                         i / I3200_RANKS_PER_CHANNEL,
 387                         i % I3200_RANKS_PER_CHANNEL);
 388
 389                 if (nr_pages == 0) {
 390                         csrow->mtype = MEM_EMPTY;
 391                         continue;
 392                 }
 393
 394                 csrow->first_page = last_page + 1;
 395                 last_page += nr_pages;
 396                 csrow->last_page = last_page;
 397                 csrow->nr_pages = nr_pages;
 398
 399                 csrow->grain = nr_pages << PAGE_SHIFT;
 400                 csrow->mtype = MEM_DDR2;
 401                 csrow->dtype = DEV_UNKNOWN;
 402                 csrow->edac_mode = EDAC_UNKNOWN;
 403         }
 404
 405         i3200_clear_error_info(mci);
 406
 407         rc = -ENODEV;
 408         if (edac_mc_add_mc(mci)) {
 409                 debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
 410                 goto fail;
 411         }
 412
 413         /* get this far and it's successful */
 414         debugf3("MC: %s(): success\n", __func__);
 415         return 0;
 416
 417 fail:
 418         iounmap(window);
 419         if (mci)
 420                 edac_mc_free(mci);
 421
 422         return rc;
 423 }
 424
 425 static int __devinit i3200_init_one(struct pci_dev *pdev,
 426                 const struct pci_device_id *ent)
 427 {
 428         int rc;
 429
 430         debugf0("MC: %s()\n", __func__);
 431
 432         if (pci_enable_device(pdev) < 0)
 433                 return -EIO;
 434
 435         rc = i3200_probe1(pdev, ent->driver_data);
 436         if (!mci_pdev)
 437                 mci_pdev = pci_dev_get(pdev);
 438
 439         return rc;
 440 }
 441
 442 static void __devexit i3200_remove_one(struct pci_dev *pdev)
 443 {
 444         struct mem_ctl_info *mci;
 445         struct i3200_priv *priv;
 446
 447         debugf0("%s()\n", __func__);
 448
 449         mci = edac_mc_del_mc(&pdev->dev);
 450         if (!mci)
 451                 return;
 452
 453         priv = mci->pvt_info;
 454         iounmap(priv->window);
 455
 456         edac_mc_free(mci);
 457 }
 458
 459 static const struct pci_device_id i3200_pci_tbl[] __devinitdata = {
 460         {
 461                 PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 462                 I3200},
 463         {
 464                 0,
 465         }            /* 0 terminated list. */
 466 };
 467
 468 MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);
 469
 470 static struct pci_driver i3200_driver = {
 471         .name = EDAC_MOD_STR,
 472         .probe = i3200_init_one,
 473         .remove = __devexit_p(i3200_remove_one),
 474         .id_table = i3200_pci_tbl,
 475 };
 476
 477 static int __init i3200_init(void)
 478 {
 479         int pci_rc;
 480
 481         debugf3("MC: %s()\n", __func__);
 482
 483         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
 484         opstate_init();
 485
 486         pci_rc = pci_register_driver(&i3200_driver);
 487         if (pci_rc < 0)
 488                 goto fail0;
 489
 490         if (!mci_pdev) {
 491                 i3200_registered = 0;
 492                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 493                                 PCI_DEVICE_ID_INTEL_3200_HB, NULL);
 494                 if (!mci_pdev) {
 495                         debugf0("i3200 pci_get_device fail\n");
 496                         pci_rc = -ENODEV;
 497                         goto fail1;
 498                 }
 499
 500                 pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
 501                 if (pci_rc < 0) {
 502                         debugf0("i3200 init fail\n");
 503                         pci_rc = -ENODEV;
 504                         goto fail1;
 505                 }
 506         }
 507
 508         return 0;
 509
 510 fail1:
 511         pci_unregister_driver(&i3200_driver);
 512
 513 fail0:
 514         if (mci_pdev)
 515                 pci_dev_put(mci_pdev);
 516
 517         return pci_rc;
 518 }
 519
 520 static void __exit i3200_exit(void)
 521 {
 522         debugf3("MC: %s()\n", __func__);
 523
 524         pci_unregister_driver(&i3200_driver);
 525         if (!i3200_registered) {
 526                 i3200_remove_one(mci_pdev);
 527                 pci_dev_put(mci_pdev);
 528         }
 529 }
 530
 531 module_init(i3200_init);
 532 module_exit(i3200_exit);
 533
 534 MODULE_LICENSE("GPL");
 535 MODULE_AUTHOR("Akamai Technologies, Inc.");
 536 MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");
 537
 538 module_param(edac_op_state, int, 0444);
 539 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");