drivers/i2c/busses/i2c-mxs.c

   1 /*
   2  * Freescale MXS I2C bus driver
   3  *
   4  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
   5  *
   6  * based on a (non-working) driver which was:
   7  *
   8  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   9  *
  10  * TODO: add dma-support if platform-support for it is available
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  */
  18
  19 #include <linux/slab.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/i2c.h>
  23 #include <linux/err.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/completion.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/io.h>
  29
  30 #include <mach/common.h>
  31
  32 #define DRIVER_NAME "mxs-i2c"
  33
  34 #define MXS_I2C_CTRL0           (0x00)
  35 #define MXS_I2C_CTRL0_SET       (0x04)
  36
  37 #define MXS_I2C_CTRL0_SFTRST                    0x80000000
  38 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST          0x02000000
  39 #define MXS_I2C_CTRL0_RETAIN_CLOCK              0x00200000
  40 #define MXS_I2C_CTRL0_POST_SEND_STOP            0x00100000
  41 #define MXS_I2C_CTRL0_PRE_SEND_START            0x00080000
  42 #define MXS_I2C_CTRL0_MASTER_MODE               0x00020000
  43 #define MXS_I2C_CTRL0_DIRECTION                 0x00010000
  44 #define MXS_I2C_CTRL0_XFER_COUNT(v)             ((v) & 0x0000FFFF)
  45
  46 #define MXS_I2C_CTRL1           (0x40)
  47 #define MXS_I2C_CTRL1_SET       (0x44)
  48 #define MXS_I2C_CTRL1_CLR       (0x48)
  49
  50 #define MXS_I2C_CTRL1_BUS_FREE_IRQ              0x80
  51 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ     0x40
  52 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ          0x20
  53 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
  54 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ            0x08
  55 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ           0x04
  56 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ            0x02
  57 #define MXS_I2C_CTRL1_SLAVE_IRQ                 0x01
  58
  59 #define MXS_I2C_IRQ_MASK        (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
  60                                  MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
  61                                  MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
  62                                  MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
  63                                  MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
  64                                  MXS_I2C_CTRL1_SLAVE_IRQ)
  65
  66 #define MXS_I2C_QUEUECTRL       (0x60)
  67 #define MXS_I2C_QUEUECTRL_SET   (0x64)
  68 #define MXS_I2C_QUEUECTRL_CLR   (0x68)
  69
  70 #define MXS_I2C_QUEUECTRL_QUEUE_RUN             0x20
  71 #define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE        0x04
  72
  73 #define MXS_I2C_QUEUESTAT       (0x70)
  74 #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY        0x00002000
  75
  76 #define MXS_I2C_QUEUECMD        (0x80)
  77
  78 #define MXS_I2C_QUEUEDATA       (0x90)
  79
  80 #define MXS_I2C_DATA            (0xa0)
  81
  82
  83 #define MXS_CMD_I2C_SELECT      (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
  84                                  MXS_I2C_CTRL0_PRE_SEND_START | \
  85                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  86                                  MXS_I2C_CTRL0_DIRECTION |      \
  87                                  MXS_I2C_CTRL0_XFER_COUNT(1))
  88
  89 #define MXS_CMD_I2C_WRITE       (MXS_I2C_CTRL0_PRE_SEND_START | \
  90                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  91                                  MXS_I2C_CTRL0_DIRECTION)
  92
  93 #define MXS_CMD_I2C_READ        (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
  94                                  MXS_I2C_CTRL0_MASTER_MODE)
  95
  96 /**
  97  * struct mxs_i2c_dev - per device, private MXS-I2C data
  98  *
  99  * @dev: driver model device node
 100  * @regs: IO registers pointer
 101  * @cmd_complete: completion object for transaction wait
 102  * @cmd_err: error code for last transaction
 103  * @adapter: i2c subsystem adapter node
 104  */
 105 struct mxs_i2c_dev {
 106         struct device *dev;
 107         void __iomem *regs;
 108         struct completion cmd_complete;
 109         u32 cmd_err;
 110         struct i2c_adapter adapter;
 111 };
 112
 113 /*
 114  * TODO: check if calls to here are really needed. If not, we could get rid of
 115  * mxs_reset_block and the mach-dependency. Needs an I2C analyzer, probably.
 116  */
 117 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 118 {
 119         mxs_reset_block(i2c->regs);
 120         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 121         writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
 122                         i2c->regs + MXS_I2C_QUEUECTRL_SET);
 123 }
 124
 125 static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len,
 126                                         int flags)
 127 {
 128         u32 data;
 129
 130         writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD);
 131
 132         data = (addr << 1) | I2C_SMBUS_READ;
 133         writel(data, i2c->regs + MXS_I2C_DATA);
 134
 135         data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags;
 136         writel(data, i2c->regs + MXS_I2C_QUEUECMD);
 137 }
 138
 139 static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c,
 140                                     u8 addr, u8 *buf, int len, int flags)
 141 {
 142         u32 data;
 143         int i, shifts_left;
 144
 145         data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
 146         writel(data, i2c->regs + MXS_I2C_QUEUECMD);
 147
 148         /*
 149          * We have to copy the slave address (u8) and buffer (arbitrary number
 150          * of u8) into the data register (u32). To achieve that, the u8 are put
 151          * into the MSBs of 'data' which is then shifted for the next u8. When
 152          * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32
 153          * looks like this:
 154          *
 155          *  3          2          1          0
 156          * 10987654|32109876|54321098|76543210
 157          * --------+--------+--------+--------
 158          * buffer+2|buffer+1|buffer+0|slave_addr
 159          */
 160
 161         data = ((addr << 1) | I2C_SMBUS_WRITE) << 24;
 162
 163         for (i = 0; i < len; i++) {
 164                 data >>= 8;
 165                 data |= buf[i] << 24;
 166                 if ((i & 3) == 2)
 167                         writel(data, i2c->regs + MXS_I2C_DATA);
 168         }
 169
 170         /* Write out the remaining bytes if any */
 171         shifts_left = 24 - (i & 3) * 8;
 172         if (shifts_left)
 173                 writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA);
 174 }
 175
 176 /*
 177  * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the
 178  * rd_threshold to 1). Couldn't get this to work, though.
 179  */
 180 static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c)
 181 {
 182         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 183
 184         while (readl(i2c->regs + MXS_I2C_QUEUESTAT)
 185                         & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) {
 186                         if (time_after(jiffies, timeout))
 187                                 return -ETIMEDOUT;
 188                         cond_resched();
 189         }
 190
 191         return 0;
 192 }
 193
 194 static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
 195 {
 196         u32 data;
 197         int i;
 198
 199         for (i = 0; i < len; i++) {
 200                 if ((i & 3) == 0) {
 201                         if (mxs_i2c_wait_for_data(i2c))
 202                                 return -ETIMEDOUT;
 203                         data = readl(i2c->regs + MXS_I2C_QUEUEDATA);
 204                 }
 205                 buf[i] = data & 0xff;
 206                 data >>= 8;
 207         }
 208
 209         return 0;
 210 }
 211
 212 /*
 213  * Low level master read/write transaction.
 214  */
 215 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 216                                 int stop)
 217 {
 218         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 219         int ret;
 220         int flags;
 221
 222         init_completion(&i2c->cmd_complete);
 223
 224         dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 225                 msg->addr, msg->len, msg->flags, stop);
 226
 227         if (msg->len == 0)
 228                 return -EINVAL;
 229
 230         flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
 231
 232         if (msg->flags & I2C_M_RD)
 233                 mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
 234         else
 235                 mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
 236                                         flags);
 237
 238         writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
 239                         i2c->regs + MXS_I2C_QUEUECTRL_SET);
 240
 241         ret = wait_for_completion_timeout(&i2c->cmd_complete,
 242                                                 msecs_to_jiffies(1000));
 243         if (ret == 0)
 244                 goto timeout;
 245
 246         if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
 247                 ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
 248                 if (ret)
 249                         goto timeout;
 250         }
 251
 252         if (i2c->cmd_err == -ENXIO)
 253                 mxs_i2c_reset(i2c);
 254
 255         dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
 256
 257         return i2c->cmd_err;
 258
 259 timeout:
 260         dev_dbg(i2c->dev, "Timeout!\n");
 261         mxs_i2c_reset(i2c);
 262         return -ETIMEDOUT;
 263 }
 264
 265 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 266                         int num)
 267 {
 268         int i;
 269         int err;
 270
 271         for (i = 0; i < num; i++) {
 272                 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
 273                 if (err)
 274                         return err;
 275         }
 276
 277         return num;
 278 }
 279
 280 static u32 mxs_i2c_func(struct i2c_adapter *adap)
 281 {
 282         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 283 }
 284
 285 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
 286 {
 287         struct mxs_i2c_dev *i2c = dev_id;
 288         u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
 289
 290         if (!stat)
 291                 return IRQ_NONE;
 292
 293         if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 294                 i2c->cmd_err = -ENXIO;
 295         else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 296                     MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 297                     MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
 298                 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
 299                 i2c->cmd_err = -EIO;
 300         else
 301                 i2c->cmd_err = 0;
 302
 303         complete(&i2c->cmd_complete);
 304
 305         writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
 306         return IRQ_HANDLED;
 307 }
 308
 309 static const struct i2c_algorithm mxs_i2c_algo = {
 310         .master_xfer = mxs_i2c_xfer,
 311         .functionality = mxs_i2c_func,
 312 };
 313
 314 static int __devinit mxs_i2c_probe(struct platform_device *pdev)
 315 {
 316         struct device *dev = &pdev->dev;
 317         struct mxs_i2c_dev *i2c;
 318         struct i2c_adapter *adap;
 319         struct resource *res;
 320         resource_size_t res_size;
 321         int err, irq;
 322
 323         i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
 324         if (!i2c)
 325                 return -ENOMEM;
 326
 327         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 328         if (!res)
 329                 return -ENOENT;
 330
 331         res_size = resource_size(res);
 332         if (!devm_request_mem_region(dev, res->start, res_size, res->name))
 333                 return -EBUSY;
 334
 335         i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
 336         if (!i2c->regs)
 337                 return -EBUSY;
 338
 339         irq = platform_get_irq(pdev, 0);
 340         if (irq < 0)
 341                 return irq;
 342
 343         err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
 344         if (err)
 345                 return err;
 346
 347         i2c->dev = dev;
 348         platform_set_drvdata(pdev, i2c);
 349
 350         /* Do reset to enforce correct startup after pinmuxing */
 351         mxs_i2c_reset(i2c);
 352
 353         adap = &i2c->adapter;
 354         strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
 355         adap->owner = THIS_MODULE;
 356         adap->algo = &mxs_i2c_algo;
 357         adap->dev.parent = dev;
 358         adap->nr = pdev->id;
 359         i2c_set_adapdata(adap, i2c);
 360         err = i2c_add_numbered_adapter(adap);
 361         if (err) {
 362                 dev_err(dev, "Failed to add adapter (%d)\n", err);
 363                 writel(MXS_I2C_CTRL0_SFTRST,
 364                                 i2c->regs + MXS_I2C_CTRL0_SET);
 365                 return err;
 366         }
 367
 368         return 0;
 369 }
 370
 371 static int __devexit mxs_i2c_remove(struct platform_device *pdev)
 372 {
 373         struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
 374         int ret;
 375
 376         ret = i2c_del_adapter(&i2c->adapter);
 377         if (ret)
 378                 return -EBUSY;
 379
 380         writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
 381                         i2c->regs + MXS_I2C_QUEUECTRL_CLR);
 382         writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
 383
 384         platform_set_drvdata(pdev, NULL);
 385
 386         return 0;
 387 }
 388
 389 static struct platform_driver mxs_i2c_driver = {
 390         .driver = {
 391                    .name = DRIVER_NAME,
 392                    .owner = THIS_MODULE,
 393                    },
 394         .remove = __devexit_p(mxs_i2c_remove),
 395 };
 396
 397 static int __init mxs_i2c_init(void)
 398 {
 399         return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
 400 }
 401 subsys_initcall(mxs_i2c_init);
 402
 403 static void __exit mxs_i2c_exit(void)
 404 {
 405         platform_driver_unregister(&mxs_i2c_driver);
 406 }
 407 module_exit(mxs_i2c_exit);
 408
 409 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
 410 MODULE_DESCRIPTION("MXS I2C Bus Driver");
 411 MODULE_LICENSE("GPL");
 412 MODULE_ALIAS("platform:" DRIVER_NAME);