nilfs2: unbreak compat ioctl
[zen-stable.git] / drivers / pcmcia / m32r_pcc.h
blobf95c58563bc8f648e3027ecccbca5b47ed6de400
1 /*
2 * Copyright (C) 2001 by Hiroyuki Kondo
3 */
5 #define M32R_MAX_PCC 2
7 /*
8 * M32R PC Card Controller
9 */
10 #define M32R_PCC0_BASE 0x00ef7000
11 #define M32R_PCC1_BASE 0x00ef7020
14 * Register offsets
16 #define PCCR 0x00
17 #define PCADR 0x04
18 #define PCMOD 0x08
19 #define PCIRC 0x0c
20 #define PCCSIGCR 0x10
21 #define PCATCR 0x14
24 * PCCR
26 #define PCCR_PCEN (1UL<<(31-31))
29 * PCIRC
31 #define PCIRC_BWERR (1UL<<(31-7))
32 #define PCIRC_CDIN1 (1UL<<(31-14))
33 #define PCIRC_CDIN2 (1UL<<(31-15))
34 #define PCIRC_BEIEN (1UL<<(31-23))
35 #define PCIRC_CIIEN (1UL<<(31-30))
36 #define PCIRC_COIEN (1UL<<(31-31))
39 * PCCSIGCR
41 #define PCCSIGCR_SEN (1UL<<(31-3))
42 #define PCCSIGCR_VEN (1UL<<(31-7))
43 #define PCCSIGCR_CRST (1UL<<(31-15))
44 #define PCCSIGCR_COCR (1UL<<(31-31))
49 #define PCMOD_AS_ATTRIB (1UL<<(31-19))
50 #define PCMOD_AS_IO (1UL<<(31-18))
52 #define PCMOD_CBSZ (1UL<<(31-23)) /* set for 8bit */
54 #define PCMOD_DBEX (1UL<<(31-31)) /* set for excahnge */
57 * M32R PCC Map addr
59 #define M32R_PCC0_MAPBASE 0x14000000
60 #define M32R_PCC1_MAPBASE 0x16000000
62 #define M32R_PCC_MAPMAX 0x02000000
64 #define M32R_PCC_MAPSIZE 0x00001000 /* XXX */
65 #define M32R_PCC_MAPMASK (~(M32R_PCC_MAPMAX-1))