arch/arm/plat-mxc/clock.c

   1 /*
   2  * Based on arch/arm/plat-omap/clock.c
   3  *
   4  * Copyright (C) 2004 - 2005 Nokia corporation
   5  * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
   7  * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
   8  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA  02110-1301, USA.
  23  */
  24
  25 /* #define DEBUG */
  26
  27 #include <linux/clk.h>
  28 #include <linux/err.h>
  29 #include <linux/errno.h>
  30 #include <linux/init.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/module.h>
  35 #include <linux/mutex.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/proc_fs.h>
  38 #include <linux/semaphore.h>
  39 #include <linux/string.h>
  40
  41 #include <mach/clock.h>
  42 #include <mach/hardware.h>
  43
  44 static LIST_HEAD(clocks);
  45 static DEFINE_MUTEX(clocks_mutex);
  46
  47 /*-------------------------------------------------------------------------
  48  * Standard clock functions defined in include/linux/clk.h
  49  *-------------------------------------------------------------------------*/
  50
  51 static void __clk_disable(struct clk *clk)
  52 {
  53         if (clk == NULL || IS_ERR(clk))
  54                 return;
  55
  56         __clk_disable(clk->parent);
  57         __clk_disable(clk->secondary);
  58
  59         WARN_ON(!clk->usecount);
  60         if (!(--clk->usecount) && clk->disable)
  61                 clk->disable(clk);
  62 }
  63
  64 static int __clk_enable(struct clk *clk)
  65 {
  66         if (clk == NULL || IS_ERR(clk))
  67                 return -EINVAL;
  68
  69         __clk_enable(clk->parent);
  70         __clk_enable(clk->secondary);
  71
  72         if (clk->usecount++ == 0 && clk->enable)
  73                 clk->enable(clk);
  74
  75         return 0;
  76 }
  77
  78 /* This function increments the reference count on the clock and enables the
  79  * clock if not already enabled. The parent clock tree is recursively enabled
  80  */
  81 int clk_enable(struct clk *clk)
  82 {
  83         int ret = 0;
  84
  85         if (clk == NULL || IS_ERR(clk))
  86                 return -EINVAL;
  87
  88         mutex_lock(&clocks_mutex);
  89         ret = __clk_enable(clk);
  90         mutex_unlock(&clocks_mutex);
  91
  92         return ret;
  93 }
  94 EXPORT_SYMBOL(clk_enable);
  95
  96 /* This function decrements the reference count on the clock and disables
  97  * the clock when reference count is 0. The parent clock tree is
  98  * recursively disabled
  99  */
 100 void clk_disable(struct clk *clk)
 101 {
 102         if (clk == NULL || IS_ERR(clk))
 103                 return;
 104
 105         mutex_lock(&clocks_mutex);
 106         __clk_disable(clk);
 107         mutex_unlock(&clocks_mutex);
 108 }
 109 EXPORT_SYMBOL(clk_disable);
 110
 111 /* Retrieve the *current* clock rate. If the clock itself
 112  * does not provide a special calculation routine, ask
 113  * its parent and so on, until one is able to return
 114  * a valid clock rate
 115  */
 116 unsigned long clk_get_rate(struct clk *clk)
 117 {
 118         if (clk == NULL || IS_ERR(clk))
 119                 return 0UL;
 120
 121         if (clk->get_rate)
 122                 return clk->get_rate(clk);
 123
 124         return clk_get_rate(clk->parent);
 125 }
 126 EXPORT_SYMBOL(clk_get_rate);
 127
 128 /* Round the requested clock rate to the nearest supported
 129  * rate that is less than or equal to the requested rate.
 130  * This is dependent on the clock's current parent.
 131  */
 132 long clk_round_rate(struct clk *clk, unsigned long rate)
 133 {
 134         if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
 135                 return 0;
 136
 137         return clk->round_rate(clk, rate);
 138 }
 139 EXPORT_SYMBOL(clk_round_rate);
 140
 141 /* Set the clock to the requested clock rate. The rate must
 142  * match a supported rate exactly based on what clk_round_rate returns
 143  */
 144 int clk_set_rate(struct clk *clk, unsigned long rate)
 145 {
 146         int ret = -EINVAL;
 147
 148         if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
 149                 return ret;
 150
 151         mutex_lock(&clocks_mutex);
 152         ret = clk->set_rate(clk, rate);
 153         mutex_unlock(&clocks_mutex);
 154
 155         return ret;
 156 }
 157 EXPORT_SYMBOL(clk_set_rate);
 158
 159 /* Set the clock's parent to another clock source */
 160 int clk_set_parent(struct clk *clk, struct clk *parent)
 161 {
 162         int ret = -EINVAL;
 163
 164         if (clk == NULL || IS_ERR(clk) || parent == NULL ||
 165             IS_ERR(parent) || clk->set_parent == NULL)
 166                 return ret;
 167
 168         mutex_lock(&clocks_mutex);
 169         ret = clk->set_parent(clk, parent);
 170         if (ret == 0)
 171                 clk->parent = parent;
 172         mutex_unlock(&clocks_mutex);
 173
 174         return ret;
 175 }
 176 EXPORT_SYMBOL(clk_set_parent);
 177
 178 /* Retrieve the clock's parent clock source */
 179 struct clk *clk_get_parent(struct clk *clk)
 180 {
 181         struct clk *ret = NULL;
 182
 183         if (clk == NULL || IS_ERR(clk))
 184                 return ret;
 185
 186         return clk->parent;
 187 }
 188 EXPORT_SYMBOL(clk_get_parent);
 189
 190 /*
 191  * Get the resulting clock rate from a PLL register value and the input
 192  * frequency. PLLs with this register layout can at least be found on
 193  * MX1, MX21, MX27 and MX31
 194  *
 195  *                  mfi + mfn / (mfd + 1)
 196  *  f = 2 * f_ref * --------------------
 197  *                        pd + 1
 198  */
 199 unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
 200 {
 201         long long ll;
 202         int mfn_abs;
 203         unsigned int mfi, mfn, mfd, pd;
 204
 205         mfi = (reg_val >> 10) & 0xf;
 206         mfn = reg_val & 0x3ff;
 207         mfd = (reg_val >> 16) & 0x3ff;
 208         pd =  (reg_val >> 26) & 0xf;
 209
 210         mfi = mfi <= 5 ? 5 : mfi;
 211
 212         mfn_abs = mfn;
 213
 214         /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
 215          * 2's complements number
 216          */
 217         if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
 218                 mfn_abs = 0x400 - mfn;
 219
 220         freq *= 2;
 221         freq /= pd + 1;
 222
 223         ll = (unsigned long long)freq * mfn_abs;
 224
 225         do_div(ll, mfd + 1);
 226
 227         if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
 228                 ll = -ll;
 229
 230         ll = (freq * mfi) + ll;
 231
 232         return ll;
 233 }