drivers/staging/rtl8192e/r819xE_cmdpkt.h

   1 #ifndef R819XUSB_CMDPKT_H
   2 #define R819XUSB_CMDPKT_H
   3 /* Different command packet have dedicated message length and definition. */
   4 #define         CMPK_RX_TX_FB_SIZE                                      sizeof(cmpk_txfb_t)             //20
   5 #define         CMPK_TX_SET_CONFIG_SIZE                         sizeof(cmpk_set_cfg_t)  //16
   6 #define         CMPK_BOTH_QUERY_CONFIG_SIZE                     sizeof(cmpk_set_cfg_t)  //16
   7 #define         CMPK_RX_TX_STS_SIZE                                     sizeof(cmpk_tx_status_t)//
   8 #define         CMPK_RX_DBG_MSG_SIZE                    sizeof(cmpk_rx_dbginfo_t)//
   9 #define         CMPK_TX_RAHIS_SIZE                      sizeof(cmpk_tx_rahis_t)
  10
  11 /* 2008/05/08 amy For USB constant. */
  12 #define ISR_TxBcnOk                                     BIT27                   // Transmit Beacon OK
  13 #define ISR_TxBcnErr                            BIT26                   // Transmit Beacon Error
  14 #define ISR_BcnTimerIntr                        BIT13                   // Beacon Timer Interrupt
  15
  16 #if 0
  17 /* Define packet type. */
  18 typedef enum tag_packet_type
  19 {
  20     PACKET_BROADCAST,
  21     PACKET_MULTICAST,
  22     PACKET_UNICAST,
  23     PACKET_TYPE_MAX
  24 }cmpk_pkt_type_e;
  25 #endif
  26
  27 /* Define element ID of command packet. */
  28
  29 /*------------------------------Define structure----------------------------*/
  30 /* Define different command packet structure. */
  31 /* 1. RX side: TX feedback packet. */
  32 typedef struct tag_cmd_pkt_tx_feedback
  33 {
  34         // DWORD 0
  35         u8      element_id;                     /* Command packet type. */
  36         u8      length;                         /* Command packet length. */
  37         /* 2007/07/05 MH Change tx feedback info field. */
  38         /*------TX Feedback Info Field */
  39         u8      TID:4;                          /* */
  40         u8      fail_reason:3;          /* */
  41         u8      tok:1;                          /* Transmit ok. */
  42         u8      reserve1:4;                     /* */
  43         u8      pkt_type:2;             /* */
  44         u8      bandwidth:1;            /* */
  45         u8      qos_pkt:1;                      /* */
  46
  47         // DWORD 1
  48         u8      reserve2;                       /* */
  49         /*------TX Feedback Info Field */
  50         u8      retry_cnt;                      /* */
  51         u16     pkt_id;                         /* */
  52
  53         // DWORD 3
  54         u16     seq_num;                        /* */
  55         u8      s_rate;                         /* Start rate. */
  56         u8      f_rate;                         /* Final rate. */
  57
  58         // DWORD 4
  59         u8      s_rts_rate;                     /* */
  60         u8      f_rts_rate;                     /* */
  61         u16     pkt_length;                     /* */
  62
  63         // DWORD 5
  64         u16     reserve3;                       /* */
  65         u16     duration;                       /* */
  66 }cmpk_txfb_t;
  67
  68 /* 2. RX side: Interrupt status packet. It includes Beacon State,
  69           Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */
  70 typedef struct tag_cmd_pkt_interrupt_status
  71 {
  72         u8      element_id;                     /* Command packet type. */
  73         u8      length;                         /* Command packet length. */
  74         u16     reserve;
  75         u32     interrupt_status;                               /* Interrupt Status. */
  76 }cmpk_intr_sta_t;
  77
  78
  79 /* 3. TX side: Set configuration packet. */
  80 typedef struct tag_cmd_pkt_set_configuration
  81 {
  82         u8      element_id;                     /* Command packet type. */
  83         u8      length;                         /* Command packet length. */
  84         u16     reserve1;                       /* */
  85         u8      cfg_reserve1:3;
  86         u8      cfg_size:2;                     /* Configuration info. */
  87         u8      cfg_type:2;                     /* Configuration info. */
  88         u8      cfg_action:1;           /* Configuration info. */
  89         u8      cfg_reserve2;           /* Configuration info. */
  90         u8      cfg_page:4;                     /* Configuration info. */
  91         u8      cfg_reserve3:4;         /* Configuration info. */
  92         u8      cfg_offset;                     /* Configuration info. */
  93         u32     value;                          /* */
  94         u32     mask;                           /* */
  95 }cmpk_set_cfg_t;
  96
  97 /* 4. Both side : TX/RX query configuraton packet. The query structure is the
  98       same as set configuration. */
  99 #define         cmpk_query_cfg_t        cmpk_set_cfg_t
 100
 101 /* 5. Multi packet feedback status. */
 102 typedef struct tag_tx_stats_feedback // PJ quick rxcmd 09042007
 103 {
 104         // For endian transfer --> Driver will not the same as firmware structure.
 105         // DW 0
 106         u16     reserve1;
 107         u8      length;                         // Command packet length
 108         u8      element_id;                     // Command packet type
 109
 110         // DW 1
 111         u16     txfail;                         // Tx Fail count
 112         u16     txok;                           // Tx ok count
 113
 114         // DW 2
 115         u16     txmcok;                         // tx multicast
 116         u16     txretry;                        // Tx Retry count
 117
 118         // DW 3
 119         u16  txucok;                            // tx unicast
 120         u16     txbcok;                         // tx broadcast
 121
 122         // DW 4
 123         u16     txbcfail;                       //
 124         u16     txmcfail;                       //
 125
 126         // DW 5
 127         u16     reserve2;                       //
 128         u16     txucfail;                       //
 129
 130         // DW 6-8
 131         u32     txmclength;
 132         u32     txbclength;
 133         u32     txuclength;
 134
 135         // DW 9
 136         u16     reserve3_23;
 137         u8      reserve3_1;
 138         u8      rate;
 139 }__attribute__((packed)) cmpk_tx_status_t;
 140
 141 /* 6. Debug feedback message. */
 142 /* 2007/10/23 MH Define RX debug message  */
 143 typedef struct tag_rx_debug_message_feedback
 144 {
 145         // For endian transfer --> for driver
 146         // DW 0
 147         u16     reserve1;
 148         u8      length;                         // Command packet length
 149         u8      element_id;                     // Command packet type
 150
 151         // DW 1-??
 152         // Variable debug message.
 153
 154 }cmpk_rx_dbginfo_t;
 155
 156 /* 2008/03/20 MH Define transmit rate history. For big endian format. */
 157 typedef struct tag_tx_rate_history
 158 {
 159         // For endian transfer --> for driver
 160         // DW 0
 161         u8      element_id;                     // Command packet type
 162         u8      length;                         // Command packet length
 163         u16     reserved1;
 164
 165         // DW 1-2       CCK rate counter
 166         u16     cck[4];
 167
 168         // DW 3-6
 169         u16     ofdm[8];
 170
 171         // DW 7-14
 172         //UINT16        MCS_BW0_SG0[16];
 173
 174         // DW 15-22
 175         //UINT16        MCS_BW1_SG0[16];
 176
 177         // DW 23-30
 178         //UINT16        MCS_BW0_SG1[16];
 179
 180         // DW 31-38
 181         //UINT16        MCS_BW1_SG1[16];
 182
 183         // DW 7-14      BW=0 SG=0
 184         // DW 15-22     BW=1 SG=0
 185         // DW 23-30     BW=0 SG=1
 186         // DW 31-38     BW=1 SG=1
 187         u16     ht_mcs[4][16];
 188
 189 }__attribute__((packed)) cmpk_tx_rahis_t;
 190
 191 typedef enum tag_command_packet_directories
 192 {
 193     RX_TX_FEEDBACK = 0,
 194     RX_INTERRUPT_STATUS         = 1,
 195     TX_SET_CONFIG                               = 2,
 196     BOTH_QUERY_CONFIG                   = 3,
 197     RX_TX_STATUS                                = 4,
 198     RX_DBGINFO_FEEDBACK         = 5,
 199     RX_TX_PER_PKT_FEEDBACK              = 6,
 200     RX_TX_RATE_HISTORY          = 7,
 201     RX_CMD_ELE_MAX
 202 }cmpk_element_e;
 203
 204 u32 cmpk_message_handle_rx(struct r8192_priv *priv, struct ieee80211_rx_stats *pstats);
 205
 206
 207 #endif