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ASoC: tlv312aic23: unbreak resume
[zen-stable.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
blob6753f5955aa69e94310f6ef61e3729f597e9e7dc
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static u32 i915_gem_get_seqno(struct drm_device *dev)
56 {
57 drm_i915_private_t *dev_priv = dev->dev_private;
58 u32 seqno;
59
60 seqno = dev_priv->next_seqno;
61
62 /* reserve 0 for non-seqno */
63 if (++dev_priv->next_seqno == 0)
64 dev_priv->next_seqno = 1;
65
66 return seqno;
67 }
68
69 static int
70 render_ring_flush(struct intel_ring_buffer *ring,
71 u32 invalidate_domains,
72 u32 flush_domains)
73 {
74 struct drm_device *dev = ring->dev;
75 u32 cmd;
76 int ret;
77
78 /*
79 * read/write caches:
80 *
81 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
82 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
83 * also flushed at 2d versus 3d pipeline switches.
84 *
85 * read-only caches:
86 *
87 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
88 * MI_READ_FLUSH is set, and is always flushed on 965.
89 *
90 * I915_GEM_DOMAIN_COMMAND may not exist?
91 *
92 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
93 * invalidated when MI_EXE_FLUSH is set.
94 *
95 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
96 * invalidated with every MI_FLUSH.
97 *
98 * TLBs:
99 *
100 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
101 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
102 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
103 * are flushed at any MI_FLUSH.
104 */
105
106 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
107 if ((invalidate_domains|flush_domains) &
108 I915_GEM_DOMAIN_RENDER)
109 cmd &= ~MI_NO_WRITE_FLUSH;
110 if (INTEL_INFO(dev)->gen < 4) {
111 /*
112 * On the 965, the sampler cache always gets flushed
113 * and this bit is reserved.
114 */
115 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
116 cmd |= MI_READ_FLUSH;
117 }
118 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
119 cmd |= MI_EXE_FLUSH;
120
121 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
122 (IS_G4X(dev) || IS_GEN5(dev)))
123 cmd |= MI_INVALIDATE_ISP;
124
125 ret = intel_ring_begin(ring, 2);
126 if (ret)
127 return ret;
128
129 intel_ring_emit(ring, cmd);
130 intel_ring_emit(ring, MI_NOOP);
131 intel_ring_advance(ring);
132
133 return 0;
134 }
135
136 /**
137 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
138 * implementing two workarounds on gen6. From section 1.4.7.1
139 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
140 *
141 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
142 * produced by non-pipelined state commands), software needs to first
143 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
144 * 0.
145 *
146 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
147 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
148 *
149 * And the workaround for these two requires this workaround first:
150 *
151 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
152 * BEFORE the pipe-control with a post-sync op and no write-cache
153 * flushes.
154 *
155 * And this last workaround is tricky because of the requirements on
156 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
157 * volume 2 part 1:
158 *
159 * "1 of the following must also be set:
160 * - Render Target Cache Flush Enable ([12] of DW1)
161 * - Depth Cache Flush Enable ([0] of DW1)
162 * - Stall at Pixel Scoreboard ([1] of DW1)
163 * - Depth Stall ([13] of DW1)
164 * - Post-Sync Operation ([13] of DW1)
165 * - Notify Enable ([8] of DW1)"
166 *
167 * The cache flushes require the workaround flush that triggered this
168 * one, so we can't use it. Depth stall would trigger the same.
169 * Post-sync nonzero is what triggered this second workaround, so we
170 * can't use that one either. Notify enable is IRQs, which aren't
171 * really our business. That leaves only stall at scoreboard.
172 */
173 static int
174 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
175 {
176 struct pipe_control *pc = ring->private;
177 u32 scratch_addr = pc->gtt_offset + 128;
178 int ret;
179
180
181 ret = intel_ring_begin(ring, 6);
182 if (ret)
183 return ret;
184
185 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
186 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
187 PIPE_CONTROL_STALL_AT_SCOREBOARD);
188 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
189 intel_ring_emit(ring, 0); /* low dword */
190 intel_ring_emit(ring, 0); /* high dword */
191 intel_ring_emit(ring, MI_NOOP);
192 intel_ring_advance(ring);
193
194 ret = intel_ring_begin(ring, 6);
195 if (ret)
196 return ret;
197
198 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
199 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
200 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
201 intel_ring_emit(ring, 0);
202 intel_ring_emit(ring, 0);
203 intel_ring_emit(ring, MI_NOOP);
204 intel_ring_advance(ring);
205
206 return 0;
207 }
208
209 static int
210 gen6_render_ring_flush(struct intel_ring_buffer *ring,
211 u32 invalidate_domains, u32 flush_domains)
212 {
213 u32 flags = 0;
214 struct pipe_control *pc = ring->private;
215 u32 scratch_addr = pc->gtt_offset + 128;
216 int ret;
217
218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 intel_emit_post_sync_nonzero_flush(ring);
220
221 /* Just flush everything. Experiments have shown that reducing the
222 * number of bits based on the write domains has little performance
223 * impact.
224 */
225 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
226 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
227 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
228 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
232
233 ret = intel_ring_begin(ring, 6);
234 if (ret)
235 return ret;
236
237 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
238 intel_ring_emit(ring, flags);
239 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
240 intel_ring_emit(ring, 0); /* lower dword */
241 intel_ring_emit(ring, 0); /* uppwer dword */
242 intel_ring_emit(ring, MI_NOOP);
243 intel_ring_advance(ring);
244
245 return 0;
246 }
247
248 static void ring_write_tail(struct intel_ring_buffer *ring,
249 u32 value)
250 {
251 drm_i915_private_t *dev_priv = ring->dev->dev_private;
252 I915_WRITE_TAIL(ring, value);
253 }
254
255 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
256 {
257 drm_i915_private_t *dev_priv = ring->dev->dev_private;
258 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
259 RING_ACTHD(ring->mmio_base) : ACTHD;
260
261 return I915_READ(acthd_reg);
262 }
263
264 static int init_ring_common(struct intel_ring_buffer *ring)
265 {
266 drm_i915_private_t *dev_priv = ring->dev->dev_private;
267 struct drm_i915_gem_object *obj = ring->obj;
268 u32 head;
269
270 /* Stop the ring if it's running. */
271 I915_WRITE_CTL(ring, 0);
272 I915_WRITE_HEAD(ring, 0);
273 ring->write_tail(ring, 0);
274
275 /* Initialize the ring. */
276 I915_WRITE_START(ring, obj->gtt_offset);
277 head = I915_READ_HEAD(ring) & HEAD_ADDR;
278
279 /* G45 ring initialization fails to reset head to zero */
280 if (head != 0) {
281 DRM_DEBUG_KMS("%s head not reset to zero "
282 "ctl %08x head %08x tail %08x start %08x\n",
283 ring->name,
284 I915_READ_CTL(ring),
285 I915_READ_HEAD(ring),
286 I915_READ_TAIL(ring),
287 I915_READ_START(ring));
288
289 I915_WRITE_HEAD(ring, 0);
290
291 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
292 DRM_ERROR("failed to set %s head to zero "
293 "ctl %08x head %08x tail %08x start %08x\n",
294 ring->name,
295 I915_READ_CTL(ring),
296 I915_READ_HEAD(ring),
297 I915_READ_TAIL(ring),
298 I915_READ_START(ring));
299 }
300 }
301
302 I915_WRITE_CTL(ring,
303 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
304 | RING_VALID);
305
306 /* If the head is still not zero, the ring is dead */
307 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
308 I915_READ_START(ring) != obj->gtt_offset ||
309 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
310 DRM_ERROR("%s initialization failed "
311 "ctl %08x head %08x tail %08x start %08x\n",
312 ring->name,
313 I915_READ_CTL(ring),
314 I915_READ_HEAD(ring),
315 I915_READ_TAIL(ring),
316 I915_READ_START(ring));
317 return -EIO;
318 }
319
320 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
321 i915_kernel_lost_context(ring->dev);
322 else {
323 ring->head = I915_READ_HEAD(ring);
324 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
325 ring->space = ring_space(ring);
326 }
327
328 return 0;
329 }
330
331 static int
332 init_pipe_control(struct intel_ring_buffer *ring)
333 {
334 struct pipe_control *pc;
335 struct drm_i915_gem_object *obj;
336 int ret;
337
338 if (ring->private)
339 return 0;
340
341 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
342 if (!pc)
343 return -ENOMEM;
344
345 obj = i915_gem_alloc_object(ring->dev, 4096);
346 if (obj == NULL) {
347 DRM_ERROR("Failed to allocate seqno page\n");
348 ret = -ENOMEM;
349 goto err;
350 }
351
352 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
353
354 ret = i915_gem_object_pin(obj, 4096, true);
355 if (ret)
356 goto err_unref;
357
358 pc->gtt_offset = obj->gtt_offset;
359 pc->cpu_page = kmap(obj->pages[0]);
360 if (pc->cpu_page == NULL)
361 goto err_unpin;
362
363 pc->obj = obj;
364 ring->private = pc;
365 return 0;
366
367 err_unpin:
368 i915_gem_object_unpin(obj);
369 err_unref:
370 drm_gem_object_unreference(&obj->base);
371 err:
372 kfree(pc);
373 return ret;
374 }
375
376 static void
377 cleanup_pipe_control(struct intel_ring_buffer *ring)
378 {
379 struct pipe_control *pc = ring->private;
380 struct drm_i915_gem_object *obj;
381
382 if (!ring->private)
383 return;
384
385 obj = pc->obj;
386 kunmap(obj->pages[0]);
387 i915_gem_object_unpin(obj);
388 drm_gem_object_unreference(&obj->base);
389
390 kfree(pc);
391 ring->private = NULL;
392 }
393
394 static int init_render_ring(struct intel_ring_buffer *ring)
395 {
396 struct drm_device *dev = ring->dev;
397 struct drm_i915_private *dev_priv = dev->dev_private;
398 int ret = init_ring_common(ring);
399
400 if (INTEL_INFO(dev)->gen > 3) {
401 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
402 if (IS_GEN6(dev) || IS_GEN7(dev))
403 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
404 I915_WRITE(MI_MODE, mode);
405 if (IS_GEN7(dev))
406 I915_WRITE(GFX_MODE_GEN7,
407 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
408 GFX_MODE_ENABLE(GFX_REPLAY_MODE));
409 }
410
411 if (INTEL_INFO(dev)->gen >= 5) {
412 ret = init_pipe_control(ring);
413 if (ret)
414 return ret;
415 }
416
417
418 if (IS_GEN6(dev)) {
419 /* From the Sandybridge PRM, volume 1 part 3, page 24:
420 * "If this bit is set, STCunit will have LRA as replacement
421 * policy. [...] This bit must be reset. LRA replacement
422 * policy is not supported."
423 */
424 I915_WRITE(CACHE_MODE_0,
425 CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
426 }
427
428 if (INTEL_INFO(dev)->gen >= 6) {
429 I915_WRITE(INSTPM,
430 INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
431 }
432
433 return ret;
434 }
435
436 static void render_ring_cleanup(struct intel_ring_buffer *ring)
437 {
438 if (!ring->private)
439 return;
440
441 cleanup_pipe_control(ring);
442 }
443
444 static void
445 update_mboxes(struct intel_ring_buffer *ring,
446 u32 seqno,
447 u32 mmio_offset)
448 {
449 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
450 MI_SEMAPHORE_GLOBAL_GTT |
451 MI_SEMAPHORE_REGISTER |
452 MI_SEMAPHORE_UPDATE);
453 intel_ring_emit(ring, seqno);
454 intel_ring_emit(ring, mmio_offset);
455 }
456
457 /**
458 * gen6_add_request - Update the semaphore mailbox registers
459 *
460 * @ring - ring that is adding a request
461 * @seqno - return seqno stuck into the ring
462 *
463 * Update the mailbox registers in the *other* rings with the current seqno.
464 * This acts like a signal in the canonical semaphore.
465 */
466 static int
467 gen6_add_request(struct intel_ring_buffer *ring,
468 u32 *seqno)
469 {
470 u32 mbox1_reg;
471 u32 mbox2_reg;
472 int ret;
473
474 ret = intel_ring_begin(ring, 10);
475 if (ret)
476 return ret;
477
478 mbox1_reg = ring->signal_mbox[0];
479 mbox2_reg = ring->signal_mbox[1];
480
481 *seqno = i915_gem_get_seqno(ring->dev);
482
483 update_mboxes(ring, *seqno, mbox1_reg);
484 update_mboxes(ring, *seqno, mbox2_reg);
485 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
486 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
487 intel_ring_emit(ring, *seqno);
488 intel_ring_emit(ring, MI_USER_INTERRUPT);
489 intel_ring_advance(ring);
490
491 return 0;
492 }
493
494 /**
495 * intel_ring_sync - sync the waiter to the signaller on seqno
496 *
497 * @waiter - ring that is waiting
498 * @signaller - ring which has, or will signal
499 * @seqno - seqno which the waiter will block on
500 */
501 static int
502 intel_ring_sync(struct intel_ring_buffer *waiter,
503 struct intel_ring_buffer *signaller,
504 int ring,
505 u32 seqno)
506 {
507 int ret;
508 u32 dw1 = MI_SEMAPHORE_MBOX |
509 MI_SEMAPHORE_COMPARE |
510 MI_SEMAPHORE_REGISTER;
511
512 ret = intel_ring_begin(waiter, 4);
513 if (ret)
514 return ret;
515
516 intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
517 intel_ring_emit(waiter, seqno);
518 intel_ring_emit(waiter, 0);
519 intel_ring_emit(waiter, MI_NOOP);
520 intel_ring_advance(waiter);
521
522 return 0;
523 }
524
525 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
526 int
527 render_ring_sync_to(struct intel_ring_buffer *waiter,
528 struct intel_ring_buffer *signaller,
529 u32 seqno)
530 {
531 WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
532 return intel_ring_sync(waiter,
533 signaller,
534 RCS,
535 seqno);
536 }
537
538 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
539 int
540 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
541 struct intel_ring_buffer *signaller,
542 u32 seqno)
543 {
544 WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
545 return intel_ring_sync(waiter,
546 signaller,
547 VCS,
548 seqno);
549 }
550
551 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
552 int
553 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
554 struct intel_ring_buffer *signaller,
555 u32 seqno)
556 {
557 WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
558 return intel_ring_sync(waiter,
559 signaller,
560 BCS,
561 seqno);
562 }
563
564
565
566 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
567 do { \
568 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
569 PIPE_CONTROL_DEPTH_STALL); \
570 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
571 intel_ring_emit(ring__, 0); \
572 intel_ring_emit(ring__, 0); \
573 } while (0)
574
575 static int
576 pc_render_add_request(struct intel_ring_buffer *ring,
577 u32 *result)
578 {
579 struct drm_device *dev = ring->dev;
580 u32 seqno = i915_gem_get_seqno(dev);
581 struct pipe_control *pc = ring->private;
582 u32 scratch_addr = pc->gtt_offset + 128;
583 int ret;
584
585 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
586 * incoherent with writes to memory, i.e. completely fubar,
587 * so we need to use PIPE_NOTIFY instead.
588 *
589 * However, we also need to workaround the qword write
590 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
591 * memory before requesting an interrupt.
592 */
593 ret = intel_ring_begin(ring, 32);
594 if (ret)
595 return ret;
596
597 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
598 PIPE_CONTROL_WRITE_FLUSH |
599 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
600 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
601 intel_ring_emit(ring, seqno);
602 intel_ring_emit(ring, 0);
603 PIPE_CONTROL_FLUSH(ring, scratch_addr);
604 scratch_addr += 128; /* write to separate cachelines */
605 PIPE_CONTROL_FLUSH(ring, scratch_addr);
606 scratch_addr += 128;
607 PIPE_CONTROL_FLUSH(ring, scratch_addr);
608 scratch_addr += 128;
609 PIPE_CONTROL_FLUSH(ring, scratch_addr);
610 scratch_addr += 128;
611 PIPE_CONTROL_FLUSH(ring, scratch_addr);
612 scratch_addr += 128;
613 PIPE_CONTROL_FLUSH(ring, scratch_addr);
614 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
615 PIPE_CONTROL_WRITE_FLUSH |
616 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
617 PIPE_CONTROL_NOTIFY);
618 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
619 intel_ring_emit(ring, seqno);
620 intel_ring_emit(ring, 0);
621 intel_ring_advance(ring);
622
623 *result = seqno;
624 return 0;
625 }
626
627 static int
628 render_ring_add_request(struct intel_ring_buffer *ring,
629 u32 *result)
630 {
631 struct drm_device *dev = ring->dev;
632 u32 seqno = i915_gem_get_seqno(dev);
633 int ret;
634
635 ret = intel_ring_begin(ring, 4);
636 if (ret)
637 return ret;
638
639 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
640 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
641 intel_ring_emit(ring, seqno);
642 intel_ring_emit(ring, MI_USER_INTERRUPT);
643 intel_ring_advance(ring);
644
645 *result = seqno;
646 return 0;
647 }
648
649 static u32
650 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
651 {
652 struct drm_device *dev = ring->dev;
653
654 /* Workaround to force correct ordering between irq and seqno writes on
655 * ivb (and maybe also on snb) by reading from a CS register (like
656 * ACTHD) before reading the status page. */
657 if (IS_GEN7(dev))
658 intel_ring_get_active_head(ring);
659 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
660 }
661
662 static u32
663 ring_get_seqno(struct intel_ring_buffer *ring)
664 {
665 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
666 }
667
668 static u32
669 pc_render_get_seqno(struct intel_ring_buffer *ring)
670 {
671 struct pipe_control *pc = ring->private;
672 return pc->cpu_page[0];
673 }
674
675 static void
676 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
677 {
678 dev_priv->gt_irq_mask &= ~mask;
679 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
680 POSTING_READ(GTIMR);
681 }
682
683 static void
684 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
685 {
686 dev_priv->gt_irq_mask |= mask;
687 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
688 POSTING_READ(GTIMR);
689 }
690
691 static void
692 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
693 {
694 dev_priv->irq_mask &= ~mask;
695 I915_WRITE(IMR, dev_priv->irq_mask);
696 POSTING_READ(IMR);
697 }
698
699 static void
700 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
701 {
702 dev_priv->irq_mask |= mask;
703 I915_WRITE(IMR, dev_priv->irq_mask);
704 POSTING_READ(IMR);
705 }
706
707 static bool
708 render_ring_get_irq(struct intel_ring_buffer *ring)
709 {
710 struct drm_device *dev = ring->dev;
711 drm_i915_private_t *dev_priv = dev->dev_private;
712
713 if (!dev->irq_enabled)
714 return false;
715
716 spin_lock(&ring->irq_lock);
717 if (ring->irq_refcount++ == 0) {
718 if (HAS_PCH_SPLIT(dev))
719 ironlake_enable_irq(dev_priv,
720 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
721 else
722 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
723 }
724 spin_unlock(&ring->irq_lock);
725
726 return true;
727 }
728
729 static void
730 render_ring_put_irq(struct intel_ring_buffer *ring)
731 {
732 struct drm_device *dev = ring->dev;
733 drm_i915_private_t *dev_priv = dev->dev_private;
734
735 spin_lock(&ring->irq_lock);
736 if (--ring->irq_refcount == 0) {
737 if (HAS_PCH_SPLIT(dev))
738 ironlake_disable_irq(dev_priv,
739 GT_USER_INTERRUPT |
740 GT_PIPE_NOTIFY);
741 else
742 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
743 }
744 spin_unlock(&ring->irq_lock);
745 }
746
747 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
748 {
749 struct drm_device *dev = ring->dev;
750 drm_i915_private_t *dev_priv = ring->dev->dev_private;
751 u32 mmio = 0;
752
753 /* The ring status page addresses are no longer next to the rest of
754 * the ring registers as of gen7.
755 */
756 if (IS_GEN7(dev)) {
757 switch (ring->id) {
758 case RING_RENDER:
759 mmio = RENDER_HWS_PGA_GEN7;
760 break;
761 case RING_BLT:
762 mmio = BLT_HWS_PGA_GEN7;
763 break;
764 case RING_BSD:
765 mmio = BSD_HWS_PGA_GEN7;
766 break;
767 }
768 } else if (IS_GEN6(ring->dev)) {
769 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
770 } else {
771 mmio = RING_HWS_PGA(ring->mmio_base);
772 }
773
774 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
775 POSTING_READ(mmio);
776 }
777
778 static int
779 bsd_ring_flush(struct intel_ring_buffer *ring,
780 u32 invalidate_domains,
781 u32 flush_domains)
782 {
783 int ret;
784
785 ret = intel_ring_begin(ring, 2);
786 if (ret)
787 return ret;
788
789 intel_ring_emit(ring, MI_FLUSH);
790 intel_ring_emit(ring, MI_NOOP);
791 intel_ring_advance(ring);
792 return 0;
793 }
794
795 static int
796 ring_add_request(struct intel_ring_buffer *ring,
797 u32 *result)
798 {
799 u32 seqno;
800 int ret;
801
802 ret = intel_ring_begin(ring, 4);
803 if (ret)
804 return ret;
805
806 seqno = i915_gem_get_seqno(ring->dev);
807
808 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
809 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
810 intel_ring_emit(ring, seqno);
811 intel_ring_emit(ring, MI_USER_INTERRUPT);
812 intel_ring_advance(ring);
813
814 *result = seqno;
815 return 0;
816 }
817
818 static bool
819 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
820 {
821 struct drm_device *dev = ring->dev;
822 drm_i915_private_t *dev_priv = dev->dev_private;
823
824 if (!dev->irq_enabled)
825 return false;
826
827 /* It looks like we need to prevent the gt from suspending while waiting
828 * for an notifiy irq, otherwise irqs seem to get lost on at least the
829 * blt/bsd rings on ivb. */
830 if (IS_GEN7(dev))
831 gen6_gt_force_wake_get(dev_priv);
832
833 spin_lock(&ring->irq_lock);
834 if (ring->irq_refcount++ == 0) {
835 ring->irq_mask &= ~rflag;
836 I915_WRITE_IMR(ring, ring->irq_mask);
837 ironlake_enable_irq(dev_priv, gflag);
838 }
839 spin_unlock(&ring->irq_lock);
840
841 return true;
842 }
843
844 static void
845 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
846 {
847 struct drm_device *dev = ring->dev;
848 drm_i915_private_t *dev_priv = dev->dev_private;
849
850 spin_lock(&ring->irq_lock);
851 if (--ring->irq_refcount == 0) {
852 ring->irq_mask |= rflag;
853 I915_WRITE_IMR(ring, ring->irq_mask);
854 ironlake_disable_irq(dev_priv, gflag);
855 }
856 spin_unlock(&ring->irq_lock);
857
858 if (IS_GEN7(dev))
859 gen6_gt_force_wake_put(dev_priv);
860 }
861
862 static bool
863 bsd_ring_get_irq(struct intel_ring_buffer *ring)
864 {
865 struct drm_device *dev = ring->dev;
866 drm_i915_private_t *dev_priv = dev->dev_private;
867
868 if (!dev->irq_enabled)
869 return false;
870
871 spin_lock(&ring->irq_lock);
872 if (ring->irq_refcount++ == 0) {
873 if (IS_G4X(dev))
874 i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
875 else
876 ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
877 }
878 spin_unlock(&ring->irq_lock);
879
880 return true;
881 }
882 static void
883 bsd_ring_put_irq(struct intel_ring_buffer *ring)
884 {
885 struct drm_device *dev = ring->dev;
886 drm_i915_private_t *dev_priv = dev->dev_private;
887
888 spin_lock(&ring->irq_lock);
889 if (--ring->irq_refcount == 0) {
890 if (IS_G4X(dev))
891 i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
892 else
893 ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
894 }
895 spin_unlock(&ring->irq_lock);
896 }
897
898 static int
899 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
900 {
901 int ret;
902
903 ret = intel_ring_begin(ring, 2);
904 if (ret)
905 return ret;
906
907 intel_ring_emit(ring,
908 MI_BATCH_BUFFER_START | (2 << 6) |
909 MI_BATCH_NON_SECURE_I965);
910 intel_ring_emit(ring, offset);
911 intel_ring_advance(ring);
912
913 return 0;
914 }
915
916 static int
917 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
918 u32 offset, u32 len)
919 {
920 struct drm_device *dev = ring->dev;
921 int ret;
922
923 if (IS_I830(dev) || IS_845G(dev)) {
924 ret = intel_ring_begin(ring, 4);
925 if (ret)
926 return ret;
927
928 intel_ring_emit(ring, MI_BATCH_BUFFER);
929 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
930 intel_ring_emit(ring, offset + len - 8);
931 intel_ring_emit(ring, 0);
932 } else {
933 ret = intel_ring_begin(ring, 2);
934 if (ret)
935 return ret;
936
937 if (INTEL_INFO(dev)->gen >= 4) {
938 intel_ring_emit(ring,
939 MI_BATCH_BUFFER_START | (2 << 6) |
940 MI_BATCH_NON_SECURE_I965);
941 intel_ring_emit(ring, offset);
942 } else {
943 intel_ring_emit(ring,
944 MI_BATCH_BUFFER_START | (2 << 6));
945 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
946 }
947 }
948 intel_ring_advance(ring);
949
950 return 0;
951 }
952
953 static void cleanup_status_page(struct intel_ring_buffer *ring)
954 {
955 drm_i915_private_t *dev_priv = ring->dev->dev_private;
956 struct drm_i915_gem_object *obj;
957
958 obj = ring->status_page.obj;
959 if (obj == NULL)
960 return;
961
962 kunmap(obj->pages[0]);
963 i915_gem_object_unpin(obj);
964 drm_gem_object_unreference(&obj->base);
965 ring->status_page.obj = NULL;
966
967 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
968 }
969
970 static int init_status_page(struct intel_ring_buffer *ring)
971 {
972 struct drm_device *dev = ring->dev;
973 drm_i915_private_t *dev_priv = dev->dev_private;
974 struct drm_i915_gem_object *obj;
975 int ret;
976
977 obj = i915_gem_alloc_object(dev, 4096);
978 if (obj == NULL) {
979 DRM_ERROR("Failed to allocate status page\n");
980 ret = -ENOMEM;
981 goto err;
982 }
983
984 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
985
986 ret = i915_gem_object_pin(obj, 4096, true);
987 if (ret != 0) {
988 goto err_unref;
989 }
990
991 ring->status_page.gfx_addr = obj->gtt_offset;
992 ring->status_page.page_addr = kmap(obj->pages[0]);
993 if (ring->status_page.page_addr == NULL) {
994 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
995 goto err_unpin;
996 }
997 ring->status_page.obj = obj;
998 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
999
1000 intel_ring_setup_status_page(ring);
1001 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1002 ring->name, ring->status_page.gfx_addr);
1003
1004 return 0;
1005
1006 err_unpin:
1007 i915_gem_object_unpin(obj);
1008 err_unref:
1009 drm_gem_object_unreference(&obj->base);
1010 err:
1011 return ret;
1012 }
1013
1014 int intel_init_ring_buffer(struct drm_device *dev,
1015 struct intel_ring_buffer *ring)
1016 {
1017 struct drm_i915_gem_object *obj;
1018 int ret;
1019
1020 ring->dev = dev;
1021 INIT_LIST_HEAD(&ring->active_list);
1022 INIT_LIST_HEAD(&ring->request_list);
1023 INIT_LIST_HEAD(&ring->gpu_write_list);
1024
1025 init_waitqueue_head(&ring->irq_queue);
1026 spin_lock_init(&ring->irq_lock);
1027 ring->irq_mask = ~0;
1028
1029 if (I915_NEED_GFX_HWS(dev)) {
1030 ret = init_status_page(ring);
1031 if (ret)
1032 return ret;
1033 }
1034
1035 obj = i915_gem_alloc_object(dev, ring->size);
1036 if (obj == NULL) {
1037 DRM_ERROR("Failed to allocate ringbuffer\n");
1038 ret = -ENOMEM;
1039 goto err_hws;
1040 }
1041
1042 ring->obj = obj;
1043
1044 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1045 if (ret)
1046 goto err_unref;
1047
1048 ring->map.size = ring->size;
1049 ring->map.offset = dev->agp->base + obj->gtt_offset;
1050 ring->map.type = 0;
1051 ring->map.flags = 0;
1052 ring->map.mtrr = 0;
1053
1054 drm_core_ioremap_wc(&ring->map, dev);
1055 if (ring->map.handle == NULL) {
1056 DRM_ERROR("Failed to map ringbuffer.\n");
1057 ret = -EINVAL;
1058 goto err_unpin;
1059 }
1060
1061 ring->virtual_start = ring->map.handle;
1062 ret = ring->init(ring);
1063 if (ret)
1064 goto err_unmap;
1065
1066 /* Workaround an erratum on the i830 which causes a hang if
1067 * the TAIL pointer points to within the last 2 cachelines
1068 * of the buffer.
1069 */
1070 ring->effective_size = ring->size;
1071 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1072 ring->effective_size -= 128;
1073
1074 return 0;
1075
1076 err_unmap:
1077 drm_core_ioremapfree(&ring->map, dev);
1078 err_unpin:
1079 i915_gem_object_unpin(obj);
1080 err_unref:
1081 drm_gem_object_unreference(&obj->base);
1082 ring->obj = NULL;
1083 err_hws:
1084 cleanup_status_page(ring);
1085 return ret;
1086 }
1087
1088 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1089 {
1090 struct drm_i915_private *dev_priv;
1091 int ret;
1092
1093 if (ring->obj == NULL)
1094 return;
1095
1096 /* Disable the ring buffer. The ring must be idle at this point */
1097 dev_priv = ring->dev->dev_private;
1098 ret = intel_wait_ring_idle(ring);
1099 if (ret)
1100 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1101 ring->name, ret);
1102
1103 I915_WRITE_CTL(ring, 0);
1104
1105 drm_core_ioremapfree(&ring->map, ring->dev);
1106
1107 i915_gem_object_unpin(ring->obj);
1108 drm_gem_object_unreference(&ring->obj->base);
1109 ring->obj = NULL;
1110
1111 if (ring->cleanup)
1112 ring->cleanup(ring);
1113
1114 cleanup_status_page(ring);
1115 }
1116
1117 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1118 {
1119 unsigned int *virt;
1120 int rem = ring->size - ring->tail;
1121
1122 if (ring->space < rem) {
1123 int ret = intel_wait_ring_buffer(ring, rem);
1124 if (ret)
1125 return ret;
1126 }
1127
1128 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1129 rem /= 8;
1130 while (rem--) {
1131 *virt++ = MI_NOOP;
1132 *virt++ = MI_NOOP;
1133 }
1134
1135 ring->tail = 0;
1136 ring->space = ring_space(ring);
1137
1138 return 0;
1139 }
1140
1141 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1142 {
1143 struct drm_device *dev = ring->dev;
1144 struct drm_i915_private *dev_priv = dev->dev_private;
1145 unsigned long end;
1146
1147 trace_i915_ring_wait_begin(ring);
1148 if (drm_core_check_feature(dev, DRIVER_GEM))
1149 /* With GEM the hangcheck timer should kick us out of the loop,
1150 * leaving it early runs the risk of corrupting GEM state (due
1151 * to running on almost untested codepaths). But on resume
1152 * timers don't work yet, so prevent a complete hang in that
1153 * case by choosing an insanely large timeout. */
1154 end = jiffies + 60 * HZ;
1155 else
1156 end = jiffies + 3 * HZ;
1157
1158 do {
1159 ring->head = I915_READ_HEAD(ring);
1160 ring->space = ring_space(ring);
1161 if (ring->space >= n) {
1162 trace_i915_ring_wait_end(ring);
1163 return 0;
1164 }
1165
1166 if (dev->primary->master) {
1167 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1168 if (master_priv->sarea_priv)
1169 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1170 }
1171
1172 msleep(1);
1173 if (atomic_read(&dev_priv->mm.wedged))
1174 return -EAGAIN;
1175 } while (!time_after(jiffies, end));
1176 trace_i915_ring_wait_end(ring);
1177 return -EBUSY;
1178 }
1179
1180 int intel_ring_begin(struct intel_ring_buffer *ring,
1181 int num_dwords)
1182 {
1183 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1184 int n = 4*num_dwords;
1185 int ret;
1186
1187 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1188 return -EIO;
1189
1190 if (unlikely(ring->tail + n > ring->effective_size)) {
1191 ret = intel_wrap_ring_buffer(ring);
1192 if (unlikely(ret))
1193 return ret;
1194 }
1195
1196 if (unlikely(ring->space < n)) {
1197 ret = intel_wait_ring_buffer(ring, n);
1198 if (unlikely(ret))
1199 return ret;
1200 }
1201
1202 ring->space -= n;
1203 return 0;
1204 }
1205
1206 void intel_ring_advance(struct intel_ring_buffer *ring)
1207 {
1208 ring->tail &= ring->size - 1;
1209 ring->write_tail(ring, ring->tail);
1210 }
1211
1212 static const struct intel_ring_buffer render_ring = {
1213 .name = "render ring",
1214 .id = RING_RENDER,
1215 .mmio_base = RENDER_RING_BASE,
1216 .size = 32 * PAGE_SIZE,
1217 .init = init_render_ring,
1218 .write_tail = ring_write_tail,
1219 .flush = render_ring_flush,
1220 .add_request = render_ring_add_request,
1221 .get_seqno = ring_get_seqno,
1222 .irq_get = render_ring_get_irq,
1223 .irq_put = render_ring_put_irq,
1224 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1225 .cleanup = render_ring_cleanup,
1226 .sync_to = render_ring_sync_to,
1227 .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID,
1228 MI_SEMAPHORE_SYNC_RV,
1229 MI_SEMAPHORE_SYNC_RB},
1230 .signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC},
1231 };
1232
1233 /* ring buffer for bit-stream decoder */
1234
1235 static const struct intel_ring_buffer bsd_ring = {
1236 .name = "bsd ring",
1237 .id = RING_BSD,
1238 .mmio_base = BSD_RING_BASE,
1239 .size = 32 * PAGE_SIZE,
1240 .init = init_ring_common,
1241 .write_tail = ring_write_tail,
1242 .flush = bsd_ring_flush,
1243 .add_request = ring_add_request,
1244 .get_seqno = ring_get_seqno,
1245 .irq_get = bsd_ring_get_irq,
1246 .irq_put = bsd_ring_put_irq,
1247 .dispatch_execbuffer = ring_dispatch_execbuffer,
1248 };
1249
1250
1251 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1252 u32 value)
1253 {
1254 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1255
1256 /* Every tail move must follow the sequence below */
1257 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1258 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1259 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1260 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1261
1262 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1263 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1264 50))
1265 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1266
1267 I915_WRITE_TAIL(ring, value);
1268 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1269 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1270 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1271 }
1272
1273 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1274 u32 invalidate, u32 flush)
1275 {
1276 uint32_t cmd;
1277 int ret;
1278
1279 ret = intel_ring_begin(ring, 4);
1280 if (ret)
1281 return ret;
1282
1283 cmd = MI_FLUSH_DW;
1284 if (invalidate & I915_GEM_GPU_DOMAINS)
1285 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1286 intel_ring_emit(ring, cmd);
1287 intel_ring_emit(ring, 0);
1288 intel_ring_emit(ring, 0);
1289 intel_ring_emit(ring, MI_NOOP);
1290 intel_ring_advance(ring);
1291 return 0;
1292 }
1293
1294 static int
1295 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1296 u32 offset, u32 len)
1297 {
1298 int ret;
1299
1300 ret = intel_ring_begin(ring, 2);
1301 if (ret)
1302 return ret;
1303
1304 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1305 /* bit0-7 is the length on GEN6+ */
1306 intel_ring_emit(ring, offset);
1307 intel_ring_advance(ring);
1308
1309 return 0;
1310 }
1311
1312 static bool
1313 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1314 {
1315 return gen6_ring_get_irq(ring,
1316 GT_USER_INTERRUPT,
1317 GEN6_RENDER_USER_INTERRUPT);
1318 }
1319
1320 static void
1321 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1322 {
1323 return gen6_ring_put_irq(ring,
1324 GT_USER_INTERRUPT,
1325 GEN6_RENDER_USER_INTERRUPT);
1326 }
1327
1328 static bool
1329 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1330 {
1331 return gen6_ring_get_irq(ring,
1332 GT_GEN6_BSD_USER_INTERRUPT,
1333 GEN6_BSD_USER_INTERRUPT);
1334 }
1335
1336 static void
1337 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1338 {
1339 return gen6_ring_put_irq(ring,
1340 GT_GEN6_BSD_USER_INTERRUPT,
1341 GEN6_BSD_USER_INTERRUPT);
1342 }
1343
1344 /* ring buffer for Video Codec for Gen6+ */
1345 static const struct intel_ring_buffer gen6_bsd_ring = {
1346 .name = "gen6 bsd ring",
1347 .id = RING_BSD,
1348 .mmio_base = GEN6_BSD_RING_BASE,
1349 .size = 32 * PAGE_SIZE,
1350 .init = init_ring_common,
1351 .write_tail = gen6_bsd_ring_write_tail,
1352 .flush = gen6_ring_flush,
1353 .add_request = gen6_add_request,
1354 .get_seqno = gen6_ring_get_seqno,
1355 .irq_get = gen6_bsd_ring_get_irq,
1356 .irq_put = gen6_bsd_ring_put_irq,
1357 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1358 .sync_to = gen6_bsd_ring_sync_to,
1359 .semaphore_register = {MI_SEMAPHORE_SYNC_VR,
1360 MI_SEMAPHORE_SYNC_INVALID,
1361 MI_SEMAPHORE_SYNC_VB},
1362 .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC},
1363 };
1364
1365 /* Blitter support (SandyBridge+) */
1366
1367 static bool
1368 blt_ring_get_irq(struct intel_ring_buffer *ring)
1369 {
1370 return gen6_ring_get_irq(ring,
1371 GT_BLT_USER_INTERRUPT,
1372 GEN6_BLITTER_USER_INTERRUPT);
1373 }
1374
1375 static void
1376 blt_ring_put_irq(struct intel_ring_buffer *ring)
1377 {
1378 gen6_ring_put_irq(ring,
1379 GT_BLT_USER_INTERRUPT,
1380 GEN6_BLITTER_USER_INTERRUPT);
1381 }
1382
1383
1384 /* Workaround for some stepping of SNB,
1385 * each time when BLT engine ring tail moved,
1386 * the first command in the ring to be parsed
1387 * should be MI_BATCH_BUFFER_START
1388 */
1389 #define NEED_BLT_WORKAROUND(dev) \
1390 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1391
1392 static inline struct drm_i915_gem_object *
1393 to_blt_workaround(struct intel_ring_buffer *ring)
1394 {
1395 return ring->private;
1396 }
1397
1398 static int blt_ring_init(struct intel_ring_buffer *ring)
1399 {
1400 if (NEED_BLT_WORKAROUND(ring->dev)) {
1401 struct drm_i915_gem_object *obj;
1402 u32 *ptr;
1403 int ret;
1404
1405 obj = i915_gem_alloc_object(ring->dev, 4096);
1406 if (obj == NULL)
1407 return -ENOMEM;
1408
1409 ret = i915_gem_object_pin(obj, 4096, true);
1410 if (ret) {
1411 drm_gem_object_unreference(&obj->base);
1412 return ret;
1413 }
1414
1415 ptr = kmap(obj->pages[0]);
1416 *ptr++ = MI_BATCH_BUFFER_END;
1417 *ptr++ = MI_NOOP;
1418 kunmap(obj->pages[0]);
1419
1420 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1421 if (ret) {
1422 i915_gem_object_unpin(obj);
1423 drm_gem_object_unreference(&obj->base);
1424 return ret;
1425 }
1426
1427 ring->private = obj;
1428 }
1429
1430 return init_ring_common(ring);
1431 }
1432
1433 static int blt_ring_begin(struct intel_ring_buffer *ring,
1434 int num_dwords)
1435 {
1436 if (ring->private) {
1437 int ret = intel_ring_begin(ring, num_dwords+2);
1438 if (ret)
1439 return ret;
1440
1441 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1442 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1443
1444 return 0;
1445 } else
1446 return intel_ring_begin(ring, 4);
1447 }
1448
1449 static int blt_ring_flush(struct intel_ring_buffer *ring,
1450 u32 invalidate, u32 flush)
1451 {
1452 uint32_t cmd;
1453 int ret;
1454
1455 ret = blt_ring_begin(ring, 4);
1456 if (ret)
1457 return ret;
1458
1459 cmd = MI_FLUSH_DW;
1460 if (invalidate & I915_GEM_DOMAIN_RENDER)
1461 cmd |= MI_INVALIDATE_TLB;
1462 intel_ring_emit(ring, cmd);
1463 intel_ring_emit(ring, 0);
1464 intel_ring_emit(ring, 0);
1465 intel_ring_emit(ring, MI_NOOP);
1466 intel_ring_advance(ring);
1467 return 0;
1468 }
1469
1470 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1471 {
1472 if (!ring->private)
1473 return;
1474
1475 i915_gem_object_unpin(ring->private);
1476 drm_gem_object_unreference(ring->private);
1477 ring->private = NULL;
1478 }
1479
1480 static const struct intel_ring_buffer gen6_blt_ring = {
1481 .name = "blt ring",
1482 .id = RING_BLT,
1483 .mmio_base = BLT_RING_BASE,
1484 .size = 32 * PAGE_SIZE,
1485 .init = blt_ring_init,
1486 .write_tail = ring_write_tail,
1487 .flush = blt_ring_flush,
1488 .add_request = gen6_add_request,
1489 .get_seqno = gen6_ring_get_seqno,
1490 .irq_get = blt_ring_get_irq,
1491 .irq_put = blt_ring_put_irq,
1492 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1493 .cleanup = blt_ring_cleanup,
1494 .sync_to = gen6_blt_ring_sync_to,
1495 .semaphore_register = {MI_SEMAPHORE_SYNC_BR,
1496 MI_SEMAPHORE_SYNC_BV,
1497 MI_SEMAPHORE_SYNC_INVALID},
1498 .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC},
1499 };
1500
1501 int intel_init_render_ring_buffer(struct drm_device *dev)
1502 {
1503 drm_i915_private_t *dev_priv = dev->dev_private;
1504 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1505
1506 *ring = render_ring;
1507 if (INTEL_INFO(dev)->gen >= 6) {
1508 ring->add_request = gen6_add_request;
1509 ring->flush = gen6_render_ring_flush;
1510 ring->irq_get = gen6_render_ring_get_irq;
1511 ring->irq_put = gen6_render_ring_put_irq;
1512 ring->get_seqno = gen6_ring_get_seqno;
1513 } else if (IS_GEN5(dev)) {
1514 ring->add_request = pc_render_add_request;
1515 ring->get_seqno = pc_render_get_seqno;
1516 }
1517
1518 if (!I915_NEED_GFX_HWS(dev)) {
1519 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1520 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1521 }
1522
1523 return intel_init_ring_buffer(dev, ring);
1524 }
1525
1526 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1527 {
1528 drm_i915_private_t *dev_priv = dev->dev_private;
1529 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1530
1531 *ring = render_ring;
1532 if (INTEL_INFO(dev)->gen >= 6) {
1533 ring->add_request = gen6_add_request;
1534 ring->irq_get = gen6_render_ring_get_irq;
1535 ring->irq_put = gen6_render_ring_put_irq;
1536 } else if (IS_GEN5(dev)) {
1537 ring->add_request = pc_render_add_request;
1538 ring->get_seqno = pc_render_get_seqno;
1539 }
1540
1541 if (!I915_NEED_GFX_HWS(dev))
1542 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1543
1544 ring->dev = dev;
1545 INIT_LIST_HEAD(&ring->active_list);
1546 INIT_LIST_HEAD(&ring->request_list);
1547 INIT_LIST_HEAD(&ring->gpu_write_list);
1548
1549 ring->size = size;
1550 ring->effective_size = ring->size;
1551 if (IS_I830(ring->dev))
1552 ring->effective_size -= 128;
1553
1554 ring->map.offset = start;
1555 ring->map.size = size;
1556 ring->map.type = 0;
1557 ring->map.flags = 0;
1558 ring->map.mtrr = 0;
1559
1560 drm_core_ioremap_wc(&ring->map, dev);
1561 if (ring->map.handle == NULL) {
1562 DRM_ERROR("can not ioremap virtual address for"
1563 " ring buffer\n");
1564 return -ENOMEM;
1565 }
1566
1567 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1568 return 0;
1569 }
1570
1571 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1572 {
1573 drm_i915_private_t *dev_priv = dev->dev_private;
1574 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1575
1576 if (IS_GEN6(dev) || IS_GEN7(dev))
1577 *ring = gen6_bsd_ring;
1578 else
1579 *ring = bsd_ring;
1580
1581 return intel_init_ring_buffer(dev, ring);
1582 }
1583
1584 int intel_init_blt_ring_buffer(struct drm_device *dev)
1585 {
1586 drm_i915_private_t *dev_priv = dev->dev_private;
1587 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1588
1589 *ring = gen6_blt_ring;
1590
1591 return intel_init_ring_buffer(dev, ring);
1592 }