2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #ifndef __ASM_ARCH_MXC_IRQS_H__
12 #define __ASM_ARCH_MXC_IRQS_H__
14 #include <asm-generic/gpio.h>
17 * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
18 * have 128 IRQs, and those with AVIC have 64.
20 * To support single image, the biggest number should be defined on
23 #if defined CONFIG_ARM_GIC
24 #define MXC_INTERNAL_IRQS 160
25 #elif defined CONFIG_MXC_TZIC
26 #define MXC_INTERNAL_IRQS 128
28 #define MXC_INTERNAL_IRQS 64
31 #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
34 * The next 16 interrupts are for board specific purposes. Since
35 * the kernel can only run on one machine at a time, we can re-use
36 * these. If you need more, increase MXC_BOARD_IRQS, but keep it
37 * within sensible limits.
39 #define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
41 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
42 #define MXC_BOARD_IRQS 80
44 #define MXC_BOARD_IRQS 16
47 #define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
49 #ifdef CONFIG_MX3_IPU_IRQS
50 #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
52 #define MX3_IPU_IRQS 0
54 /* REVISIT: Add IPU irqs on IMX51 */
56 #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
58 extern int imx_irq_set_priority(unsigned char irq
, unsigned char prio
);
60 /* all normal IRQs can be FIQs */
62 /* switch between IRQ and FIQ */
63 extern int mxc_set_irq_fiq(unsigned int irq
, unsigned int type
);
65 #endif /* __ASM_ARCH_MXC_IRQS_H__ */