2 * linux/arch/arm/plat-mxc/time.c
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/clockchips.h>
27 #include <linux/clk.h>
29 #include <mach/hardware.h>
30 #include <asm/sched_clock.h>
31 #include <asm/mach/time.h>
32 #include <mach/common.h>
35 * There are 2 versions of the timer hardware on Freescale MXC hardware.
36 * Version 1: MX1/MXL, MX21, MX27.
37 * Version 2: MX25, MX31, MX35, MX37, MX51
40 /* defines common for all i.MX */
42 #define MXC_TCTL_TEN (1 << 0) /* Enable module */
43 #define MXC_TPRER 0x04
46 #define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
47 #define MX1_2_TCTL_IRQEN (1 << 4)
48 #define MX1_2_TCTL_FRR (1 << 8)
49 #define MX1_2_TCMP 0x08
50 #define MX1_2_TCN 0x10
51 #define MX1_2_TSTAT 0x14
54 #define MX2_TSTAT_CAPT (1 << 1)
55 #define MX2_TSTAT_COMP (1 << 0)
57 /* MX31, MX35, MX25, MX5 */
58 #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
59 #define V2_TCTL_CLK_IPG (1 << 6)
60 #define V2_TCTL_FRR (1 << 9)
63 #define V2_TSTAT_OF1 (1 << 0)
67 #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
68 #define timer_is_v2() (!timer_is_v1())
70 static struct clock_event_device clockevent_mxc
;
71 static enum clock_event_mode clockevent_mode
= CLOCK_EVT_MODE_UNUSED
;
73 static void __iomem
*timer_base
;
75 static inline void gpt_irq_disable(void)
80 __raw_writel(0, timer_base
+ V2_IR
);
82 tmp
= __raw_readl(timer_base
+ MXC_TCTL
);
83 __raw_writel(tmp
& ~MX1_2_TCTL_IRQEN
, timer_base
+ MXC_TCTL
);
87 static inline void gpt_irq_enable(void)
90 __raw_writel(1<<0, timer_base
+ V2_IR
);
92 __raw_writel(__raw_readl(timer_base
+ MXC_TCTL
) | MX1_2_TCTL_IRQEN
,
93 timer_base
+ MXC_TCTL
);
97 static void gpt_irq_acknowledge(void)
101 __raw_writel(0, timer_base
+ MX1_2_TSTAT
);
103 __raw_writel(MX2_TSTAT_CAPT
| MX2_TSTAT_COMP
,
104 timer_base
+ MX1_2_TSTAT
);
105 } else if (timer_is_v2())
106 __raw_writel(V2_TSTAT_OF1
, timer_base
+ V2_TSTAT
);
109 static void __iomem
*sched_clock_reg
;
111 static u32 notrace
mxc_read_sched_clock(void)
113 return sched_clock_reg
? __raw_readl(sched_clock_reg
) : 0;
116 static int __init
mxc_clocksource_init(struct clk
*timer_clk
)
118 unsigned int c
= clk_get_rate(timer_clk
);
119 void __iomem
*reg
= timer_base
+ (timer_is_v2() ? V2_TCN
: MX1_2_TCN
);
121 sched_clock_reg
= reg
;
123 setup_sched_clock(mxc_read_sched_clock
, 32, c
);
124 return clocksource_mmio_init(reg
, "mxc_timer1", c
, 200, 32,
125 clocksource_mmio_readl_up
);
130 static int mx1_2_set_next_event(unsigned long evt
,
131 struct clock_event_device
*unused
)
135 tcmp
= __raw_readl(timer_base
+ MX1_2_TCN
) + evt
;
137 __raw_writel(tcmp
, timer_base
+ MX1_2_TCMP
);
139 return (int)(tcmp
- __raw_readl(timer_base
+ MX1_2_TCN
)) < 0 ?
143 static int v2_set_next_event(unsigned long evt
,
144 struct clock_event_device
*unused
)
148 tcmp
= __raw_readl(timer_base
+ V2_TCN
) + evt
;
150 __raw_writel(tcmp
, timer_base
+ V2_TCMP
);
152 return (int)(tcmp
- __raw_readl(timer_base
+ V2_TCN
)) < 0 ?
157 static const char *clock_event_mode_label
[] = {
158 [CLOCK_EVT_MODE_PERIODIC
] = "CLOCK_EVT_MODE_PERIODIC",
159 [CLOCK_EVT_MODE_ONESHOT
] = "CLOCK_EVT_MODE_ONESHOT",
160 [CLOCK_EVT_MODE_SHUTDOWN
] = "CLOCK_EVT_MODE_SHUTDOWN",
161 [CLOCK_EVT_MODE_UNUSED
] = "CLOCK_EVT_MODE_UNUSED"
165 static void mxc_set_mode(enum clock_event_mode mode
,
166 struct clock_event_device
*evt
)
171 * The timer interrupt generation is disabled at least
172 * for enough time to call mxc_set_next_event()
174 local_irq_save(flags
);
176 /* Disable interrupt in GPT module */
179 if (mode
!= clockevent_mode
) {
180 /* Set event time into far-far future */
182 __raw_writel(__raw_readl(timer_base
+ V2_TCN
) - 3,
183 timer_base
+ V2_TCMP
);
185 __raw_writel(__raw_readl(timer_base
+ MX1_2_TCN
) - 3,
186 timer_base
+ MX1_2_TCMP
);
188 /* Clear pending interrupt */
189 gpt_irq_acknowledge();
193 printk(KERN_INFO
"mxc_set_mode: changing mode from %s to %s\n",
194 clock_event_mode_label
[clockevent_mode
],
195 clock_event_mode_label
[mode
]);
198 /* Remember timer mode */
199 clockevent_mode
= mode
;
200 local_irq_restore(flags
);
203 case CLOCK_EVT_MODE_PERIODIC
:
204 printk(KERN_ERR
"mxc_set_mode: Periodic mode is not "
205 "supported for i.MX\n");
207 case CLOCK_EVT_MODE_ONESHOT
:
209 * Do not put overhead of interrupt enable/disable into
210 * mxc_set_next_event(), the core has about 4 minutes
211 * to call mxc_set_next_event() or shutdown clock after
214 local_irq_save(flags
);
216 local_irq_restore(flags
);
218 case CLOCK_EVT_MODE_SHUTDOWN
:
219 case CLOCK_EVT_MODE_UNUSED
:
220 case CLOCK_EVT_MODE_RESUME
:
221 /* Left event sources disabled, no more interrupts appear */
227 * IRQ handler for the timer
229 static irqreturn_t
mxc_timer_interrupt(int irq
, void *dev_id
)
231 struct clock_event_device
*evt
= &clockevent_mxc
;
235 tstat
= __raw_readl(timer_base
+ V2_TSTAT
);
237 tstat
= __raw_readl(timer_base
+ MX1_2_TSTAT
);
239 gpt_irq_acknowledge();
241 evt
->event_handler(evt
);
246 static struct irqaction mxc_timer_irq
= {
247 .name
= "i.MX Timer Tick",
248 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
249 .handler
= mxc_timer_interrupt
,
252 static struct clock_event_device clockevent_mxc
= {
253 .name
= "mxc_timer1",
254 .features
= CLOCK_EVT_FEAT_ONESHOT
,
256 .set_mode
= mxc_set_mode
,
257 .set_next_event
= mx1_2_set_next_event
,
261 static int __init
mxc_clockevent_init(struct clk
*timer_clk
)
263 unsigned int c
= clk_get_rate(timer_clk
);
266 clockevent_mxc
.set_next_event
= v2_set_next_event
;
268 clockevent_mxc
.mult
= div_sc(c
, NSEC_PER_SEC
,
269 clockevent_mxc
.shift
);
270 clockevent_mxc
.max_delta_ns
=
271 clockevent_delta2ns(0xfffffffe, &clockevent_mxc
);
272 clockevent_mxc
.min_delta_ns
=
273 clockevent_delta2ns(0xff, &clockevent_mxc
);
275 clockevent_mxc
.cpumask
= cpumask_of(0);
277 clockevents_register_device(&clockevent_mxc
);
282 void __init
mxc_timer_init(struct clk
*timer_clk
, void __iomem
*base
, int irq
)
286 clk_enable(timer_clk
);
291 * Initialise to a known state (all timers off, and timing reset)
294 __raw_writel(0, timer_base
+ MXC_TCTL
);
295 __raw_writel(0, timer_base
+ MXC_TPRER
); /* see datasheet note */
298 tctl_val
= V2_TCTL_CLK_IPG
| V2_TCTL_FRR
| V2_TCTL_WAITEN
| MXC_TCTL_TEN
;
300 tctl_val
= MX1_2_TCTL_FRR
| MX1_2_TCTL_CLK_PCLK1
| MXC_TCTL_TEN
;
302 __raw_writel(tctl_val
, timer_base
+ MXC_TCTL
);
304 /* init and register the timer to the framework */
305 mxc_clocksource_init(timer_clk
);
306 mxc_clockevent_init(timer_clk
);
308 /* Make irqs happen */
309 setup_irq(irq
, &mxc_timer_irq
);