arch/cris/arch-v32/kernel/time.c

   1 /*
   2  *  linux/arch/cris/arch-v32/kernel/time.c
   3  *
   4  *  Copyright (C) 2003-2010 Axis Communications AB
   5  *
   6  */
   7
   8 #include <linux/timex.h>
   9 #include <linux/time.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/swap.h>
  13 #include <linux/sched.h>
  14 #include <linux/init.h>
  15 #include <linux/threads.h>
  16 #include <linux/cpufreq.h>
  17 #include <asm/types.h>
  18 #include <asm/signal.h>
  19 #include <asm/io.h>
  20 #include <asm/delay.h>
  21 #include <asm/rtc.h>
  22 #include <asm/irq.h>
  23 #include <asm/irq_regs.h>
  24
  25 #include <hwregs/reg_map.h>
  26 #include <hwregs/reg_rdwr.h>
  27 #include <hwregs/timer_defs.h>
  28 #include <hwregs/intr_vect_defs.h>
  29 #ifdef CONFIG_CRIS_MACH_ARTPEC3
  30 #include <hwregs/clkgen_defs.h>
  31 #endif
  32
  33 /* Watchdog defines */
  34 #define ETRAX_WD_KEY_MASK       0x7F /* key is 7 bit */
  35 #define ETRAX_WD_HZ             763 /* watchdog counts at 763 Hz */
  36 /* Number of 763 counts before watchdog bites */
  37 #define ETRAX_WD_CNT            ((2*ETRAX_WD_HZ)/HZ + 1)
  38
  39 /* Register the continuos readonly timer available in FS and ARTPEC-3.  */
  40 static cycle_t read_cont_rotime(struct clocksource *cs)
  41 {
  42         return (u32)REG_RD(timer, regi_timer0, r_time);
  43 }
  44
  45 static struct clocksource cont_rotime = {
  46         .name   = "crisv32_rotime",
  47         .rating = 300,
  48         .read   = read_cont_rotime,
  49         .mask   = CLOCKSOURCE_MASK(32),
  50         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
  51 };
  52
  53 static int __init etrax_init_cont_rotime(void)
  54 {
  55         clocksource_register_khz(&cont_rotime, 100000);
  56         return 0;
  57 }
  58 arch_initcall(etrax_init_cont_rotime);
  59
  60
  61 unsigned long timer_regs[NR_CPUS] =
  62 {
  63         regi_timer0,
  64 #ifdef CONFIG_SMP
  65         regi_timer2
  66 #endif
  67 };
  68
  69 extern int set_rtc_mmss(unsigned long nowtime);
  70 extern int have_rtc;
  71
  72 #ifdef CONFIG_CPU_FREQ
  73 static int
  74 cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
  75                         void *data);
  76
  77 static struct notifier_block cris_time_freq_notifier_block = {
  78         .notifier_call = cris_time_freq_notifier,
  79 };
  80 #endif
  81
  82 unsigned long get_ns_in_jiffie(void)
  83 {
  84         reg_timer_r_tmr0_data data;
  85         unsigned long ns;
  86
  87         data = REG_RD(timer, regi_timer0, r_tmr0_data);
  88         ns = (TIMER0_DIV - data) * 10;
  89         return ns;
  90 }
  91
  92
  93 /* From timer MDS describing the hardware watchdog:
  94  * 4.3.1 Watchdog Operation
  95  * The watchdog timer is an 8-bit timer with a configurable start value.
  96  * Once started the watchdog counts downwards with a frequency of 763 Hz
  97  * (100/131072 MHz). When the watchdog counts down to 1, it generates an
  98  * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
  99  * chip.
 100  */
 101 /* This gives us 1.3 ms to do something useful when the NMI comes */
 102
 103 /* Right now, starting the watchdog is the same as resetting it */
 104 #define start_watchdog reset_watchdog
 105
 106 #if defined(CONFIG_ETRAX_WATCHDOG)
 107 static short int watchdog_key = 42;  /* arbitrary 7 bit number */
 108 #endif
 109
 110 /* Number of pages to consider "out of memory". It is normal that the memory
 111  * is used though, so set this really low. */
 112 #define WATCHDOG_MIN_FREE_PAGES 8
 113
 114 void reset_watchdog(void)
 115 {
 116 #if defined(CONFIG_ETRAX_WATCHDOG)
 117         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 118
 119         /* Only keep watchdog happy as long as we have memory left! */
 120         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 121                 /* Reset the watchdog with the inverse of the old key */
 122                 /* Invert key, which is 7 bits */
 123                 watchdog_key ^= ETRAX_WD_KEY_MASK;
 124                 wd_ctrl.cnt = ETRAX_WD_CNT;
 125                 wd_ctrl.cmd = regk_timer_start;
 126                 wd_ctrl.key = watchdog_key;
 127                 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 128         }
 129 #endif
 130 }
 131
 132 /* stop the watchdog - we still need the correct key */
 133
 134 void stop_watchdog(void)
 135 {
 136 #if defined(CONFIG_ETRAX_WATCHDOG)
 137         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 138         watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
 139         wd_ctrl.cnt = ETRAX_WD_CNT;
 140         wd_ctrl.cmd = regk_timer_stop;
 141         wd_ctrl.key = watchdog_key;
 142         REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 143 #endif
 144 }
 145
 146 extern void show_registers(struct pt_regs *regs);
 147
 148 void handle_watchdog_bite(struct pt_regs *regs)
 149 {
 150 #if defined(CONFIG_ETRAX_WATCHDOG)
 151         extern int cause_of_death;
 152
 153         oops_in_progress = 1;
 154         printk(KERN_WARNING "Watchdog bite\n");
 155
 156         /* Check if forced restart or unexpected watchdog */
 157         if (cause_of_death == 0xbedead) {
 158 #ifdef CONFIG_CRIS_MACH_ARTPEC3
 159                 /* There is a bug in Artpec-3 (voodoo TR 78) that requires
 160                  * us to go to lower frequency for the reset to be reliable
 161                  */
 162                 reg_clkgen_rw_clk_ctrl ctrl =
 163                         REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
 164                 ctrl.pll = 0;
 165                 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
 166 #endif
 167                 while(1);
 168         }
 169
 170         /* Unexpected watchdog, stop the watchdog and dump registers. */
 171         stop_watchdog();
 172         printk(KERN_WARNING "Oops: bitten by watchdog\n");
 173         show_registers(regs);
 174         oops_in_progress = 0;
 175 #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
 176         reset_watchdog();
 177 #endif
 178         while(1) /* nothing */;
 179 #endif
 180 }
 181
 182 /*
 183  * timer_interrupt() needs to keep up the real-time clock,
 184  * as well as call the "xtime_update()" routine every clocktick.
 185  */
 186 extern void cris_do_profile(struct pt_regs *regs);
 187
 188 static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
 189 {
 190         struct pt_regs *regs = get_irq_regs();
 191         int cpu = smp_processor_id();
 192         reg_timer_r_masked_intr masked_intr;
 193         reg_timer_rw_ack_intr ack_intr = { 0 };
 194
 195         /* Check if the timer interrupt is for us (a tmr0 int) */
 196         masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
 197         if (!masked_intr.tmr0)
 198                 return IRQ_NONE;
 199
 200         /* Acknowledge the timer irq. */
 201         ack_intr.tmr0 = 1;
 202         REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
 203
 204         /* Reset watchdog otherwise it resets us! */
 205         reset_watchdog();
 206
 207         /* Update statistics. */
 208         update_process_times(user_mode(regs));
 209
 210         cris_do_profile(regs); /* Save profiling information */
 211
 212         /* The master CPU is responsible for the time keeping. */
 213         if (cpu != 0)
 214                 return IRQ_HANDLED;
 215
 216         /* Call the real timer interrupt handler */
 217         xtime_update(1);
 218         return IRQ_HANDLED;
 219 }
 220
 221 /* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain.
 222  * It needs to be IRQF_DISABLED to make the jiffies update work properly.
 223  */
 224 static struct irqaction irq_timer = {
 225         .handler = timer_interrupt,
 226         .flags = IRQF_SHARED | IRQF_DISABLED,
 227         .name = "timer"
 228 };
 229
 230 void __init cris_timer_init(void)
 231 {
 232         int cpu = smp_processor_id();
 233         reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
 234         reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
 235         reg_timer_rw_intr_mask timer_intr_mask;
 236
 237         /* Setup the etrax timers.
 238          * Base frequency is 100MHz, divider 1000000 -> 100 HZ
 239          * We use timer0, so timer1 is free.
 240          * The trig timer is used by the fasttimer API if enabled.
 241          */
 242
 243         tmr0_ctrl.op = regk_timer_ld;
 244         tmr0_ctrl.freq = regk_timer_f100;
 245         REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
 246         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
 247         tmr0_ctrl.op = regk_timer_run;
 248         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
 249
 250         /* Enable the timer irq. */
 251         timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
 252         timer_intr_mask.tmr0 = 1;
 253         REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
 254 }
 255
 256 void __init time_init(void)
 257 {
 258         reg_intr_vect_rw_mask intr_mask;
 259
 260         /* Probe for the RTC and read it if it exists.
 261          * Before the RTC can be probed the loops_per_usec variable needs
 262          * to be initialized to make usleep work. A better value for
 263          * loops_per_usec is calculated by the kernel later once the
 264          * clock has started.
 265          */
 266         loops_per_usec = 50;
 267
 268         if(RTC_INIT() < 0)
 269                 have_rtc = 0;
 270         else
 271                 have_rtc = 1;
 272
 273         /* Start CPU local timer. */
 274         cris_timer_init();
 275
 276         /* Enable the timer irq in global config. */
 277         intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
 278         intr_mask.timer0 = 1;
 279         REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
 280
 281         /* Now actually register the timer irq handler that calls
 282          * timer_interrupt(). */
 283         setup_irq(TIMER0_INTR_VECT, &irq_timer);
 284
 285         /* Enable watchdog if we should use one. */
 286
 287 #if defined(CONFIG_ETRAX_WATCHDOG)
 288         printk(KERN_INFO "Enabling watchdog...\n");
 289         start_watchdog();
 290
 291         /* If we use the hardware watchdog, we want to trap it as an NMI
 292          * and dump registers before it resets us.  For this to happen, we
 293          * must set the "m" NMI enable flag (which once set, is unset only
 294          * when an NMI is taken). */
 295         {
 296                 unsigned long flags;
 297                 local_save_flags(flags);
 298                 flags |= (1<<30); /* NMI M flag is at bit 30 */
 299                 local_irq_restore(flags);
 300         }
 301 #endif
 302
 303 #ifdef CONFIG_CPU_FREQ
 304         cpufreq_register_notifier(&cris_time_freq_notifier_block,
 305                 CPUFREQ_TRANSITION_NOTIFIER);
 306 #endif
 307 }
 308
 309 #ifdef CONFIG_CPU_FREQ
 310 static int
 311 cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
 312                         void *data)
 313 {
 314         struct cpufreq_freqs *freqs = data;
 315         if (val == CPUFREQ_POSTCHANGE) {
 316                 reg_timer_r_tmr0_data data;
 317                 reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
 318                 do {
 319                         data = REG_RD(timer, timer_regs[freqs->cpu],
 320                                 r_tmr0_data);
 321                 } while (data > 20);
 322                 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
 323         }
 324         return 0;
 325 }
 326 #endif