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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / arch / x86 / kvm / mmu.c
blob224b02c3cda91683afed63cccc5e794fadef4559
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include "irq.h"
22 #include "mmu.h"
23 #include "x86.h"
24 #include "kvm_cache_regs.h"
25
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
29 #include <linux/mm.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
38
39 #include <asm/page.h>
40 #include <asm/cmpxchg.h>
41 #include <asm/io.h>
42 #include <asm/vmx.h>
43
44 /*
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
50 */
51 bool tdp_enabled = false;
52
53 enum {
54 AUDIT_PRE_PAGE_FAULT,
55 AUDIT_POST_PAGE_FAULT,
56 AUDIT_PRE_PTE_WRITE,
57 AUDIT_POST_PTE_WRITE,
58 AUDIT_PRE_SYNC,
59 AUDIT_POST_SYNC
60 };
61
62 #undef MMU_DEBUG
63
64 #ifdef MMU_DEBUG
65
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
68
69 #else
70
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
73
74 #endif
75
76 #ifdef MMU_DEBUG
77 static bool dbg = 0;
78 module_param(dbg, bool, 0644);
79 #endif
80
81 #ifndef MMU_DEBUG
82 #define ASSERT(x) do { } while (0)
83 #else
84 #define ASSERT(x) \
85 if (!(x)) { \
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
88 }
89 #endif
90
91 #define PTE_PREFETCH_NUM 8
92
93 #define PT_FIRST_AVAIL_BITS_SHIFT 9
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
95
96 #define PT64_LEVEL_BITS 9
97
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
100
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
103
104
105 #define PT32_LEVEL_BITS 10
106
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
109
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
113
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
116
117
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
127
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
134
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
136 | PT64_NX_MASK)
137
138 #define PTE_LIST_EXT 4
139
140 #define ACC_EXEC_MASK 1
141 #define ACC_WRITE_MASK PT_WRITABLE_MASK
142 #define ACC_USER_MASK PT_USER_MASK
143 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
144
145 #include <trace/events/kvm.h>
146
147 #define CREATE_TRACE_POINTS
148 #include "mmutrace.h"
149
150 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
151
152 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153
154 struct pte_list_desc {
155 u64 *sptes[PTE_LIST_EXT];
156 struct pte_list_desc *more;
157 };
158
159 struct kvm_shadow_walk_iterator {
160 u64 addr;
161 hpa_t shadow_addr;
162 u64 *sptep;
163 int level;
164 unsigned index;
165 };
166
167 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
168 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
169 shadow_walk_okay(&(_walker)); \
170 shadow_walk_next(&(_walker)))
171
172 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
173 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
174 shadow_walk_okay(&(_walker)) && \
175 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
176 __shadow_walk_next(&(_walker), spte))
177
178 static struct kmem_cache *pte_list_desc_cache;
179 static struct kmem_cache *mmu_page_header_cache;
180 static struct percpu_counter kvm_total_used_mmu_pages;
181
182 static u64 __read_mostly shadow_nx_mask;
183 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
184 static u64 __read_mostly shadow_user_mask;
185 static u64 __read_mostly shadow_accessed_mask;
186 static u64 __read_mostly shadow_dirty_mask;
187 static u64 __read_mostly shadow_mmio_mask;
188
189 static void mmu_spte_set(u64 *sptep, u64 spte);
190
191 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
192 {
193 shadow_mmio_mask = mmio_mask;
194 }
195 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
196
197 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
198 {
199 access &= ACC_WRITE_MASK | ACC_USER_MASK;
200
201 trace_mark_mmio_spte(sptep, gfn, access);
202 mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
203 }
204
205 static bool is_mmio_spte(u64 spte)
206 {
207 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
208 }
209
210 static gfn_t get_mmio_spte_gfn(u64 spte)
211 {
212 return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
213 }
214
215 static unsigned get_mmio_spte_access(u64 spte)
216 {
217 return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
218 }
219
220 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
221 {
222 if (unlikely(is_noslot_pfn(pfn))) {
223 mark_mmio_spte(sptep, gfn, access);
224 return true;
225 }
226
227 return false;
228 }
229
230 static inline u64 rsvd_bits(int s, int e)
231 {
232 return ((1ULL << (e - s + 1)) - 1) << s;
233 }
234
235 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
236 u64 dirty_mask, u64 nx_mask, u64 x_mask)
237 {
238 shadow_user_mask = user_mask;
239 shadow_accessed_mask = accessed_mask;
240 shadow_dirty_mask = dirty_mask;
241 shadow_nx_mask = nx_mask;
242 shadow_x_mask = x_mask;
243 }
244 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
245
246 static int is_cpuid_PSE36(void)
247 {
248 return 1;
249 }
250
251 static int is_nx(struct kvm_vcpu *vcpu)
252 {
253 return vcpu->arch.efer & EFER_NX;
254 }
255
256 static int is_shadow_present_pte(u64 pte)
257 {
258 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
259 }
260
261 static int is_large_pte(u64 pte)
262 {
263 return pte & PT_PAGE_SIZE_MASK;
264 }
265
266 static int is_dirty_gpte(unsigned long pte)
267 {
268 return pte & PT_DIRTY_MASK;
269 }
270
271 static int is_rmap_spte(u64 pte)
272 {
273 return is_shadow_present_pte(pte);
274 }
275
276 static int is_last_spte(u64 pte, int level)
277 {
278 if (level == PT_PAGE_TABLE_LEVEL)
279 return 1;
280 if (is_large_pte(pte))
281 return 1;
282 return 0;
283 }
284
285 static pfn_t spte_to_pfn(u64 pte)
286 {
287 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
288 }
289
290 static gfn_t pse36_gfn_delta(u32 gpte)
291 {
292 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
293
294 return (gpte & PT32_DIR_PSE36_MASK) << shift;
295 }
296
297 #ifdef CONFIG_X86_64
298 static void __set_spte(u64 *sptep, u64 spte)
299 {
300 *sptep = spte;
301 }
302
303 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
304 {
305 *sptep = spte;
306 }
307
308 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
309 {
310 return xchg(sptep, spte);
311 }
312
313 static u64 __get_spte_lockless(u64 *sptep)
314 {
315 return ACCESS_ONCE(*sptep);
316 }
317
318 static bool __check_direct_spte_mmio_pf(u64 spte)
319 {
320 /* It is valid if the spte is zapped. */
321 return spte == 0ull;
322 }
323 #else
324 union split_spte {
325 struct {
326 u32 spte_low;
327 u32 spte_high;
328 };
329 u64 spte;
330 };
331
332 static void count_spte_clear(u64 *sptep, u64 spte)
333 {
334 struct kvm_mmu_page *sp = page_header(__pa(sptep));
335
336 if (is_shadow_present_pte(spte))
337 return;
338
339 /* Ensure the spte is completely set before we increase the count */
340 smp_wmb();
341 sp->clear_spte_count++;
342 }
343
344 static void __set_spte(u64 *sptep, u64 spte)
345 {
346 union split_spte *ssptep, sspte;
347
348 ssptep = (union split_spte *)sptep;
349 sspte = (union split_spte)spte;
350
351 ssptep->spte_high = sspte.spte_high;
352
353 /*
354 * If we map the spte from nonpresent to present, We should store
355 * the high bits firstly, then set present bit, so cpu can not
356 * fetch this spte while we are setting the spte.
357 */
358 smp_wmb();
359
360 ssptep->spte_low = sspte.spte_low;
361 }
362
363 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
364 {
365 union split_spte *ssptep, sspte;
366
367 ssptep = (union split_spte *)sptep;
368 sspte = (union split_spte)spte;
369
370 ssptep->spte_low = sspte.spte_low;
371
372 /*
373 * If we map the spte from present to nonpresent, we should clear
374 * present bit firstly to avoid vcpu fetch the old high bits.
375 */
376 smp_wmb();
377
378 ssptep->spte_high = sspte.spte_high;
379 count_spte_clear(sptep, spte);
380 }
381
382 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
383 {
384 union split_spte *ssptep, sspte, orig;
385
386 ssptep = (union split_spte *)sptep;
387 sspte = (union split_spte)spte;
388
389 /* xchg acts as a barrier before the setting of the high bits */
390 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
391 orig.spte_high = ssptep->spte_high;
392 ssptep->spte_high = sspte.spte_high;
393 count_spte_clear(sptep, spte);
394
395 return orig.spte;
396 }
397
398 /*
399 * The idea using the light way get the spte on x86_32 guest is from
400 * gup_get_pte(arch/x86/mm/gup.c).
401 * The difference is we can not catch the spte tlb flush if we leave
402 * guest mode, so we emulate it by increase clear_spte_count when spte
403 * is cleared.
404 */
405 static u64 __get_spte_lockless(u64 *sptep)
406 {
407 struct kvm_mmu_page *sp = page_header(__pa(sptep));
408 union split_spte spte, *orig = (union split_spte *)sptep;
409 int count;
410
411 retry:
412 count = sp->clear_spte_count;
413 smp_rmb();
414
415 spte.spte_low = orig->spte_low;
416 smp_rmb();
417
418 spte.spte_high = orig->spte_high;
419 smp_rmb();
420
421 if (unlikely(spte.spte_low != orig->spte_low ||
422 count != sp->clear_spte_count))
423 goto retry;
424
425 return spte.spte;
426 }
427
428 static bool __check_direct_spte_mmio_pf(u64 spte)
429 {
430 union split_spte sspte = (union split_spte)spte;
431 u32 high_mmio_mask = shadow_mmio_mask >> 32;
432
433 /* It is valid if the spte is zapped. */
434 if (spte == 0ull)
435 return true;
436
437 /* It is valid if the spte is being zapped. */
438 if (sspte.spte_low == 0ull &&
439 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
440 return true;
441
442 return false;
443 }
444 #endif
445
446 static bool spte_has_volatile_bits(u64 spte)
447 {
448 if (!shadow_accessed_mask)
449 return false;
450
451 if (!is_shadow_present_pte(spte))
452 return false;
453
454 if ((spte & shadow_accessed_mask) &&
455 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
456 return false;
457
458 return true;
459 }
460
461 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
462 {
463 return (old_spte & bit_mask) && !(new_spte & bit_mask);
464 }
465
466 /* Rules for using mmu_spte_set:
467 * Set the sptep from nonpresent to present.
468 * Note: the sptep being assigned *must* be either not present
469 * or in a state where the hardware will not attempt to update
470 * the spte.
471 */
472 static void mmu_spte_set(u64 *sptep, u64 new_spte)
473 {
474 WARN_ON(is_shadow_present_pte(*sptep));
475 __set_spte(sptep, new_spte);
476 }
477
478 /* Rules for using mmu_spte_update:
479 * Update the state bits, it means the mapped pfn is not changged.
480 */
481 static void mmu_spte_update(u64 *sptep, u64 new_spte)
482 {
483 u64 mask, old_spte = *sptep;
484
485 WARN_ON(!is_rmap_spte(new_spte));
486
487 if (!is_shadow_present_pte(old_spte))
488 return mmu_spte_set(sptep, new_spte);
489
490 new_spte |= old_spte & shadow_dirty_mask;
491
492 mask = shadow_accessed_mask;
493 if (is_writable_pte(old_spte))
494 mask |= shadow_dirty_mask;
495
496 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
497 __update_clear_spte_fast(sptep, new_spte);
498 else
499 old_spte = __update_clear_spte_slow(sptep, new_spte);
500
501 if (!shadow_accessed_mask)
502 return;
503
504 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
505 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
506 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
507 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
508 }
509
510 /*
511 * Rules for using mmu_spte_clear_track_bits:
512 * It sets the sptep from present to nonpresent, and track the
513 * state bits, it is used to clear the last level sptep.
514 */
515 static int mmu_spte_clear_track_bits(u64 *sptep)
516 {
517 pfn_t pfn;
518 u64 old_spte = *sptep;
519
520 if (!spte_has_volatile_bits(old_spte))
521 __update_clear_spte_fast(sptep, 0ull);
522 else
523 old_spte = __update_clear_spte_slow(sptep, 0ull);
524
525 if (!is_rmap_spte(old_spte))
526 return 0;
527
528 pfn = spte_to_pfn(old_spte);
529 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
530 kvm_set_pfn_accessed(pfn);
531 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
532 kvm_set_pfn_dirty(pfn);
533 return 1;
534 }
535
536 /*
537 * Rules for using mmu_spte_clear_no_track:
538 * Directly clear spte without caring the state bits of sptep,
539 * it is used to set the upper level spte.
540 */
541 static void mmu_spte_clear_no_track(u64 *sptep)
542 {
543 __update_clear_spte_fast(sptep, 0ull);
544 }
545
546 static u64 mmu_spte_get_lockless(u64 *sptep)
547 {
548 return __get_spte_lockless(sptep);
549 }
550
551 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
552 {
553 rcu_read_lock();
554 atomic_inc(&vcpu->kvm->arch.reader_counter);
555
556 /* Increase the counter before walking shadow page table */
557 smp_mb__after_atomic_inc();
558 }
559
560 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
561 {
562 /* Decrease the counter after walking shadow page table finished */
563 smp_mb__before_atomic_dec();
564 atomic_dec(&vcpu->kvm->arch.reader_counter);
565 rcu_read_unlock();
566 }
567
568 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
569 struct kmem_cache *base_cache, int min)
570 {
571 void *obj;
572
573 if (cache->nobjs >= min)
574 return 0;
575 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
576 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
577 if (!obj)
578 return -ENOMEM;
579 cache->objects[cache->nobjs++] = obj;
580 }
581 return 0;
582 }
583
584 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
585 {
586 return cache->nobjs;
587 }
588
589 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
590 struct kmem_cache *cache)
591 {
592 while (mc->nobjs)
593 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
594 }
595
596 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
597 int min)
598 {
599 void *page;
600
601 if (cache->nobjs >= min)
602 return 0;
603 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
604 page = (void *)__get_free_page(GFP_KERNEL);
605 if (!page)
606 return -ENOMEM;
607 cache->objects[cache->nobjs++] = page;
608 }
609 return 0;
610 }
611
612 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
613 {
614 while (mc->nobjs)
615 free_page((unsigned long)mc->objects[--mc->nobjs]);
616 }
617
618 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
619 {
620 int r;
621
622 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
623 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
624 if (r)
625 goto out;
626 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
627 if (r)
628 goto out;
629 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
630 mmu_page_header_cache, 4);
631 out:
632 return r;
633 }
634
635 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
636 {
637 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
638 pte_list_desc_cache);
639 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
640 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
641 mmu_page_header_cache);
642 }
643
644 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
645 size_t size)
646 {
647 void *p;
648
649 BUG_ON(!mc->nobjs);
650 p = mc->objects[--mc->nobjs];
651 return p;
652 }
653
654 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
655 {
656 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
657 sizeof(struct pte_list_desc));
658 }
659
660 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
661 {
662 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
663 }
664
665 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
666 {
667 if (!sp->role.direct)
668 return sp->gfns[index];
669
670 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
671 }
672
673 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
674 {
675 if (sp->role.direct)
676 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
677 else
678 sp->gfns[index] = gfn;
679 }
680
681 /*
682 * Return the pointer to the large page information for a given gfn,
683 * handling slots that are not large page aligned.
684 */
685 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
686 struct kvm_memory_slot *slot,
687 int level)
688 {
689 unsigned long idx;
690
691 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
692 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
693 return &slot->lpage_info[level - 2][idx];
694 }
695
696 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
697 {
698 struct kvm_memory_slot *slot;
699 struct kvm_lpage_info *linfo;
700 int i;
701
702 slot = gfn_to_memslot(kvm, gfn);
703 for (i = PT_DIRECTORY_LEVEL;
704 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
705 linfo = lpage_info_slot(gfn, slot, i);
706 linfo->write_count += 1;
707 }
708 kvm->arch.indirect_shadow_pages++;
709 }
710
711 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
712 {
713 struct kvm_memory_slot *slot;
714 struct kvm_lpage_info *linfo;
715 int i;
716
717 slot = gfn_to_memslot(kvm, gfn);
718 for (i = PT_DIRECTORY_LEVEL;
719 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
720 linfo = lpage_info_slot(gfn, slot, i);
721 linfo->write_count -= 1;
722 WARN_ON(linfo->write_count < 0);
723 }
724 kvm->arch.indirect_shadow_pages--;
725 }
726
727 static int has_wrprotected_page(struct kvm *kvm,
728 gfn_t gfn,
729 int level)
730 {
731 struct kvm_memory_slot *slot;
732 struct kvm_lpage_info *linfo;
733
734 slot = gfn_to_memslot(kvm, gfn);
735 if (slot) {
736 linfo = lpage_info_slot(gfn, slot, level);
737 return linfo->write_count;
738 }
739
740 return 1;
741 }
742
743 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
744 {
745 unsigned long page_size;
746 int i, ret = 0;
747
748 page_size = kvm_host_page_size(kvm, gfn);
749
750 for (i = PT_PAGE_TABLE_LEVEL;
751 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
752 if (page_size >= KVM_HPAGE_SIZE(i))
753 ret = i;
754 else
755 break;
756 }
757
758 return ret;
759 }
760
761 static struct kvm_memory_slot *
762 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
763 bool no_dirty_log)
764 {
765 struct kvm_memory_slot *slot;
766
767 slot = gfn_to_memslot(vcpu->kvm, gfn);
768 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
769 (no_dirty_log && slot->dirty_bitmap))
770 slot = NULL;
771
772 return slot;
773 }
774
775 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
776 {
777 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
778 }
779
780 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
781 {
782 int host_level, level, max_level;
783
784 host_level = host_mapping_level(vcpu->kvm, large_gfn);
785
786 if (host_level == PT_PAGE_TABLE_LEVEL)
787 return host_level;
788
789 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
790 kvm_x86_ops->get_lpage_level() : host_level;
791
792 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
793 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
794 break;
795
796 return level - 1;
797 }
798
799 /*
800 * Pte mapping structures:
801 *
802 * If pte_list bit zero is zero, then pte_list point to the spte.
803 *
804 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
805 * pte_list_desc containing more mappings.
806 *
807 * Returns the number of pte entries before the spte was added or zero if
808 * the spte was not added.
809 *
810 */
811 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
812 unsigned long *pte_list)
813 {
814 struct pte_list_desc *desc;
815 int i, count = 0;
816
817 if (!*pte_list) {
818 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
819 *pte_list = (unsigned long)spte;
820 } else if (!(*pte_list & 1)) {
821 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
822 desc = mmu_alloc_pte_list_desc(vcpu);
823 desc->sptes[0] = (u64 *)*pte_list;
824 desc->sptes[1] = spte;
825 *pte_list = (unsigned long)desc | 1;
826 ++count;
827 } else {
828 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
829 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
830 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
831 desc = desc->more;
832 count += PTE_LIST_EXT;
833 }
834 if (desc->sptes[PTE_LIST_EXT-1]) {
835 desc->more = mmu_alloc_pte_list_desc(vcpu);
836 desc = desc->more;
837 }
838 for (i = 0; desc->sptes[i]; ++i)
839 ++count;
840 desc->sptes[i] = spte;
841 }
842 return count;
843 }
844
845 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
846 {
847 struct pte_list_desc *desc;
848 u64 *prev_spte;
849 int i;
850
851 if (!*pte_list)
852 return NULL;
853 else if (!(*pte_list & 1)) {
854 if (!spte)
855 return (u64 *)*pte_list;
856 return NULL;
857 }
858 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
859 prev_spte = NULL;
860 while (desc) {
861 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
862 if (prev_spte == spte)
863 return desc->sptes[i];
864 prev_spte = desc->sptes[i];
865 }
866 desc = desc->more;
867 }
868 return NULL;
869 }
870
871 static void
872 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
873 int i, struct pte_list_desc *prev_desc)
874 {
875 int j;
876
877 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
878 ;
879 desc->sptes[i] = desc->sptes[j];
880 desc->sptes[j] = NULL;
881 if (j != 0)
882 return;
883 if (!prev_desc && !desc->more)
884 *pte_list = (unsigned long)desc->sptes[0];
885 else
886 if (prev_desc)
887 prev_desc->more = desc->more;
888 else
889 *pte_list = (unsigned long)desc->more | 1;
890 mmu_free_pte_list_desc(desc);
891 }
892
893 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
894 {
895 struct pte_list_desc *desc;
896 struct pte_list_desc *prev_desc;
897 int i;
898
899 if (!*pte_list) {
900 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
901 BUG();
902 } else if (!(*pte_list & 1)) {
903 rmap_printk("pte_list_remove: %p 1->0\n", spte);
904 if ((u64 *)*pte_list != spte) {
905 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
906 BUG();
907 }
908 *pte_list = 0;
909 } else {
910 rmap_printk("pte_list_remove: %p many->many\n", spte);
911 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
912 prev_desc = NULL;
913 while (desc) {
914 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
915 if (desc->sptes[i] == spte) {
916 pte_list_desc_remove_entry(pte_list,
917 desc, i,
918 prev_desc);
919 return;
920 }
921 prev_desc = desc;
922 desc = desc->more;
923 }
924 pr_err("pte_list_remove: %p many->many\n", spte);
925 BUG();
926 }
927 }
928
929 typedef void (*pte_list_walk_fn) (u64 *spte);
930 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
931 {
932 struct pte_list_desc *desc;
933 int i;
934
935 if (!*pte_list)
936 return;
937
938 if (!(*pte_list & 1))
939 return fn((u64 *)*pte_list);
940
941 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
942 while (desc) {
943 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
944 fn(desc->sptes[i]);
945 desc = desc->more;
946 }
947 }
948
949 static unsigned long *__gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level,
950 struct kvm_memory_slot *slot)
951 {
952 struct kvm_lpage_info *linfo;
953
954 if (likely(level == PT_PAGE_TABLE_LEVEL))
955 return &slot->rmap[gfn - slot->base_gfn];
956
957 linfo = lpage_info_slot(gfn, slot, level);
958 return &linfo->rmap_pde;
959 }
960
961 /*
962 * Take gfn and return the reverse mapping to it.
963 */
964 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
965 {
966 struct kvm_memory_slot *slot;
967
968 slot = gfn_to_memslot(kvm, gfn);
969 return __gfn_to_rmap(kvm, gfn, level, slot);
970 }
971
972 static bool rmap_can_add(struct kvm_vcpu *vcpu)
973 {
974 struct kvm_mmu_memory_cache *cache;
975
976 cache = &vcpu->arch.mmu_pte_list_desc_cache;
977 return mmu_memory_cache_free_objects(cache);
978 }
979
980 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
981 {
982 struct kvm_mmu_page *sp;
983 unsigned long *rmapp;
984
985 sp = page_header(__pa(spte));
986 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
987 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
988 return pte_list_add(vcpu, spte, rmapp);
989 }
990
991 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
992 {
993 return pte_list_next(rmapp, spte);
994 }
995
996 static void rmap_remove(struct kvm *kvm, u64 *spte)
997 {
998 struct kvm_mmu_page *sp;
999 gfn_t gfn;
1000 unsigned long *rmapp;
1001
1002 sp = page_header(__pa(spte));
1003 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1004 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1005 pte_list_remove(spte, rmapp);
1006 }
1007
1008 static void drop_spte(struct kvm *kvm, u64 *sptep)
1009 {
1010 if (mmu_spte_clear_track_bits(sptep))
1011 rmap_remove(kvm, sptep);
1012 }
1013
1014 int kvm_mmu_rmap_write_protect(struct kvm *kvm, u64 gfn,
1015 struct kvm_memory_slot *slot)
1016 {
1017 unsigned long *rmapp;
1018 u64 *spte;
1019 int i, write_protected = 0;
1020
1021 rmapp = __gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL, slot);
1022 spte = rmap_next(kvm, rmapp, NULL);
1023 while (spte) {
1024 BUG_ON(!(*spte & PT_PRESENT_MASK));
1025 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
1026 if (is_writable_pte(*spte)) {
1027 mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
1028 write_protected = 1;
1029 }
1030 spte = rmap_next(kvm, rmapp, spte);
1031 }
1032
1033 /* check for huge page mappings */
1034 for (i = PT_DIRECTORY_LEVEL;
1035 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1036 rmapp = __gfn_to_rmap(kvm, gfn, i, slot);
1037 spte = rmap_next(kvm, rmapp, NULL);
1038 while (spte) {
1039 BUG_ON(!(*spte & PT_PRESENT_MASK));
1040 BUG_ON(!is_large_pte(*spte));
1041 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
1042 if (is_writable_pte(*spte)) {
1043 drop_spte(kvm, spte);
1044 --kvm->stat.lpages;
1045 spte = NULL;
1046 write_protected = 1;
1047 }
1048 spte = rmap_next(kvm, rmapp, spte);
1049 }
1050 }
1051
1052 return write_protected;
1053 }
1054
1055 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
1056 {
1057 struct kvm_memory_slot *slot;
1058
1059 slot = gfn_to_memslot(kvm, gfn);
1060 return kvm_mmu_rmap_write_protect(kvm, gfn, slot);
1061 }
1062
1063 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1064 unsigned long data)
1065 {
1066 u64 *spte;
1067 int need_tlb_flush = 0;
1068
1069 while ((spte = rmap_next(kvm, rmapp, NULL))) {
1070 BUG_ON(!(*spte & PT_PRESENT_MASK));
1071 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
1072 drop_spte(kvm, spte);
1073 need_tlb_flush = 1;
1074 }
1075 return need_tlb_flush;
1076 }
1077
1078 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1079 unsigned long data)
1080 {
1081 int need_flush = 0;
1082 u64 *spte, new_spte;
1083 pte_t *ptep = (pte_t *)data;
1084 pfn_t new_pfn;
1085
1086 WARN_ON(pte_huge(*ptep));
1087 new_pfn = pte_pfn(*ptep);
1088 spte = rmap_next(kvm, rmapp, NULL);
1089 while (spte) {
1090 BUG_ON(!is_shadow_present_pte(*spte));
1091 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
1092 need_flush = 1;
1093 if (pte_write(*ptep)) {
1094 drop_spte(kvm, spte);
1095 spte = rmap_next(kvm, rmapp, NULL);
1096 } else {
1097 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
1098 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1099
1100 new_spte &= ~PT_WRITABLE_MASK;
1101 new_spte &= ~SPTE_HOST_WRITEABLE;
1102 new_spte &= ~shadow_accessed_mask;
1103 mmu_spte_clear_track_bits(spte);
1104 mmu_spte_set(spte, new_spte);
1105 spte = rmap_next(kvm, rmapp, spte);
1106 }
1107 }
1108 if (need_flush)
1109 kvm_flush_remote_tlbs(kvm);
1110
1111 return 0;
1112 }
1113
1114 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1115 unsigned long data,
1116 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1117 unsigned long data))
1118 {
1119 int j;
1120 int ret;
1121 int retval = 0;
1122 struct kvm_memslots *slots;
1123 struct kvm_memory_slot *memslot;
1124
1125 slots = kvm_memslots(kvm);
1126
1127 kvm_for_each_memslot(memslot, slots) {
1128 unsigned long start = memslot->userspace_addr;
1129 unsigned long end;
1130
1131 end = start + (memslot->npages << PAGE_SHIFT);
1132 if (hva >= start && hva < end) {
1133 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1134 gfn_t gfn = memslot->base_gfn + gfn_offset;
1135
1136 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1137
1138 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1139 struct kvm_lpage_info *linfo;
1140
1141 linfo = lpage_info_slot(gfn, memslot,
1142 PT_DIRECTORY_LEVEL + j);
1143 ret |= handler(kvm, &linfo->rmap_pde, data);
1144 }
1145 trace_kvm_age_page(hva, memslot, ret);
1146 retval |= ret;
1147 }
1148 }
1149
1150 return retval;
1151 }
1152
1153 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1154 {
1155 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1156 }
1157
1158 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1159 {
1160 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1161 }
1162
1163 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1164 unsigned long data)
1165 {
1166 u64 *spte;
1167 int young = 0;
1168
1169 /*
1170 * Emulate the accessed bit for EPT, by checking if this page has
1171 * an EPT mapping, and clearing it if it does. On the next access,
1172 * a new EPT mapping will be established.
1173 * This has some overhead, but not as much as the cost of swapping
1174 * out actively used pages or breaking up actively used hugepages.
1175 */
1176 if (!shadow_accessed_mask)
1177 return kvm_unmap_rmapp(kvm, rmapp, data);
1178
1179 spte = rmap_next(kvm, rmapp, NULL);
1180 while (spte) {
1181 int _young;
1182 u64 _spte = *spte;
1183 BUG_ON(!(_spte & PT_PRESENT_MASK));
1184 _young = _spte & PT_ACCESSED_MASK;
1185 if (_young) {
1186 young = 1;
1187 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
1188 }
1189 spte = rmap_next(kvm, rmapp, spte);
1190 }
1191 return young;
1192 }
1193
1194 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1195 unsigned long data)
1196 {
1197 u64 *spte;
1198 int young = 0;
1199
1200 /*
1201 * If there's no access bit in the secondary pte set by the
1202 * hardware it's up to gup-fast/gup to set the access bit in
1203 * the primary pte or in the page structure.
1204 */
1205 if (!shadow_accessed_mask)
1206 goto out;
1207
1208 spte = rmap_next(kvm, rmapp, NULL);
1209 while (spte) {
1210 u64 _spte = *spte;
1211 BUG_ON(!(_spte & PT_PRESENT_MASK));
1212 young = _spte & PT_ACCESSED_MASK;
1213 if (young) {
1214 young = 1;
1215 break;
1216 }
1217 spte = rmap_next(kvm, rmapp, spte);
1218 }
1219 out:
1220 return young;
1221 }
1222
1223 #define RMAP_RECYCLE_THRESHOLD 1000
1224
1225 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1226 {
1227 unsigned long *rmapp;
1228 struct kvm_mmu_page *sp;
1229
1230 sp = page_header(__pa(spte));
1231
1232 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1233
1234 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1235 kvm_flush_remote_tlbs(vcpu->kvm);
1236 }
1237
1238 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1239 {
1240 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1241 }
1242
1243 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1244 {
1245 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1246 }
1247
1248 #ifdef MMU_DEBUG
1249 static int is_empty_shadow_page(u64 *spt)
1250 {
1251 u64 *pos;
1252 u64 *end;
1253
1254 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1255 if (is_shadow_present_pte(*pos)) {
1256 printk(KERN_ERR "%s: %p %llx\n", __func__,
1257 pos, *pos);
1258 return 0;
1259 }
1260 return 1;
1261 }
1262 #endif
1263
1264 /*
1265 * This value is the sum of all of the kvm instances's
1266 * kvm->arch.n_used_mmu_pages values. We need a global,
1267 * aggregate version in order to make the slab shrinker
1268 * faster
1269 */
1270 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1271 {
1272 kvm->arch.n_used_mmu_pages += nr;
1273 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1274 }
1275
1276 /*
1277 * Remove the sp from shadow page cache, after call it,
1278 * we can not find this sp from the cache, and the shadow
1279 * page table is still valid.
1280 * It should be under the protection of mmu lock.
1281 */
1282 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1283 {
1284 ASSERT(is_empty_shadow_page(sp->spt));
1285 hlist_del(&sp->hash_link);
1286 if (!sp->role.direct)
1287 free_page((unsigned long)sp->gfns);
1288 }
1289
1290 /*
1291 * Free the shadow page table and the sp, we can do it
1292 * out of the protection of mmu lock.
1293 */
1294 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1295 {
1296 list_del(&sp->link);
1297 free_page((unsigned long)sp->spt);
1298 kmem_cache_free(mmu_page_header_cache, sp);
1299 }
1300
1301 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1302 {
1303 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1304 }
1305
1306 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1307 struct kvm_mmu_page *sp, u64 *parent_pte)
1308 {
1309 if (!parent_pte)
1310 return;
1311
1312 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1313 }
1314
1315 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1316 u64 *parent_pte)
1317 {
1318 pte_list_remove(parent_pte, &sp->parent_ptes);
1319 }
1320
1321 static void drop_parent_pte(struct kvm_mmu_page *sp,
1322 u64 *parent_pte)
1323 {
1324 mmu_page_remove_parent_pte(sp, parent_pte);
1325 mmu_spte_clear_no_track(parent_pte);
1326 }
1327
1328 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1329 u64 *parent_pte, int direct)
1330 {
1331 struct kvm_mmu_page *sp;
1332 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1333 sizeof *sp);
1334 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1335 if (!direct)
1336 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1337 PAGE_SIZE);
1338 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1339 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1340 bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM);
1341 sp->parent_ptes = 0;
1342 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1343 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1344 return sp;
1345 }
1346
1347 static void mark_unsync(u64 *spte);
1348 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1349 {
1350 pte_list_walk(&sp->parent_ptes, mark_unsync);
1351 }
1352
1353 static void mark_unsync(u64 *spte)
1354 {
1355 struct kvm_mmu_page *sp;
1356 unsigned int index;
1357
1358 sp = page_header(__pa(spte));
1359 index = spte - sp->spt;
1360 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1361 return;
1362 if (sp->unsync_children++)
1363 return;
1364 kvm_mmu_mark_parents_unsync(sp);
1365 }
1366
1367 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1368 struct kvm_mmu_page *sp)
1369 {
1370 return 1;
1371 }
1372
1373 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1374 {
1375 }
1376
1377 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1378 struct kvm_mmu_page *sp, u64 *spte,
1379 const void *pte)
1380 {
1381 WARN_ON(1);
1382 }
1383
1384 #define KVM_PAGE_ARRAY_NR 16
1385
1386 struct kvm_mmu_pages {
1387 struct mmu_page_and_offset {
1388 struct kvm_mmu_page *sp;
1389 unsigned int idx;
1390 } page[KVM_PAGE_ARRAY_NR];
1391 unsigned int nr;
1392 };
1393
1394 #define for_each_unsync_children(bitmap, idx) \
1395 for (idx = find_first_bit(bitmap, 512); \
1396 idx < 512; \
1397 idx = find_next_bit(bitmap, 512, idx+1))
1398
1399 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1400 int idx)
1401 {
1402 int i;
1403
1404 if (sp->unsync)
1405 for (i=0; i < pvec->nr; i++)
1406 if (pvec->page[i].sp == sp)
1407 return 0;
1408
1409 pvec->page[pvec->nr].sp = sp;
1410 pvec->page[pvec->nr].idx = idx;
1411 pvec->nr++;
1412 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1413 }
1414
1415 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1416 struct kvm_mmu_pages *pvec)
1417 {
1418 int i, ret, nr_unsync_leaf = 0;
1419
1420 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1421 struct kvm_mmu_page *child;
1422 u64 ent = sp->spt[i];
1423
1424 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1425 goto clear_child_bitmap;
1426
1427 child = page_header(ent & PT64_BASE_ADDR_MASK);
1428
1429 if (child->unsync_children) {
1430 if (mmu_pages_add(pvec, child, i))
1431 return -ENOSPC;
1432
1433 ret = __mmu_unsync_walk(child, pvec);
1434 if (!ret)
1435 goto clear_child_bitmap;
1436 else if (ret > 0)
1437 nr_unsync_leaf += ret;
1438 else
1439 return ret;
1440 } else if (child->unsync) {
1441 nr_unsync_leaf++;
1442 if (mmu_pages_add(pvec, child, i))
1443 return -ENOSPC;
1444 } else
1445 goto clear_child_bitmap;
1446
1447 continue;
1448
1449 clear_child_bitmap:
1450 __clear_bit(i, sp->unsync_child_bitmap);
1451 sp->unsync_children--;
1452 WARN_ON((int)sp->unsync_children < 0);
1453 }
1454
1455
1456 return nr_unsync_leaf;
1457 }
1458
1459 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1460 struct kvm_mmu_pages *pvec)
1461 {
1462 if (!sp->unsync_children)
1463 return 0;
1464
1465 mmu_pages_add(pvec, sp, 0);
1466 return __mmu_unsync_walk(sp, pvec);
1467 }
1468
1469 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1470 {
1471 WARN_ON(!sp->unsync);
1472 trace_kvm_mmu_sync_page(sp);
1473 sp->unsync = 0;
1474 --kvm->stat.mmu_unsync;
1475 }
1476
1477 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1478 struct list_head *invalid_list);
1479 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1480 struct list_head *invalid_list);
1481
1482 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1483 hlist_for_each_entry(sp, pos, \
1484 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1485 if ((sp)->gfn != (gfn)) {} else
1486
1487 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1488 hlist_for_each_entry(sp, pos, \
1489 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1490 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1491 (sp)->role.invalid) {} else
1492
1493 /* @sp->gfn should be write-protected at the call site */
1494 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1495 struct list_head *invalid_list, bool clear_unsync)
1496 {
1497 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1498 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1499 return 1;
1500 }
1501
1502 if (clear_unsync)
1503 kvm_unlink_unsync_page(vcpu->kvm, sp);
1504
1505 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1506 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1507 return 1;
1508 }
1509
1510 kvm_mmu_flush_tlb(vcpu);
1511 return 0;
1512 }
1513
1514 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1515 struct kvm_mmu_page *sp)
1516 {
1517 LIST_HEAD(invalid_list);
1518 int ret;
1519
1520 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1521 if (ret)
1522 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1523
1524 return ret;
1525 }
1526
1527 #ifdef CONFIG_KVM_MMU_AUDIT
1528 #include "mmu_audit.c"
1529 #else
1530 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1531 static void mmu_audit_disable(void) { }
1532 #endif
1533
1534 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1535 struct list_head *invalid_list)
1536 {
1537 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1538 }
1539
1540 /* @gfn should be write-protected at the call site */
1541 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1542 {
1543 struct kvm_mmu_page *s;
1544 struct hlist_node *node;
1545 LIST_HEAD(invalid_list);
1546 bool flush = false;
1547
1548 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1549 if (!s->unsync)
1550 continue;
1551
1552 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1553 kvm_unlink_unsync_page(vcpu->kvm, s);
1554 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1555 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1556 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1557 continue;
1558 }
1559 flush = true;
1560 }
1561
1562 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1563 if (flush)
1564 kvm_mmu_flush_tlb(vcpu);
1565 }
1566
1567 struct mmu_page_path {
1568 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1569 unsigned int idx[PT64_ROOT_LEVEL-1];
1570 };
1571
1572 #define for_each_sp(pvec, sp, parents, i) \
1573 for (i = mmu_pages_next(&pvec, &parents, -1), \
1574 sp = pvec.page[i].sp; \
1575 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1576 i = mmu_pages_next(&pvec, &parents, i))
1577
1578 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1579 struct mmu_page_path *parents,
1580 int i)
1581 {
1582 int n;
1583
1584 for (n = i+1; n < pvec->nr; n++) {
1585 struct kvm_mmu_page *sp = pvec->page[n].sp;
1586
1587 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1588 parents->idx[0] = pvec->page[n].idx;
1589 return n;
1590 }
1591
1592 parents->parent[sp->role.level-2] = sp;
1593 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1594 }
1595
1596 return n;
1597 }
1598
1599 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1600 {
1601 struct kvm_mmu_page *sp;
1602 unsigned int level = 0;
1603
1604 do {
1605 unsigned int idx = parents->idx[level];
1606
1607 sp = parents->parent[level];
1608 if (!sp)
1609 return;
1610
1611 --sp->unsync_children;
1612 WARN_ON((int)sp->unsync_children < 0);
1613 __clear_bit(idx, sp->unsync_child_bitmap);
1614 level++;
1615 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1616 }
1617
1618 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1619 struct mmu_page_path *parents,
1620 struct kvm_mmu_pages *pvec)
1621 {
1622 parents->parent[parent->role.level-1] = NULL;
1623 pvec->nr = 0;
1624 }
1625
1626 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1627 struct kvm_mmu_page *parent)
1628 {
1629 int i;
1630 struct kvm_mmu_page *sp;
1631 struct mmu_page_path parents;
1632 struct kvm_mmu_pages pages;
1633 LIST_HEAD(invalid_list);
1634
1635 kvm_mmu_pages_init(parent, &parents, &pages);
1636 while (mmu_unsync_walk(parent, &pages)) {
1637 int protected = 0;
1638
1639 for_each_sp(pages, sp, parents, i)
1640 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1641
1642 if (protected)
1643 kvm_flush_remote_tlbs(vcpu->kvm);
1644
1645 for_each_sp(pages, sp, parents, i) {
1646 kvm_sync_page(vcpu, sp, &invalid_list);
1647 mmu_pages_clear_parents(&parents);
1648 }
1649 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1650 cond_resched_lock(&vcpu->kvm->mmu_lock);
1651 kvm_mmu_pages_init(parent, &parents, &pages);
1652 }
1653 }
1654
1655 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1656 {
1657 int i;
1658
1659 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1660 sp->spt[i] = 0ull;
1661 }
1662
1663 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1664 {
1665 sp->write_flooding_count = 0;
1666 }
1667
1668 static void clear_sp_write_flooding_count(u64 *spte)
1669 {
1670 struct kvm_mmu_page *sp = page_header(__pa(spte));
1671
1672 __clear_sp_write_flooding_count(sp);
1673 }
1674
1675 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1676 gfn_t gfn,
1677 gva_t gaddr,
1678 unsigned level,
1679 int direct,
1680 unsigned access,
1681 u64 *parent_pte)
1682 {
1683 union kvm_mmu_page_role role;
1684 unsigned quadrant;
1685 struct kvm_mmu_page *sp;
1686 struct hlist_node *node;
1687 bool need_sync = false;
1688
1689 role = vcpu->arch.mmu.base_role;
1690 role.level = level;
1691 role.direct = direct;
1692 if (role.direct)
1693 role.cr4_pae = 0;
1694 role.access = access;
1695 if (!vcpu->arch.mmu.direct_map
1696 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1697 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1698 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1699 role.quadrant = quadrant;
1700 }
1701 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1702 if (!need_sync && sp->unsync)
1703 need_sync = true;
1704
1705 if (sp->role.word != role.word)
1706 continue;
1707
1708 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1709 break;
1710
1711 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1712 if (sp->unsync_children) {
1713 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1714 kvm_mmu_mark_parents_unsync(sp);
1715 } else if (sp->unsync)
1716 kvm_mmu_mark_parents_unsync(sp);
1717
1718 __clear_sp_write_flooding_count(sp);
1719 trace_kvm_mmu_get_page(sp, false);
1720 return sp;
1721 }
1722 ++vcpu->kvm->stat.mmu_cache_miss;
1723 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1724 if (!sp)
1725 return sp;
1726 sp->gfn = gfn;
1727 sp->role = role;
1728 hlist_add_head(&sp->hash_link,
1729 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1730 if (!direct) {
1731 if (rmap_write_protect(vcpu->kvm, gfn))
1732 kvm_flush_remote_tlbs(vcpu->kvm);
1733 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1734 kvm_sync_pages(vcpu, gfn);
1735
1736 account_shadowed(vcpu->kvm, gfn);
1737 }
1738 init_shadow_page_table(sp);
1739 trace_kvm_mmu_get_page(sp, true);
1740 return sp;
1741 }
1742
1743 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1744 struct kvm_vcpu *vcpu, u64 addr)
1745 {
1746 iterator->addr = addr;
1747 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1748 iterator->level = vcpu->arch.mmu.shadow_root_level;
1749
1750 if (iterator->level == PT64_ROOT_LEVEL &&
1751 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1752 !vcpu->arch.mmu.direct_map)
1753 --iterator->level;
1754
1755 if (iterator->level == PT32E_ROOT_LEVEL) {
1756 iterator->shadow_addr
1757 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1758 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1759 --iterator->level;
1760 if (!iterator->shadow_addr)
1761 iterator->level = 0;
1762 }
1763 }
1764
1765 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1766 {
1767 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1768 return false;
1769
1770 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1771 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1772 return true;
1773 }
1774
1775 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1776 u64 spte)
1777 {
1778 if (is_last_spte(spte, iterator->level)) {
1779 iterator->level = 0;
1780 return;
1781 }
1782
1783 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1784 --iterator->level;
1785 }
1786
1787 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1788 {
1789 return __shadow_walk_next(iterator, *iterator->sptep);
1790 }
1791
1792 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1793 {
1794 u64 spte;
1795
1796 spte = __pa(sp->spt)
1797 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1798 | PT_WRITABLE_MASK | PT_USER_MASK;
1799 mmu_spte_set(sptep, spte);
1800 }
1801
1802 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1803 {
1804 if (is_large_pte(*sptep)) {
1805 drop_spte(vcpu->kvm, sptep);
1806 kvm_flush_remote_tlbs(vcpu->kvm);
1807 }
1808 }
1809
1810 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1811 unsigned direct_access)
1812 {
1813 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1814 struct kvm_mmu_page *child;
1815
1816 /*
1817 * For the direct sp, if the guest pte's dirty bit
1818 * changed form clean to dirty, it will corrupt the
1819 * sp's access: allow writable in the read-only sp,
1820 * so we should update the spte at this point to get
1821 * a new sp with the correct access.
1822 */
1823 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1824 if (child->role.access == direct_access)
1825 return;
1826
1827 drop_parent_pte(child, sptep);
1828 kvm_flush_remote_tlbs(vcpu->kvm);
1829 }
1830 }
1831
1832 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1833 u64 *spte)
1834 {
1835 u64 pte;
1836 struct kvm_mmu_page *child;
1837
1838 pte = *spte;
1839 if (is_shadow_present_pte(pte)) {
1840 if (is_last_spte(pte, sp->role.level)) {
1841 drop_spte(kvm, spte);
1842 if (is_large_pte(pte))
1843 --kvm->stat.lpages;
1844 } else {
1845 child = page_header(pte & PT64_BASE_ADDR_MASK);
1846 drop_parent_pte(child, spte);
1847 }
1848 return true;
1849 }
1850
1851 if (is_mmio_spte(pte))
1852 mmu_spte_clear_no_track(spte);
1853
1854 return false;
1855 }
1856
1857 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1858 struct kvm_mmu_page *sp)
1859 {
1860 unsigned i;
1861
1862 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1863 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1864 }
1865
1866 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1867 {
1868 mmu_page_remove_parent_pte(sp, parent_pte);
1869 }
1870
1871 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1872 {
1873 u64 *parent_pte;
1874
1875 while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1876 drop_parent_pte(sp, parent_pte);
1877 }
1878
1879 static int mmu_zap_unsync_children(struct kvm *kvm,
1880 struct kvm_mmu_page *parent,
1881 struct list_head *invalid_list)
1882 {
1883 int i, zapped = 0;
1884 struct mmu_page_path parents;
1885 struct kvm_mmu_pages pages;
1886
1887 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1888 return 0;
1889
1890 kvm_mmu_pages_init(parent, &parents, &pages);
1891 while (mmu_unsync_walk(parent, &pages)) {
1892 struct kvm_mmu_page *sp;
1893
1894 for_each_sp(pages, sp, parents, i) {
1895 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1896 mmu_pages_clear_parents(&parents);
1897 zapped++;
1898 }
1899 kvm_mmu_pages_init(parent, &parents, &pages);
1900 }
1901
1902 return zapped;
1903 }
1904
1905 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1906 struct list_head *invalid_list)
1907 {
1908 int ret;
1909
1910 trace_kvm_mmu_prepare_zap_page(sp);
1911 ++kvm->stat.mmu_shadow_zapped;
1912 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1913 kvm_mmu_page_unlink_children(kvm, sp);
1914 kvm_mmu_unlink_parents(kvm, sp);
1915 if (!sp->role.invalid && !sp->role.direct)
1916 unaccount_shadowed(kvm, sp->gfn);
1917 if (sp->unsync)
1918 kvm_unlink_unsync_page(kvm, sp);
1919 if (!sp->root_count) {
1920 /* Count self */
1921 ret++;
1922 list_move(&sp->link, invalid_list);
1923 kvm_mod_used_mmu_pages(kvm, -1);
1924 } else {
1925 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1926 kvm_reload_remote_mmus(kvm);
1927 }
1928
1929 sp->role.invalid = 1;
1930 return ret;
1931 }
1932
1933 static void kvm_mmu_isolate_pages(struct list_head *invalid_list)
1934 {
1935 struct kvm_mmu_page *sp;
1936
1937 list_for_each_entry(sp, invalid_list, link)
1938 kvm_mmu_isolate_page(sp);
1939 }
1940
1941 static void free_pages_rcu(struct rcu_head *head)
1942 {
1943 struct kvm_mmu_page *next, *sp;
1944
1945 sp = container_of(head, struct kvm_mmu_page, rcu);
1946 while (sp) {
1947 if (!list_empty(&sp->link))
1948 next = list_first_entry(&sp->link,
1949 struct kvm_mmu_page, link);
1950 else
1951 next = NULL;
1952 kvm_mmu_free_page(sp);
1953 sp = next;
1954 }
1955 }
1956
1957 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1958 struct list_head *invalid_list)
1959 {
1960 struct kvm_mmu_page *sp;
1961
1962 if (list_empty(invalid_list))
1963 return;
1964
1965 kvm_flush_remote_tlbs(kvm);
1966
1967 if (atomic_read(&kvm->arch.reader_counter)) {
1968 kvm_mmu_isolate_pages(invalid_list);
1969 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1970 list_del_init(invalid_list);
1971
1972 trace_kvm_mmu_delay_free_pages(sp);
1973 call_rcu(&sp->rcu, free_pages_rcu);
1974 return;
1975 }
1976
1977 do {
1978 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1979 WARN_ON(!sp->role.invalid || sp->root_count);
1980 kvm_mmu_isolate_page(sp);
1981 kvm_mmu_free_page(sp);
1982 } while (!list_empty(invalid_list));
1983
1984 }
1985
1986 /*
1987 * Changing the number of mmu pages allocated to the vm
1988 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1989 */
1990 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1991 {
1992 LIST_HEAD(invalid_list);
1993 /*
1994 * If we set the number of mmu pages to be smaller be than the
1995 * number of actived pages , we must to free some mmu pages before we
1996 * change the value
1997 */
1998
1999 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2000 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
2001 !list_empty(&kvm->arch.active_mmu_pages)) {
2002 struct kvm_mmu_page *page;
2003
2004 page = container_of(kvm->arch.active_mmu_pages.prev,
2005 struct kvm_mmu_page, link);
2006 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2007 }
2008 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2009 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2010 }
2011
2012 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2013 }
2014
2015 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2016 {
2017 struct kvm_mmu_page *sp;
2018 struct hlist_node *node;
2019 LIST_HEAD(invalid_list);
2020 int r;
2021
2022 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2023 r = 0;
2024 spin_lock(&kvm->mmu_lock);
2025 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2026 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2027 sp->role.word);
2028 r = 1;
2029 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2030 }
2031 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2032 spin_unlock(&kvm->mmu_lock);
2033
2034 return r;
2035 }
2036 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2037
2038 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2039 {
2040 int slot = memslot_id(kvm, gfn);
2041 struct kvm_mmu_page *sp = page_header(__pa(pte));
2042
2043 __set_bit(slot, sp->slot_bitmap);
2044 }
2045
2046 /*
2047 * The function is based on mtrr_type_lookup() in
2048 * arch/x86/kernel/cpu/mtrr/generic.c
2049 */
2050 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2051 u64 start, u64 end)
2052 {
2053 int i;
2054 u64 base, mask;
2055 u8 prev_match, curr_match;
2056 int num_var_ranges = KVM_NR_VAR_MTRR;
2057
2058 if (!mtrr_state->enabled)
2059 return 0xFF;
2060
2061 /* Make end inclusive end, instead of exclusive */
2062 end--;
2063
2064 /* Look in fixed ranges. Just return the type as per start */
2065 if (mtrr_state->have_fixed && (start < 0x100000)) {
2066 int idx;
2067
2068 if (start < 0x80000) {
2069 idx = 0;
2070 idx += (start >> 16);
2071 return mtrr_state->fixed_ranges[idx];
2072 } else if (start < 0xC0000) {
2073 idx = 1 * 8;
2074 idx += ((start - 0x80000) >> 14);
2075 return mtrr_state->fixed_ranges[idx];
2076 } else if (start < 0x1000000) {
2077 idx = 3 * 8;
2078 idx += ((start - 0xC0000) >> 12);
2079 return mtrr_state->fixed_ranges[idx];
2080 }
2081 }
2082
2083 /*
2084 * Look in variable ranges
2085 * Look of multiple ranges matching this address and pick type
2086 * as per MTRR precedence
2087 */
2088 if (!(mtrr_state->enabled & 2))
2089 return mtrr_state->def_type;
2090
2091 prev_match = 0xFF;
2092 for (i = 0; i < num_var_ranges; ++i) {
2093 unsigned short start_state, end_state;
2094
2095 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2096 continue;
2097
2098 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2099 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2100 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2101 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2102
2103 start_state = ((start & mask) == (base & mask));
2104 end_state = ((end & mask) == (base & mask));
2105 if (start_state != end_state)
2106 return 0xFE;
2107
2108 if ((start & mask) != (base & mask))
2109 continue;
2110
2111 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2112 if (prev_match == 0xFF) {
2113 prev_match = curr_match;
2114 continue;
2115 }
2116
2117 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2118 curr_match == MTRR_TYPE_UNCACHABLE)
2119 return MTRR_TYPE_UNCACHABLE;
2120
2121 if ((prev_match == MTRR_TYPE_WRBACK &&
2122 curr_match == MTRR_TYPE_WRTHROUGH) ||
2123 (prev_match == MTRR_TYPE_WRTHROUGH &&
2124 curr_match == MTRR_TYPE_WRBACK)) {
2125 prev_match = MTRR_TYPE_WRTHROUGH;
2126 curr_match = MTRR_TYPE_WRTHROUGH;
2127 }
2128
2129 if (prev_match != curr_match)
2130 return MTRR_TYPE_UNCACHABLE;
2131 }
2132
2133 if (prev_match != 0xFF)
2134 return prev_match;
2135
2136 return mtrr_state->def_type;
2137 }
2138
2139 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2140 {
2141 u8 mtrr;
2142
2143 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2144 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2145 if (mtrr == 0xfe || mtrr == 0xff)
2146 mtrr = MTRR_TYPE_WRBACK;
2147 return mtrr;
2148 }
2149 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2150
2151 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2152 {
2153 trace_kvm_mmu_unsync_page(sp);
2154 ++vcpu->kvm->stat.mmu_unsync;
2155 sp->unsync = 1;
2156
2157 kvm_mmu_mark_parents_unsync(sp);
2158 }
2159
2160 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2161 {
2162 struct kvm_mmu_page *s;
2163 struct hlist_node *node;
2164
2165 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2166 if (s->unsync)
2167 continue;
2168 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2169 __kvm_unsync_page(vcpu, s);
2170 }
2171 }
2172
2173 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2174 bool can_unsync)
2175 {
2176 struct kvm_mmu_page *s;
2177 struct hlist_node *node;
2178 bool need_unsync = false;
2179
2180 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2181 if (!can_unsync)
2182 return 1;
2183
2184 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2185 return 1;
2186
2187 if (!need_unsync && !s->unsync) {
2188 need_unsync = true;
2189 }
2190 }
2191 if (need_unsync)
2192 kvm_unsync_pages(vcpu, gfn);
2193 return 0;
2194 }
2195
2196 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2197 unsigned pte_access, int user_fault,
2198 int write_fault, int level,
2199 gfn_t gfn, pfn_t pfn, bool speculative,
2200 bool can_unsync, bool host_writable)
2201 {
2202 u64 spte, entry = *sptep;
2203 int ret = 0;
2204
2205 if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2206 return 0;
2207
2208 spte = PT_PRESENT_MASK;
2209 if (!speculative)
2210 spte |= shadow_accessed_mask;
2211
2212 if (pte_access & ACC_EXEC_MASK)
2213 spte |= shadow_x_mask;
2214 else
2215 spte |= shadow_nx_mask;
2216 if (pte_access & ACC_USER_MASK)
2217 spte |= shadow_user_mask;
2218 if (level > PT_PAGE_TABLE_LEVEL)
2219 spte |= PT_PAGE_SIZE_MASK;
2220 if (tdp_enabled)
2221 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2222 kvm_is_mmio_pfn(pfn));
2223
2224 if (host_writable)
2225 spte |= SPTE_HOST_WRITEABLE;
2226 else
2227 pte_access &= ~ACC_WRITE_MASK;
2228
2229 spte |= (u64)pfn << PAGE_SHIFT;
2230
2231 if ((pte_access & ACC_WRITE_MASK)
2232 || (!vcpu->arch.mmu.direct_map && write_fault
2233 && !is_write_protection(vcpu) && !user_fault)) {
2234
2235 if (level > PT_PAGE_TABLE_LEVEL &&
2236 has_wrprotected_page(vcpu->kvm, gfn, level)) {
2237 ret = 1;
2238 drop_spte(vcpu->kvm, sptep);
2239 goto done;
2240 }
2241
2242 spte |= PT_WRITABLE_MASK;
2243
2244 if (!vcpu->arch.mmu.direct_map
2245 && !(pte_access & ACC_WRITE_MASK)) {
2246 spte &= ~PT_USER_MASK;
2247 /*
2248 * If we converted a user page to a kernel page,
2249 * so that the kernel can write to it when cr0.wp=0,
2250 * then we should prevent the kernel from executing it
2251 * if SMEP is enabled.
2252 */
2253 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2254 spte |= PT64_NX_MASK;
2255 }
2256
2257 /*
2258 * Optimization: for pte sync, if spte was writable the hash
2259 * lookup is unnecessary (and expensive). Write protection
2260 * is responsibility of mmu_get_page / kvm_sync_page.
2261 * Same reasoning can be applied to dirty page accounting.
2262 */
2263 if (!can_unsync && is_writable_pte(*sptep))
2264 goto set_pte;
2265
2266 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2267 pgprintk("%s: found shadow page for %llx, marking ro\n",
2268 __func__, gfn);
2269 ret = 1;
2270 pte_access &= ~ACC_WRITE_MASK;
2271 if (is_writable_pte(spte))
2272 spte &= ~PT_WRITABLE_MASK;
2273 }
2274 }
2275
2276 if (pte_access & ACC_WRITE_MASK)
2277 mark_page_dirty(vcpu->kvm, gfn);
2278
2279 set_pte:
2280 mmu_spte_update(sptep, spte);
2281 /*
2282 * If we overwrite a writable spte with a read-only one we
2283 * should flush remote TLBs. Otherwise rmap_write_protect
2284 * will find a read-only spte, even though the writable spte
2285 * might be cached on a CPU's TLB.
2286 */
2287 if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2288 kvm_flush_remote_tlbs(vcpu->kvm);
2289 done:
2290 return ret;
2291 }
2292
2293 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2294 unsigned pt_access, unsigned pte_access,
2295 int user_fault, int write_fault,
2296 int *emulate, int level, gfn_t gfn,
2297 pfn_t pfn, bool speculative,
2298 bool host_writable)
2299 {
2300 int was_rmapped = 0;
2301 int rmap_count;
2302
2303 pgprintk("%s: spte %llx access %x write_fault %d"
2304 " user_fault %d gfn %llx\n",
2305 __func__, *sptep, pt_access,
2306 write_fault, user_fault, gfn);
2307
2308 if (is_rmap_spte(*sptep)) {
2309 /*
2310 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2311 * the parent of the now unreachable PTE.
2312 */
2313 if (level > PT_PAGE_TABLE_LEVEL &&
2314 !is_large_pte(*sptep)) {
2315 struct kvm_mmu_page *child;
2316 u64 pte = *sptep;
2317
2318 child = page_header(pte & PT64_BASE_ADDR_MASK);
2319 drop_parent_pte(child, sptep);
2320 kvm_flush_remote_tlbs(vcpu->kvm);
2321 } else if (pfn != spte_to_pfn(*sptep)) {
2322 pgprintk("hfn old %llx new %llx\n",
2323 spte_to_pfn(*sptep), pfn);
2324 drop_spte(vcpu->kvm, sptep);
2325 kvm_flush_remote_tlbs(vcpu->kvm);
2326 } else
2327 was_rmapped = 1;
2328 }
2329
2330 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2331 level, gfn, pfn, speculative, true,
2332 host_writable)) {
2333 if (write_fault)
2334 *emulate = 1;
2335 kvm_mmu_flush_tlb(vcpu);
2336 }
2337
2338 if (unlikely(is_mmio_spte(*sptep) && emulate))
2339 *emulate = 1;
2340
2341 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2342 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2343 is_large_pte(*sptep)? "2MB" : "4kB",
2344 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2345 *sptep, sptep);
2346 if (!was_rmapped && is_large_pte(*sptep))
2347 ++vcpu->kvm->stat.lpages;
2348
2349 if (is_shadow_present_pte(*sptep)) {
2350 page_header_update_slot(vcpu->kvm, sptep, gfn);
2351 if (!was_rmapped) {
2352 rmap_count = rmap_add(vcpu, sptep, gfn);
2353 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2354 rmap_recycle(vcpu, sptep, gfn);
2355 }
2356 }
2357 kvm_release_pfn_clean(pfn);
2358 }
2359
2360 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2361 {
2362 }
2363
2364 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2365 bool no_dirty_log)
2366 {
2367 struct kvm_memory_slot *slot;
2368 unsigned long hva;
2369
2370 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2371 if (!slot) {
2372 get_page(fault_page);
2373 return page_to_pfn(fault_page);
2374 }
2375
2376 hva = gfn_to_hva_memslot(slot, gfn);
2377
2378 return hva_to_pfn_atomic(vcpu->kvm, hva);
2379 }
2380
2381 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2382 struct kvm_mmu_page *sp,
2383 u64 *start, u64 *end)
2384 {
2385 struct page *pages[PTE_PREFETCH_NUM];
2386 unsigned access = sp->role.access;
2387 int i, ret;
2388 gfn_t gfn;
2389
2390 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2391 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2392 return -1;
2393
2394 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2395 if (ret <= 0)
2396 return -1;
2397
2398 for (i = 0; i < ret; i++, gfn++, start++)
2399 mmu_set_spte(vcpu, start, ACC_ALL,
2400 access, 0, 0, NULL,
2401 sp->role.level, gfn,
2402 page_to_pfn(pages[i]), true, true);
2403
2404 return 0;
2405 }
2406
2407 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2408 struct kvm_mmu_page *sp, u64 *sptep)
2409 {
2410 u64 *spte, *start = NULL;
2411 int i;
2412
2413 WARN_ON(!sp->role.direct);
2414
2415 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2416 spte = sp->spt + i;
2417
2418 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2419 if (is_shadow_present_pte(*spte) || spte == sptep) {
2420 if (!start)
2421 continue;
2422 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2423 break;
2424 start = NULL;
2425 } else if (!start)
2426 start = spte;
2427 }
2428 }
2429
2430 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2431 {
2432 struct kvm_mmu_page *sp;
2433
2434 /*
2435 * Since it's no accessed bit on EPT, it's no way to
2436 * distinguish between actually accessed translations
2437 * and prefetched, so disable pte prefetch if EPT is
2438 * enabled.
2439 */
2440 if (!shadow_accessed_mask)
2441 return;
2442
2443 sp = page_header(__pa(sptep));
2444 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2445 return;
2446
2447 __direct_pte_prefetch(vcpu, sp, sptep);
2448 }
2449
2450 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2451 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2452 bool prefault)
2453 {
2454 struct kvm_shadow_walk_iterator iterator;
2455 struct kvm_mmu_page *sp;
2456 int emulate = 0;
2457 gfn_t pseudo_gfn;
2458
2459 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2460 if (iterator.level == level) {
2461 unsigned pte_access = ACC_ALL;
2462
2463 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2464 0, write, &emulate,
2465 level, gfn, pfn, prefault, map_writable);
2466 direct_pte_prefetch(vcpu, iterator.sptep);
2467 ++vcpu->stat.pf_fixed;
2468 break;
2469 }
2470
2471 if (!is_shadow_present_pte(*iterator.sptep)) {
2472 u64 base_addr = iterator.addr;
2473
2474 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2475 pseudo_gfn = base_addr >> PAGE_SHIFT;
2476 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2477 iterator.level - 1,
2478 1, ACC_ALL, iterator.sptep);
2479 if (!sp) {
2480 pgprintk("nonpaging_map: ENOMEM\n");
2481 kvm_release_pfn_clean(pfn);
2482 return -ENOMEM;
2483 }
2484
2485 mmu_spte_set(iterator.sptep,
2486 __pa(sp->spt)
2487 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2488 | shadow_user_mask | shadow_x_mask
2489 | shadow_accessed_mask);
2490 }
2491 }
2492 return emulate;
2493 }
2494
2495 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2496 {
2497 siginfo_t info;
2498
2499 info.si_signo = SIGBUS;
2500 info.si_errno = 0;
2501 info.si_code = BUS_MCEERR_AR;
2502 info.si_addr = (void __user *)address;
2503 info.si_addr_lsb = PAGE_SHIFT;
2504
2505 send_sig_info(SIGBUS, &info, tsk);
2506 }
2507
2508 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2509 {
2510 kvm_release_pfn_clean(pfn);
2511 if (is_hwpoison_pfn(pfn)) {
2512 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2513 return 0;
2514 }
2515
2516 return -EFAULT;
2517 }
2518
2519 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2520 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2521 {
2522 pfn_t pfn = *pfnp;
2523 gfn_t gfn = *gfnp;
2524 int level = *levelp;
2525
2526 /*
2527 * Check if it's a transparent hugepage. If this would be an
2528 * hugetlbfs page, level wouldn't be set to
2529 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2530 * here.
2531 */
2532 if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2533 level == PT_PAGE_TABLE_LEVEL &&
2534 PageTransCompound(pfn_to_page(pfn)) &&
2535 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2536 unsigned long mask;
2537 /*
2538 * mmu_notifier_retry was successful and we hold the
2539 * mmu_lock here, so the pmd can't become splitting
2540 * from under us, and in turn
2541 * __split_huge_page_refcount() can't run from under
2542 * us and we can safely transfer the refcount from
2543 * PG_tail to PG_head as we switch the pfn to tail to
2544 * head.
2545 */
2546 *levelp = level = PT_DIRECTORY_LEVEL;
2547 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2548 VM_BUG_ON((gfn & mask) != (pfn & mask));
2549 if (pfn & mask) {
2550 gfn &= ~mask;
2551 *gfnp = gfn;
2552 kvm_release_pfn_clean(pfn);
2553 pfn &= ~mask;
2554 if (!get_page_unless_zero(pfn_to_page(pfn)))
2555 BUG();
2556 *pfnp = pfn;
2557 }
2558 }
2559 }
2560
2561 static bool mmu_invalid_pfn(pfn_t pfn)
2562 {
2563 return unlikely(is_invalid_pfn(pfn));
2564 }
2565
2566 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2567 pfn_t pfn, unsigned access, int *ret_val)
2568 {
2569 bool ret = true;
2570
2571 /* The pfn is invalid, report the error! */
2572 if (unlikely(is_invalid_pfn(pfn))) {
2573 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2574 goto exit;
2575 }
2576
2577 if (unlikely(is_noslot_pfn(pfn)))
2578 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2579
2580 ret = false;
2581 exit:
2582 return ret;
2583 }
2584
2585 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2586 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2587
2588 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2589 bool prefault)
2590 {
2591 int r;
2592 int level;
2593 int force_pt_level;
2594 pfn_t pfn;
2595 unsigned long mmu_seq;
2596 bool map_writable;
2597
2598 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2599 if (likely(!force_pt_level)) {
2600 level = mapping_level(vcpu, gfn);
2601 /*
2602 * This path builds a PAE pagetable - so we can map
2603 * 2mb pages at maximum. Therefore check if the level
2604 * is larger than that.
2605 */
2606 if (level > PT_DIRECTORY_LEVEL)
2607 level = PT_DIRECTORY_LEVEL;
2608
2609 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2610 } else
2611 level = PT_PAGE_TABLE_LEVEL;
2612
2613 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2614 smp_rmb();
2615
2616 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2617 return 0;
2618
2619 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2620 return r;
2621
2622 spin_lock(&vcpu->kvm->mmu_lock);
2623 if (mmu_notifier_retry(vcpu, mmu_seq))
2624 goto out_unlock;
2625 kvm_mmu_free_some_pages(vcpu);
2626 if (likely(!force_pt_level))
2627 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2628 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2629 prefault);
2630 spin_unlock(&vcpu->kvm->mmu_lock);
2631
2632
2633 return r;
2634
2635 out_unlock:
2636 spin_unlock(&vcpu->kvm->mmu_lock);
2637 kvm_release_pfn_clean(pfn);
2638 return 0;
2639 }
2640
2641
2642 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2643 {
2644 int i;
2645 struct kvm_mmu_page *sp;
2646 LIST_HEAD(invalid_list);
2647
2648 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2649 return;
2650 spin_lock(&vcpu->kvm->mmu_lock);
2651 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2652 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2653 vcpu->arch.mmu.direct_map)) {
2654 hpa_t root = vcpu->arch.mmu.root_hpa;
2655
2656 sp = page_header(root);
2657 --sp->root_count;
2658 if (!sp->root_count && sp->role.invalid) {
2659 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2660 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2661 }
2662 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2663 spin_unlock(&vcpu->kvm->mmu_lock);
2664 return;
2665 }
2666 for (i = 0; i < 4; ++i) {
2667 hpa_t root = vcpu->arch.mmu.pae_root[i];
2668
2669 if (root) {
2670 root &= PT64_BASE_ADDR_MASK;
2671 sp = page_header(root);
2672 --sp->root_count;
2673 if (!sp->root_count && sp->role.invalid)
2674 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2675 &invalid_list);
2676 }
2677 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2678 }
2679 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2680 spin_unlock(&vcpu->kvm->mmu_lock);
2681 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2682 }
2683
2684 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2685 {
2686 int ret = 0;
2687
2688 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2689 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2690 ret = 1;
2691 }
2692
2693 return ret;
2694 }
2695
2696 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2697 {
2698 struct kvm_mmu_page *sp;
2699 unsigned i;
2700
2701 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2702 spin_lock(&vcpu->kvm->mmu_lock);
2703 kvm_mmu_free_some_pages(vcpu);
2704 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2705 1, ACC_ALL, NULL);
2706 ++sp->root_count;
2707 spin_unlock(&vcpu->kvm->mmu_lock);
2708 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2709 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2710 for (i = 0; i < 4; ++i) {
2711 hpa_t root = vcpu->arch.mmu.pae_root[i];
2712
2713 ASSERT(!VALID_PAGE(root));
2714 spin_lock(&vcpu->kvm->mmu_lock);
2715 kvm_mmu_free_some_pages(vcpu);
2716 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2717 i << 30,
2718 PT32_ROOT_LEVEL, 1, ACC_ALL,
2719 NULL);
2720 root = __pa(sp->spt);
2721 ++sp->root_count;
2722 spin_unlock(&vcpu->kvm->mmu_lock);
2723 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2724 }
2725 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2726 } else
2727 BUG();
2728
2729 return 0;
2730 }
2731
2732 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2733 {
2734 struct kvm_mmu_page *sp;
2735 u64 pdptr, pm_mask;
2736 gfn_t root_gfn;
2737 int i;
2738
2739 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2740
2741 if (mmu_check_root(vcpu, root_gfn))
2742 return 1;
2743
2744 /*
2745 * Do we shadow a long mode page table? If so we need to
2746 * write-protect the guests page table root.
2747 */
2748 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2749 hpa_t root = vcpu->arch.mmu.root_hpa;
2750
2751 ASSERT(!VALID_PAGE(root));
2752
2753 spin_lock(&vcpu->kvm->mmu_lock);
2754 kvm_mmu_free_some_pages(vcpu);
2755 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2756 0, ACC_ALL, NULL);
2757 root = __pa(sp->spt);
2758 ++sp->root_count;
2759 spin_unlock(&vcpu->kvm->mmu_lock);
2760 vcpu->arch.mmu.root_hpa = root;
2761 return 0;
2762 }
2763
2764 /*
2765 * We shadow a 32 bit page table. This may be a legacy 2-level
2766 * or a PAE 3-level page table. In either case we need to be aware that
2767 * the shadow page table may be a PAE or a long mode page table.
2768 */
2769 pm_mask = PT_PRESENT_MASK;
2770 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2771 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2772
2773 for (i = 0; i < 4; ++i) {
2774 hpa_t root = vcpu->arch.mmu.pae_root[i];
2775
2776 ASSERT(!VALID_PAGE(root));
2777 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2778 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
2779 if (!is_present_gpte(pdptr)) {
2780 vcpu->arch.mmu.pae_root[i] = 0;
2781 continue;
2782 }
2783 root_gfn = pdptr >> PAGE_SHIFT;
2784 if (mmu_check_root(vcpu, root_gfn))
2785 return 1;
2786 }
2787 spin_lock(&vcpu->kvm->mmu_lock);
2788 kvm_mmu_free_some_pages(vcpu);
2789 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2790 PT32_ROOT_LEVEL, 0,
2791 ACC_ALL, NULL);
2792 root = __pa(sp->spt);
2793 ++sp->root_count;
2794 spin_unlock(&vcpu->kvm->mmu_lock);
2795
2796 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2797 }
2798 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2799
2800 /*
2801 * If we shadow a 32 bit page table with a long mode page
2802 * table we enter this path.
2803 */
2804 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2805 if (vcpu->arch.mmu.lm_root == NULL) {
2806 /*
2807 * The additional page necessary for this is only
2808 * allocated on demand.
2809 */
2810
2811 u64 *lm_root;
2812
2813 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2814 if (lm_root == NULL)
2815 return 1;
2816
2817 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2818
2819 vcpu->arch.mmu.lm_root = lm_root;
2820 }
2821
2822 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2823 }
2824
2825 return 0;
2826 }
2827
2828 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2829 {
2830 if (vcpu->arch.mmu.direct_map)
2831 return mmu_alloc_direct_roots(vcpu);
2832 else
2833 return mmu_alloc_shadow_roots(vcpu);
2834 }
2835
2836 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2837 {
2838 int i;
2839 struct kvm_mmu_page *sp;
2840
2841 if (vcpu->arch.mmu.direct_map)
2842 return;
2843
2844 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2845 return;
2846
2847 vcpu_clear_mmio_info(vcpu, ~0ul);
2848 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2849 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2850 hpa_t root = vcpu->arch.mmu.root_hpa;
2851 sp = page_header(root);
2852 mmu_sync_children(vcpu, sp);
2853 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2854 return;
2855 }
2856 for (i = 0; i < 4; ++i) {
2857 hpa_t root = vcpu->arch.mmu.pae_root[i];
2858
2859 if (root && VALID_PAGE(root)) {
2860 root &= PT64_BASE_ADDR_MASK;
2861 sp = page_header(root);
2862 mmu_sync_children(vcpu, sp);
2863 }
2864 }
2865 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2866 }
2867
2868 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2869 {
2870 spin_lock(&vcpu->kvm->mmu_lock);
2871 mmu_sync_roots(vcpu);
2872 spin_unlock(&vcpu->kvm->mmu_lock);
2873 }
2874
2875 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2876 u32 access, struct x86_exception *exception)
2877 {
2878 if (exception)
2879 exception->error_code = 0;
2880 return vaddr;
2881 }
2882
2883 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2884 u32 access,
2885 struct x86_exception *exception)
2886 {
2887 if (exception)
2888 exception->error_code = 0;
2889 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2890 }
2891
2892 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2893 {
2894 if (direct)
2895 return vcpu_match_mmio_gpa(vcpu, addr);
2896
2897 return vcpu_match_mmio_gva(vcpu, addr);
2898 }
2899
2900
2901 /*
2902 * On direct hosts, the last spte is only allows two states
2903 * for mmio page fault:
2904 * - It is the mmio spte
2905 * - It is zapped or it is being zapped.
2906 *
2907 * This function completely checks the spte when the last spte
2908 * is not the mmio spte.
2909 */
2910 static bool check_direct_spte_mmio_pf(u64 spte)
2911 {
2912 return __check_direct_spte_mmio_pf(spte);
2913 }
2914
2915 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
2916 {
2917 struct kvm_shadow_walk_iterator iterator;
2918 u64 spte = 0ull;
2919
2920 walk_shadow_page_lockless_begin(vcpu);
2921 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
2922 if (!is_shadow_present_pte(spte))
2923 break;
2924 walk_shadow_page_lockless_end(vcpu);
2925
2926 return spte;
2927 }
2928
2929 /*
2930 * If it is a real mmio page fault, return 1 and emulat the instruction
2931 * directly, return 0 to let CPU fault again on the address, -1 is
2932 * returned if bug is detected.
2933 */
2934 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2935 {
2936 u64 spte;
2937
2938 if (quickly_check_mmio_pf(vcpu, addr, direct))
2939 return 1;
2940
2941 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
2942
2943 if (is_mmio_spte(spte)) {
2944 gfn_t gfn = get_mmio_spte_gfn(spte);
2945 unsigned access = get_mmio_spte_access(spte);
2946
2947 if (direct)
2948 addr = 0;
2949
2950 trace_handle_mmio_page_fault(addr, gfn, access);
2951 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
2952 return 1;
2953 }
2954
2955 /*
2956 * It's ok if the gva is remapped by other cpus on shadow guest,
2957 * it's a BUG if the gfn is not a mmio page.
2958 */
2959 if (direct && !check_direct_spte_mmio_pf(spte))
2960 return -1;
2961
2962 /*
2963 * If the page table is zapped by other cpus, let CPU fault again on
2964 * the address.
2965 */
2966 return 0;
2967 }
2968 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
2969
2970 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
2971 u32 error_code, bool direct)
2972 {
2973 int ret;
2974
2975 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
2976 WARN_ON(ret < 0);
2977 return ret;
2978 }
2979
2980 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2981 u32 error_code, bool prefault)
2982 {
2983 gfn_t gfn;
2984 int r;
2985
2986 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2987
2988 if (unlikely(error_code & PFERR_RSVD_MASK))
2989 return handle_mmio_page_fault(vcpu, gva, error_code, true);
2990
2991 r = mmu_topup_memory_caches(vcpu);
2992 if (r)
2993 return r;
2994
2995 ASSERT(vcpu);
2996 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2997
2998 gfn = gva >> PAGE_SHIFT;
2999
3000 return nonpaging_map(vcpu, gva & PAGE_MASK,
3001 error_code & PFERR_WRITE_MASK, gfn, prefault);
3002 }
3003
3004 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3005 {
3006 struct kvm_arch_async_pf arch;
3007
3008 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3009 arch.gfn = gfn;
3010 arch.direct_map = vcpu->arch.mmu.direct_map;
3011 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3012
3013 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3014 }
3015
3016 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3017 {
3018 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3019 kvm_event_needs_reinjection(vcpu)))
3020 return false;
3021
3022 return kvm_x86_ops->interrupt_allowed(vcpu);
3023 }
3024
3025 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3026 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3027 {
3028 bool async;
3029
3030 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3031
3032 if (!async)
3033 return false; /* *pfn has correct page already */
3034
3035 put_page(pfn_to_page(*pfn));
3036
3037 if (!prefault && can_do_async_pf(vcpu)) {
3038 trace_kvm_try_async_get_page(gva, gfn);
3039 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3040 trace_kvm_async_pf_doublefault(gva, gfn);
3041 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3042 return true;
3043 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3044 return true;
3045 }
3046
3047 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3048
3049 return false;
3050 }
3051
3052 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3053 bool prefault)
3054 {
3055 pfn_t pfn;
3056 int r;
3057 int level;
3058 int force_pt_level;
3059 gfn_t gfn = gpa >> PAGE_SHIFT;
3060 unsigned long mmu_seq;
3061 int write = error_code & PFERR_WRITE_MASK;
3062 bool map_writable;
3063
3064 ASSERT(vcpu);
3065 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3066
3067 if (unlikely(error_code & PFERR_RSVD_MASK))
3068 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3069
3070 r = mmu_topup_memory_caches(vcpu);
3071 if (r)
3072 return r;
3073
3074 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3075 if (likely(!force_pt_level)) {
3076 level = mapping_level(vcpu, gfn);
3077 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3078 } else
3079 level = PT_PAGE_TABLE_LEVEL;
3080
3081 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3082 smp_rmb();
3083
3084 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3085 return 0;
3086
3087 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3088 return r;
3089
3090 spin_lock(&vcpu->kvm->mmu_lock);
3091 if (mmu_notifier_retry(vcpu, mmu_seq))
3092 goto out_unlock;
3093 kvm_mmu_free_some_pages(vcpu);
3094 if (likely(!force_pt_level))
3095 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3096 r = __direct_map(vcpu, gpa, write, map_writable,
3097 level, gfn, pfn, prefault);
3098 spin_unlock(&vcpu->kvm->mmu_lock);
3099
3100 return r;
3101
3102 out_unlock:
3103 spin_unlock(&vcpu->kvm->mmu_lock);
3104 kvm_release_pfn_clean(pfn);
3105 return 0;
3106 }
3107
3108 static void nonpaging_free(struct kvm_vcpu *vcpu)
3109 {
3110 mmu_free_roots(vcpu);
3111 }
3112
3113 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3114 struct kvm_mmu *context)
3115 {
3116 context->new_cr3 = nonpaging_new_cr3;
3117 context->page_fault = nonpaging_page_fault;
3118 context->gva_to_gpa = nonpaging_gva_to_gpa;
3119 context->free = nonpaging_free;
3120 context->sync_page = nonpaging_sync_page;
3121 context->invlpg = nonpaging_invlpg;
3122 context->update_pte = nonpaging_update_pte;
3123 context->root_level = 0;
3124 context->shadow_root_level = PT32E_ROOT_LEVEL;
3125 context->root_hpa = INVALID_PAGE;
3126 context->direct_map = true;
3127 context->nx = false;
3128 return 0;
3129 }
3130
3131 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3132 {
3133 ++vcpu->stat.tlb_flush;
3134 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3135 }
3136
3137 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3138 {
3139 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3140 mmu_free_roots(vcpu);
3141 }
3142
3143 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3144 {
3145 return kvm_read_cr3(vcpu);
3146 }
3147
3148 static void inject_page_fault(struct kvm_vcpu *vcpu,
3149 struct x86_exception *fault)
3150 {
3151 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3152 }
3153
3154 static void paging_free(struct kvm_vcpu *vcpu)
3155 {
3156 nonpaging_free(vcpu);
3157 }
3158
3159 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3160 {
3161 int bit7;
3162
3163 bit7 = (gpte >> 7) & 1;
3164 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3165 }
3166
3167 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3168 int *nr_present)
3169 {
3170 if (unlikely(is_mmio_spte(*sptep))) {
3171 if (gfn != get_mmio_spte_gfn(*sptep)) {
3172 mmu_spte_clear_no_track(sptep);
3173 return true;
3174 }
3175
3176 (*nr_present)++;
3177 mark_mmio_spte(sptep, gfn, access);
3178 return true;
3179 }
3180
3181 return false;
3182 }
3183
3184 #define PTTYPE 64
3185 #include "paging_tmpl.h"
3186 #undef PTTYPE
3187
3188 #define PTTYPE 32
3189 #include "paging_tmpl.h"
3190 #undef PTTYPE
3191
3192 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3193 struct kvm_mmu *context,
3194 int level)
3195 {
3196 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3197 u64 exb_bit_rsvd = 0;
3198
3199 if (!context->nx)
3200 exb_bit_rsvd = rsvd_bits(63, 63);
3201 switch (level) {
3202 case PT32_ROOT_LEVEL:
3203 /* no rsvd bits for 2 level 4K page table entries */
3204 context->rsvd_bits_mask[0][1] = 0;
3205 context->rsvd_bits_mask[0][0] = 0;
3206 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3207
3208 if (!is_pse(vcpu)) {
3209 context->rsvd_bits_mask[1][1] = 0;
3210 break;
3211 }
3212
3213 if (is_cpuid_PSE36())
3214 /* 36bits PSE 4MB page */
3215 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3216 else
3217 /* 32 bits PSE 4MB page */
3218 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3219 break;
3220 case PT32E_ROOT_LEVEL:
3221 context->rsvd_bits_mask[0][2] =
3222 rsvd_bits(maxphyaddr, 63) |
3223 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3224 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3225 rsvd_bits(maxphyaddr, 62); /* PDE */
3226 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3227 rsvd_bits(maxphyaddr, 62); /* PTE */
3228 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3229 rsvd_bits(maxphyaddr, 62) |
3230 rsvd_bits(13, 20); /* large page */
3231 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3232 break;
3233 case PT64_ROOT_LEVEL:
3234 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3235 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3236 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3237 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3238 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3239 rsvd_bits(maxphyaddr, 51);
3240 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3241 rsvd_bits(maxphyaddr, 51);
3242 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3243 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3244 rsvd_bits(maxphyaddr, 51) |
3245 rsvd_bits(13, 29);
3246 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3247 rsvd_bits(maxphyaddr, 51) |
3248 rsvd_bits(13, 20); /* large page */
3249 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3250 break;
3251 }
3252 }
3253
3254 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3255 struct kvm_mmu *context,
3256 int level)
3257 {
3258 context->nx = is_nx(vcpu);
3259
3260 reset_rsvds_bits_mask(vcpu, context, level);
3261
3262 ASSERT(is_pae(vcpu));
3263 context->new_cr3 = paging_new_cr3;
3264 context->page_fault = paging64_page_fault;
3265 context->gva_to_gpa = paging64_gva_to_gpa;
3266 context->sync_page = paging64_sync_page;
3267 context->invlpg = paging64_invlpg;
3268 context->update_pte = paging64_update_pte;
3269 context->free = paging_free;
3270 context->root_level = level;
3271 context->shadow_root_level = level;
3272 context->root_hpa = INVALID_PAGE;
3273 context->direct_map = false;
3274 return 0;
3275 }
3276
3277 static int paging64_init_context(struct kvm_vcpu *vcpu,
3278 struct kvm_mmu *context)
3279 {
3280 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3281 }
3282
3283 static int paging32_init_context(struct kvm_vcpu *vcpu,
3284 struct kvm_mmu *context)
3285 {
3286 context->nx = false;
3287
3288 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3289
3290 context->new_cr3 = paging_new_cr3;
3291 context->page_fault = paging32_page_fault;
3292 context->gva_to_gpa = paging32_gva_to_gpa;
3293 context->free = paging_free;
3294 context->sync_page = paging32_sync_page;
3295 context->invlpg = paging32_invlpg;
3296 context->update_pte = paging32_update_pte;
3297 context->root_level = PT32_ROOT_LEVEL;
3298 context->shadow_root_level = PT32E_ROOT_LEVEL;
3299 context->root_hpa = INVALID_PAGE;
3300 context->direct_map = false;
3301 return 0;
3302 }
3303
3304 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3305 struct kvm_mmu *context)
3306 {
3307 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3308 }
3309
3310 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3311 {
3312 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3313
3314 context->base_role.word = 0;
3315 context->new_cr3 = nonpaging_new_cr3;
3316 context->page_fault = tdp_page_fault;
3317 context->free = nonpaging_free;
3318 context->sync_page = nonpaging_sync_page;
3319 context->invlpg = nonpaging_invlpg;
3320 context->update_pte = nonpaging_update_pte;
3321 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3322 context->root_hpa = INVALID_PAGE;
3323 context->direct_map = true;
3324 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3325 context->get_cr3 = get_cr3;
3326 context->get_pdptr = kvm_pdptr_read;
3327 context->inject_page_fault = kvm_inject_page_fault;
3328 context->nx = is_nx(vcpu);
3329
3330 if (!is_paging(vcpu)) {
3331 context->nx = false;
3332 context->gva_to_gpa = nonpaging_gva_to_gpa;
3333 context->root_level = 0;
3334 } else if (is_long_mode(vcpu)) {
3335 context->nx = is_nx(vcpu);
3336 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3337 context->gva_to_gpa = paging64_gva_to_gpa;
3338 context->root_level = PT64_ROOT_LEVEL;
3339 } else if (is_pae(vcpu)) {
3340 context->nx = is_nx(vcpu);
3341 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3342 context->gva_to_gpa = paging64_gva_to_gpa;
3343 context->root_level = PT32E_ROOT_LEVEL;
3344 } else {
3345 context->nx = false;
3346 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3347 context->gva_to_gpa = paging32_gva_to_gpa;
3348 context->root_level = PT32_ROOT_LEVEL;
3349 }
3350
3351 return 0;
3352 }
3353
3354 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3355 {
3356 int r;
3357 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3358 ASSERT(vcpu);
3359 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3360
3361 if (!is_paging(vcpu))
3362 r = nonpaging_init_context(vcpu, context);
3363 else if (is_long_mode(vcpu))
3364 r = paging64_init_context(vcpu, context);
3365 else if (is_pae(vcpu))
3366 r = paging32E_init_context(vcpu, context);
3367 else
3368 r = paging32_init_context(vcpu, context);
3369
3370 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3371 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3372 vcpu->arch.mmu.base_role.smep_andnot_wp
3373 = smep && !is_write_protection(vcpu);
3374
3375 return r;
3376 }
3377 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3378
3379 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3380 {
3381 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3382
3383 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3384 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3385 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3386 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3387
3388 return r;
3389 }
3390
3391 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3392 {
3393 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3394
3395 g_context->get_cr3 = get_cr3;
3396 g_context->get_pdptr = kvm_pdptr_read;
3397 g_context->inject_page_fault = kvm_inject_page_fault;
3398
3399 /*
3400 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3401 * translation of l2_gpa to l1_gpa addresses is done using the
3402 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3403 * functions between mmu and nested_mmu are swapped.
3404 */
3405 if (!is_paging(vcpu)) {
3406 g_context->nx = false;
3407 g_context->root_level = 0;
3408 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3409 } else if (is_long_mode(vcpu)) {
3410 g_context->nx = is_nx(vcpu);
3411 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3412 g_context->root_level = PT64_ROOT_LEVEL;
3413 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3414 } else if (is_pae(vcpu)) {
3415 g_context->nx = is_nx(vcpu);
3416 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3417 g_context->root_level = PT32E_ROOT_LEVEL;
3418 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3419 } else {
3420 g_context->nx = false;
3421 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3422 g_context->root_level = PT32_ROOT_LEVEL;
3423 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3424 }
3425
3426 return 0;
3427 }
3428
3429 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3430 {
3431 if (mmu_is_nested(vcpu))
3432 return init_kvm_nested_mmu(vcpu);
3433 else if (tdp_enabled)
3434 return init_kvm_tdp_mmu(vcpu);
3435 else
3436 return init_kvm_softmmu(vcpu);
3437 }
3438
3439 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3440 {
3441 ASSERT(vcpu);
3442 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3443 /* mmu.free() should set root_hpa = INVALID_PAGE */
3444 vcpu->arch.mmu.free(vcpu);
3445 }
3446
3447 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3448 {
3449 destroy_kvm_mmu(vcpu);
3450 return init_kvm_mmu(vcpu);
3451 }
3452 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3453
3454 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3455 {
3456 int r;
3457
3458 r = mmu_topup_memory_caches(vcpu);
3459 if (r)
3460 goto out;
3461 r = mmu_alloc_roots(vcpu);
3462 spin_lock(&vcpu->kvm->mmu_lock);
3463 mmu_sync_roots(vcpu);
3464 spin_unlock(&vcpu->kvm->mmu_lock);
3465 if (r)
3466 goto out;
3467 /* set_cr3() should ensure TLB has been flushed */
3468 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3469 out:
3470 return r;
3471 }
3472 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3473
3474 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3475 {
3476 mmu_free_roots(vcpu);
3477 }
3478 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3479
3480 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3481 struct kvm_mmu_page *sp, u64 *spte,
3482 const void *new)
3483 {
3484 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3485 ++vcpu->kvm->stat.mmu_pde_zapped;
3486 return;
3487 }
3488
3489 ++vcpu->kvm->stat.mmu_pte_updated;
3490 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3491 }
3492
3493 static bool need_remote_flush(u64 old, u64 new)
3494 {
3495 if (!is_shadow_present_pte(old))
3496 return false;
3497 if (!is_shadow_present_pte(new))
3498 return true;
3499 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3500 return true;
3501 old ^= PT64_NX_MASK;
3502 new ^= PT64_NX_MASK;
3503 return (old & ~new & PT64_PERM_MASK) != 0;
3504 }
3505
3506 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3507 bool remote_flush, bool local_flush)
3508 {
3509 if (zap_page)
3510 return;
3511
3512 if (remote_flush)
3513 kvm_flush_remote_tlbs(vcpu->kvm);
3514 else if (local_flush)
3515 kvm_mmu_flush_tlb(vcpu);
3516 }
3517
3518 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3519 const u8 *new, int *bytes)
3520 {
3521 u64 gentry;
3522 int r;
3523
3524 /*
3525 * Assume that the pte write on a page table of the same type
3526 * as the current vcpu paging mode since we update the sptes only
3527 * when they have the same mode.
3528 */
3529 if (is_pae(vcpu) && *bytes == 4) {
3530 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3531 *gpa &= ~(gpa_t)7;
3532 *bytes = 8;
3533 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
3534 if (r)
3535 gentry = 0;
3536 new = (const u8 *)&gentry;
3537 }
3538
3539 switch (*bytes) {
3540 case 4:
3541 gentry = *(const u32 *)new;
3542 break;
3543 case 8:
3544 gentry = *(const u64 *)new;
3545 break;
3546 default:
3547 gentry = 0;
3548 break;
3549 }
3550
3551 return gentry;
3552 }
3553
3554 /*
3555 * If we're seeing too many writes to a page, it may no longer be a page table,
3556 * or we may be forking, in which case it is better to unmap the page.
3557 */
3558 static bool detect_write_flooding(struct kvm_mmu_page *sp, u64 *spte)
3559 {
3560 /*
3561 * Skip write-flooding detected for the sp whose level is 1, because
3562 * it can become unsync, then the guest page is not write-protected.
3563 */
3564 if (sp->role.level == 1)
3565 return false;
3566
3567 return ++sp->write_flooding_count >= 3;
3568 }
3569
3570 /*
3571 * Misaligned accesses are too much trouble to fix up; also, they usually
3572 * indicate a page is not used as a page table.
3573 */
3574 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3575 int bytes)
3576 {
3577 unsigned offset, pte_size, misaligned;
3578
3579 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3580 gpa, bytes, sp->role.word);
3581
3582 offset = offset_in_page(gpa);
3583 pte_size = sp->role.cr4_pae ? 8 : 4;
3584
3585 /*
3586 * Sometimes, the OS only writes the last one bytes to update status
3587 * bits, for example, in linux, andb instruction is used in clear_bit().
3588 */
3589 if (!(offset & (pte_size - 1)) && bytes == 1)
3590 return false;
3591
3592 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3593 misaligned |= bytes < 4;
3594
3595 return misaligned;
3596 }
3597
3598 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3599 {
3600 unsigned page_offset, quadrant;
3601 u64 *spte;
3602 int level;
3603
3604 page_offset = offset_in_page(gpa);
3605 level = sp->role.level;
3606 *nspte = 1;
3607 if (!sp->role.cr4_pae) {
3608 page_offset <<= 1; /* 32->64 */
3609 /*
3610 * A 32-bit pde maps 4MB while the shadow pdes map
3611 * only 2MB. So we need to double the offset again
3612 * and zap two pdes instead of one.
3613 */
3614 if (level == PT32_ROOT_LEVEL) {
3615 page_offset &= ~7; /* kill rounding error */
3616 page_offset <<= 1;
3617 *nspte = 2;
3618 }
3619 quadrant = page_offset >> PAGE_SHIFT;
3620 page_offset &= ~PAGE_MASK;
3621 if (quadrant != sp->role.quadrant)
3622 return NULL;
3623 }
3624
3625 spte = &sp->spt[page_offset / sizeof(*spte)];
3626 return spte;
3627 }
3628
3629 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3630 const u8 *new, int bytes)
3631 {
3632 gfn_t gfn = gpa >> PAGE_SHIFT;
3633 union kvm_mmu_page_role mask = { .word = 0 };
3634 struct kvm_mmu_page *sp;
3635 struct hlist_node *node;
3636 LIST_HEAD(invalid_list);
3637 u64 entry, gentry, *spte;
3638 int npte;
3639 bool remote_flush, local_flush, zap_page;
3640
3641 /*
3642 * If we don't have indirect shadow pages, it means no page is
3643 * write-protected, so we can exit simply.
3644 */
3645 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3646 return;
3647
3648 zap_page = remote_flush = local_flush = false;
3649
3650 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3651
3652 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3653
3654 /*
3655 * No need to care whether allocation memory is successful
3656 * or not since pte prefetch is skiped if it does not have
3657 * enough objects in the cache.
3658 */
3659 mmu_topup_memory_caches(vcpu);
3660
3661 spin_lock(&vcpu->kvm->mmu_lock);
3662 ++vcpu->kvm->stat.mmu_pte_write;
3663 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3664
3665 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3666 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3667 spte = get_written_sptes(sp, gpa, &npte);
3668
3669 if (detect_write_misaligned(sp, gpa, bytes) ||
3670 detect_write_flooding(sp, spte)) {
3671 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3672 &invalid_list);
3673 ++vcpu->kvm->stat.mmu_flooded;
3674 continue;
3675 }
3676
3677 spte = get_written_sptes(sp, gpa, &npte);
3678 if (!spte)
3679 continue;
3680
3681 local_flush = true;
3682 while (npte--) {
3683 entry = *spte;
3684 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3685 if (gentry &&
3686 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3687 & mask.word) && rmap_can_add(vcpu))
3688 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3689 if (!remote_flush && need_remote_flush(entry, *spte))
3690 remote_flush = true;
3691 ++spte;
3692 }
3693 }
3694 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3695 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3696 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3697 spin_unlock(&vcpu->kvm->mmu_lock);
3698 }
3699
3700 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3701 {
3702 gpa_t gpa;
3703 int r;
3704
3705 if (vcpu->arch.mmu.direct_map)
3706 return 0;
3707
3708 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3709
3710 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3711
3712 return r;
3713 }
3714 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3715
3716 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3717 {
3718 LIST_HEAD(invalid_list);
3719
3720 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3721 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3722 struct kvm_mmu_page *sp;
3723
3724 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3725 struct kvm_mmu_page, link);
3726 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3727 ++vcpu->kvm->stat.mmu_recycled;
3728 }
3729 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3730 }
3731
3732 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
3733 {
3734 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
3735 return vcpu_match_mmio_gpa(vcpu, addr);
3736
3737 return vcpu_match_mmio_gva(vcpu, addr);
3738 }
3739
3740 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3741 void *insn, int insn_len)
3742 {
3743 int r, emulation_type = EMULTYPE_RETRY;
3744 enum emulation_result er;
3745
3746 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3747 if (r < 0)
3748 goto out;
3749
3750 if (!r) {
3751 r = 1;
3752 goto out;
3753 }
3754
3755 if (is_mmio_page_fault(vcpu, cr2))
3756 emulation_type = 0;
3757
3758 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
3759
3760 switch (er) {
3761 case EMULATE_DONE:
3762 return 1;
3763 case EMULATE_DO_MMIO:
3764 ++vcpu->stat.mmio_exits;
3765 /* fall through */
3766 case EMULATE_FAIL:
3767 return 0;
3768 default:
3769 BUG();
3770 }
3771 out:
3772 return r;
3773 }
3774 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3775
3776 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3777 {
3778 vcpu->arch.mmu.invlpg(vcpu, gva);
3779 kvm_mmu_flush_tlb(vcpu);
3780 ++vcpu->stat.invlpg;
3781 }
3782 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3783
3784 void kvm_enable_tdp(void)
3785 {
3786 tdp_enabled = true;
3787 }
3788 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3789
3790 void kvm_disable_tdp(void)
3791 {
3792 tdp_enabled = false;
3793 }
3794 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3795
3796 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3797 {
3798 free_page((unsigned long)vcpu->arch.mmu.pae_root);
3799 if (vcpu->arch.mmu.lm_root != NULL)
3800 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3801 }
3802
3803 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3804 {
3805 struct page *page;
3806 int i;
3807
3808 ASSERT(vcpu);
3809
3810 /*
3811 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3812 * Therefore we need to allocate shadow page tables in the first
3813 * 4GB of memory, which happens to fit the DMA32 zone.
3814 */
3815 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3816 if (!page)
3817 return -ENOMEM;
3818
3819 vcpu->arch.mmu.pae_root = page_address(page);
3820 for (i = 0; i < 4; ++i)
3821 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3822
3823 return 0;
3824 }
3825
3826 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3827 {
3828 ASSERT(vcpu);
3829
3830 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
3831 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3832 vcpu->arch.mmu.translate_gpa = translate_gpa;
3833 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
3834
3835 return alloc_mmu_pages(vcpu);
3836 }
3837
3838 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3839 {
3840 ASSERT(vcpu);
3841 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3842
3843 return init_kvm_mmu(vcpu);
3844 }
3845
3846 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3847 {
3848 struct kvm_mmu_page *sp;
3849
3850 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3851 int i;
3852 u64 *pt;
3853
3854 if (!test_bit(slot, sp->slot_bitmap))
3855 continue;
3856
3857 pt = sp->spt;
3858 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3859 if (!is_shadow_present_pte(pt[i]) ||
3860 !is_last_spte(pt[i], sp->role.level))
3861 continue;
3862
3863 if (is_large_pte(pt[i])) {
3864 drop_spte(kvm, &pt[i]);
3865 --kvm->stat.lpages;
3866 continue;
3867 }
3868
3869 /* avoid RMW */
3870 if (is_writable_pte(pt[i]))
3871 mmu_spte_update(&pt[i],
3872 pt[i] & ~PT_WRITABLE_MASK);
3873 }
3874 }
3875 kvm_flush_remote_tlbs(kvm);
3876 }
3877
3878 void kvm_mmu_zap_all(struct kvm *kvm)
3879 {
3880 struct kvm_mmu_page *sp, *node;
3881 LIST_HEAD(invalid_list);
3882
3883 spin_lock(&kvm->mmu_lock);
3884 restart:
3885 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3886 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3887 goto restart;
3888
3889 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3890 spin_unlock(&kvm->mmu_lock);
3891 }
3892
3893 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3894 struct list_head *invalid_list)
3895 {
3896 struct kvm_mmu_page *page;
3897
3898 page = container_of(kvm->arch.active_mmu_pages.prev,
3899 struct kvm_mmu_page, link);
3900 kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3901 }
3902
3903 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3904 {
3905 struct kvm *kvm;
3906 struct kvm *kvm_freed = NULL;
3907 int nr_to_scan = sc->nr_to_scan;
3908
3909 if (nr_to_scan == 0)
3910 goto out;
3911
3912 raw_spin_lock(&kvm_lock);
3913
3914 list_for_each_entry(kvm, &vm_list, vm_list) {
3915 int idx;
3916 LIST_HEAD(invalid_list);
3917
3918 idx = srcu_read_lock(&kvm->srcu);
3919 spin_lock(&kvm->mmu_lock);
3920 if (!kvm_freed && nr_to_scan > 0 &&
3921 kvm->arch.n_used_mmu_pages > 0) {
3922 kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3923 &invalid_list);
3924 kvm_freed = kvm;
3925 }
3926 nr_to_scan--;
3927
3928 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3929 spin_unlock(&kvm->mmu_lock);
3930 srcu_read_unlock(&kvm->srcu, idx);
3931 }
3932 if (kvm_freed)
3933 list_move_tail(&kvm_freed->vm_list, &vm_list);
3934
3935 raw_spin_unlock(&kvm_lock);
3936
3937 out:
3938 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3939 }
3940
3941 static struct shrinker mmu_shrinker = {
3942 .shrink = mmu_shrink,
3943 .seeks = DEFAULT_SEEKS * 10,
3944 };
3945
3946 static void mmu_destroy_caches(void)
3947 {
3948 if (pte_list_desc_cache)
3949 kmem_cache_destroy(pte_list_desc_cache);
3950 if (mmu_page_header_cache)
3951 kmem_cache_destroy(mmu_page_header_cache);
3952 }
3953
3954 int kvm_mmu_module_init(void)
3955 {
3956 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3957 sizeof(struct pte_list_desc),
3958 0, 0, NULL);
3959 if (!pte_list_desc_cache)
3960 goto nomem;
3961
3962 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3963 sizeof(struct kvm_mmu_page),
3964 0, 0, NULL);
3965 if (!mmu_page_header_cache)
3966 goto nomem;
3967
3968 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3969 goto nomem;
3970
3971 register_shrinker(&mmu_shrinker);
3972
3973 return 0;
3974
3975 nomem:
3976 mmu_destroy_caches();
3977 return -ENOMEM;
3978 }
3979
3980 /*
3981 * Caculate mmu pages needed for kvm.
3982 */
3983 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3984 {
3985 unsigned int nr_mmu_pages;
3986 unsigned int nr_pages = 0;
3987 struct kvm_memslots *slots;
3988 struct kvm_memory_slot *memslot;
3989
3990 slots = kvm_memslots(kvm);
3991
3992 kvm_for_each_memslot(memslot, slots)
3993 nr_pages += memslot->npages;
3994
3995 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3996 nr_mmu_pages = max(nr_mmu_pages,
3997 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3998
3999 return nr_mmu_pages;
4000 }
4001
4002 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4003 {
4004 struct kvm_shadow_walk_iterator iterator;
4005 u64 spte;
4006 int nr_sptes = 0;
4007
4008 walk_shadow_page_lockless_begin(vcpu);
4009 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4010 sptes[iterator.level-1] = spte;
4011 nr_sptes++;
4012 if (!is_shadow_present_pte(spte))
4013 break;
4014 }
4015 walk_shadow_page_lockless_end(vcpu);
4016
4017 return nr_sptes;
4018 }
4019 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4020
4021 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4022 {
4023 ASSERT(vcpu);
4024
4025 destroy_kvm_mmu(vcpu);
4026 free_mmu_pages(vcpu);
4027 mmu_free_memory_caches(vcpu);
4028 }
4029
4030 void kvm_mmu_module_exit(void)
4031 {
4032 mmu_destroy_caches();
4033 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4034 unregister_shrinker(&mmu_shrinker);
4035 mmu_audit_disable();
4036 }