?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / staging / iio / cdc / ad7746.c
blob40b8512cbc322b74891b5d8963e3d058494444d2
1 /*
2 * AD7746 capacitive sensor driver supporting AD7745, AD7746 and AD7747
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/i2c.h>
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/stat.h>
18
19 #include "../iio.h"
20 #include "../sysfs.h"
21
22 #include "ad7746.h"
23
24 /*
25 * AD7746 Register Definition
26 */
27
28 #define AD7746_REG_STATUS 0
29 #define AD7746_REG_CAP_DATA_HIGH 1
30 #define AD7746_REG_CAP_DATA_MID 2
31 #define AD7746_REG_CAP_DATA_LOW 3
32 #define AD7746_REG_VT_DATA_HIGH 4
33 #define AD7746_REG_VT_DATA_MID 5
34 #define AD7746_REG_VT_DATA_LOW 6
35 #define AD7746_REG_CAP_SETUP 7
36 #define AD7746_REG_VT_SETUP 8
37 #define AD7746_REG_EXC_SETUP 9
38 #define AD7746_REG_CFG 10
39 #define AD7746_REG_CAPDACA 11
40 #define AD7746_REG_CAPDACB 12
41 #define AD7746_REG_CAP_OFFH 13
42 #define AD7746_REG_CAP_OFFL 14
43 #define AD7746_REG_CAP_GAINH 15
44 #define AD7746_REG_CAP_GAINL 16
45 #define AD7746_REG_VOLT_GAINH 17
46 #define AD7746_REG_VOLT_GAINL 18
47
48 /* Status Register Bit Designations (AD7746_REG_STATUS) */
49 #define AD7746_STATUS_EXCERR (1 << 3)
50 #define AD7746_STATUS_RDY (1 << 2)
51 #define AD7746_STATUS_RDYVT (1 << 1)
52 #define AD7746_STATUS_RDYCAP (1 << 0)
53
54 /* Capacitive Channel Setup Register Bit Designations (AD7746_REG_CAP_SETUP) */
55 #define AD7746_CAPSETUP_CAPEN (1 << 7)
56 #define AD7746_CAPSETUP_CIN2 (1 << 6) /* AD7746 only */
57 #define AD7746_CAPSETUP_CAPDIFF (1 << 5)
58 #define AD7746_CAPSETUP_CACHOP (1 << 0)
59
60 /* Voltage/Temperature Setup Register Bit Designations (AD7746_REG_VT_SETUP) */
61 #define AD7746_VTSETUP_VTEN (1 << 7)
62 #define AD7746_VTSETUP_VTMD_INT_TEMP (0 << 5)
63 #define AD7746_VTSETUP_VTMD_EXT_TEMP (1 << 5)
64 #define AD7746_VTSETUP_VTMD_VDD_MON (2 << 5)
65 #define AD7746_VTSETUP_VTMD_EXT_VIN (3 << 5)
66 #define AD7746_VTSETUP_EXTREF (1 << 4)
67 #define AD7746_VTSETUP_VTSHORT (1 << 1)
68 #define AD7746_VTSETUP_VTCHOP (1 << 0)
69
70 /* Excitation Setup Register Bit Designations (AD7746_REG_EXC_SETUP) */
71 #define AD7746_EXCSETUP_CLKCTRL (1 << 7)
72 #define AD7746_EXCSETUP_EXCON (1 << 6)
73 #define AD7746_EXCSETUP_EXCB (1 << 5)
74 #define AD7746_EXCSETUP_NEXCB (1 << 4)
75 #define AD7746_EXCSETUP_EXCA (1 << 3)
76 #define AD7746_EXCSETUP_NEXCA (1 << 2)
77 #define AD7746_EXCSETUP_EXCLVL(x) (((x) & 0x3) << 0)
78
79 /* Config Register Bit Designations (AD7746_REG_CFG) */
80 #define AD7746_CONF_VTFS(x) ((x) << 6)
81 #define AD7746_CONF_CAPFS(x) ((x) << 3)
82 #define AD7746_CONF_MODE_IDLE (0 << 0)
83 #define AD7746_CONF_MODE_CONT_CONV (1 << 0)
84 #define AD7746_CONF_MODE_SINGLE_CONV (2 << 0)
85 #define AD7746_CONF_MODE_PWRDN (3 << 0)
86 #define AD7746_CONF_MODE_OFFS_CAL (5 << 0)
87 #define AD7746_CONF_MODE_GAIN_CAL (6 << 0)
88
89 /* CAPDAC Register Bit Designations (AD7746_REG_CAPDACx) */
90 #define AD7746_CAPDAC_DACEN (1 << 7)
91 #define AD7746_CAPDAC_DACP(x) ((x) & 0x7F)
92
93 /*
94 * struct ad7746_chip_info - chip specifc information
95 */
96
97 struct ad7746_chip_info {
98 struct i2c_client *client;
99 /*
100 * Capacitive channel digital filter setup;
101 * conversion time/update rate setup per channel
102 */
103 u8 config;
104 u8 cap_setup;
105 u8 vt_setup;
106 u8 capdac[2][2];
107 s8 capdac_set;
108 };
109
110 enum ad7746_chan {
111 VIN,
112 VIN_VDD,
113 TEMP_INT,
114 TEMP_EXT,
115 CIN1,
116 CIN1_DIFF,
117 CIN2,
118 CIN2_DIFF,
119 };
120
121 static const struct iio_chan_spec ad7746_channels[] = {
122 [VIN] = {
123 .type = IIO_VOLTAGE,
124 .indexed = 1,
125 .channel = 0,
126 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT,
127 .address = AD7746_REG_VT_DATA_HIGH << 8 |
128 AD7746_VTSETUP_VTMD_EXT_VIN,
129 },
130 [VIN_VDD] = {
131 .type = IIO_VOLTAGE,
132 .indexed = 1,
133 .channel = 1,
134 .extend_name = "supply",
135 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT,
136 .address = AD7746_REG_VT_DATA_HIGH << 8 |
137 AD7746_VTSETUP_VTMD_VDD_MON,
138 },
139 [TEMP_INT] = {
140 .type = IIO_TEMP,
141 .indexed = 1,
142 .channel = 0,
143 .processed_val = IIO_PROCESSED,
144 .address = AD7746_REG_VT_DATA_HIGH << 8 |
145 AD7746_VTSETUP_VTMD_INT_TEMP,
146 },
147 [TEMP_EXT] = {
148 .type = IIO_TEMP,
149 .indexed = 1,
150 .channel = 1,
151 .processed_val = IIO_PROCESSED,
152 .address = AD7746_REG_VT_DATA_HIGH << 8 |
153 AD7746_VTSETUP_VTMD_EXT_TEMP,
154 },
155 [CIN1] = {
156 .type = IIO_CAPACITANCE,
157 .indexed = 1,
158 .channel = 0,
159 .info_mask = IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT |
160 IIO_CHAN_INFO_CALIBBIAS_SHARED_BIT |
161 IIO_CHAN_INFO_OFFSET_SEPARATE_BIT |
162 IIO_CHAN_INFO_SCALE_SHARED_BIT,
163 .address = AD7746_REG_CAP_DATA_HIGH << 8,
164 },
165 [CIN1_DIFF] = {
166 .type = IIO_CAPACITANCE,
167 .differential = 1,
168 .indexed = 1,
169 .channel = 0,
170 .channel2 = 2,
171 .info_mask = IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT |
172 IIO_CHAN_INFO_CALIBBIAS_SHARED_BIT |
173 IIO_CHAN_INFO_OFFSET_SEPARATE_BIT |
174 IIO_CHAN_INFO_SCALE_SHARED_BIT,
175 .address = AD7746_REG_CAP_DATA_HIGH << 8 |
176 AD7746_CAPSETUP_CAPDIFF
177 },
178 [CIN2] = {
179 .type = IIO_CAPACITANCE,
180 .indexed = 1,
181 .channel = 1,
182 .info_mask = IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT |
183 IIO_CHAN_INFO_CALIBBIAS_SHARED_BIT |
184 IIO_CHAN_INFO_OFFSET_SEPARATE_BIT |
185 IIO_CHAN_INFO_SCALE_SHARED_BIT,
186 .address = AD7746_REG_CAP_DATA_HIGH << 8 |
187 AD7746_CAPSETUP_CIN2,
188 },
189 [CIN2_DIFF] = {
190 .type = IIO_CAPACITANCE,
191 .differential = 1,
192 .indexed = 1,
193 .channel = 1,
194 .channel2 = 3,
195 .info_mask = IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT |
196 IIO_CHAN_INFO_CALIBBIAS_SHARED_BIT |
197 IIO_CHAN_INFO_OFFSET_SEPARATE_BIT |
198 IIO_CHAN_INFO_SCALE_SHARED_BIT,
199 .address = AD7746_REG_CAP_DATA_HIGH << 8 |
200 AD7746_CAPSETUP_CAPDIFF | AD7746_CAPSETUP_CIN2,
201 }
202 };
203
204 /* Values are Update Rate (Hz), Conversion Time (ms) + 1*/
205 static const unsigned char ad7746_vt_filter_rate_table[][2] = {
206 {50, 20 + 1}, {31, 32 + 1}, {16, 62 + 1}, {8, 122 + 1},
207 };
208
209 static const unsigned char ad7746_cap_filter_rate_table[][2] = {
210 {91, 11 + 1}, {84, 12 + 1}, {50, 20 + 1}, {26, 38 + 1},
211 {16, 62 + 1}, {13, 77 + 1}, {11, 92 + 1}, {9, 110 + 1},
212 };
213
214 static int ad7746_select_channel(struct iio_dev *indio_dev,
215 struct iio_chan_spec const *chan)
216 {
217 struct ad7746_chip_info *chip = iio_priv(indio_dev);
218 int ret, delay;
219 u8 vt_setup, cap_setup;
220
221 switch (chan->type) {
222 case IIO_CAPACITANCE:
223 cap_setup = (chan->address & 0xFF) | AD7746_CAPSETUP_CAPEN;
224 vt_setup = chip->vt_setup & ~AD7746_VTSETUP_VTEN;
225 delay = ad7746_cap_filter_rate_table[(chip->config >> 3) &
226 0x7][1];
227
228 if (chip->capdac_set != chan->channel) {
229 ret = i2c_smbus_write_byte_data(chip->client,
230 AD7746_REG_CAPDACA,
231 chip->capdac[chan->channel][0]);
232 if (ret < 0)
233 return ret;
234 ret = i2c_smbus_write_byte_data(chip->client,
235 AD7746_REG_CAPDACB,
236 chip->capdac[chan->channel][1]);
237 if (ret < 0)
238 return ret;
239
240 chip->capdac_set = chan->channel;
241 }
242 break;
243 case IIO_VOLTAGE:
244 case IIO_TEMP:
245 vt_setup = (chan->address & 0xFF) | AD7746_VTSETUP_VTEN;
246 cap_setup = chip->cap_setup & ~AD7746_CAPSETUP_CAPEN;
247 delay = ad7746_cap_filter_rate_table[(chip->config >> 6) &
248 0x3][1];
249 break;
250 default:
251 return -EINVAL;
252 }
253
254 if (chip->cap_setup != cap_setup) {
255 ret = i2c_smbus_write_byte_data(chip->client,
256 AD7746_REG_CAP_SETUP,
257 cap_setup);
258 if (ret < 0)
259 return ret;
260
261 chip->cap_setup = cap_setup;
262 }
263
264 if (chip->vt_setup != vt_setup) {
265 ret = i2c_smbus_write_byte_data(chip->client,
266 AD7746_REG_VT_SETUP,
267 vt_setup);
268 if (ret < 0)
269 return ret;
270
271 chip->vt_setup = vt_setup;
272 }
273
274 return delay;
275 }
276
277 static inline ssize_t ad7746_start_calib(struct device *dev,
278 struct device_attribute *attr,
279 const char *buf,
280 size_t len,
281 u8 regval)
282 {
283 struct iio_dev *indio_dev = dev_get_drvdata(dev);
284 struct ad7746_chip_info *chip = iio_priv(indio_dev);
285 bool doit;
286 int ret, timeout = 10;
287
288 ret = strtobool(buf, &doit);
289 if (ret < 0)
290 return ret;
291
292 if (!doit)
293 return 0;
294
295 mutex_lock(&indio_dev->mlock);
296 regval |= chip->config;
297 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval);
298 if (ret < 0) {
299 mutex_unlock(&indio_dev->mlock);
300 return ret;
301 }
302
303 do {
304 msleep(20);
305 ret = i2c_smbus_read_byte_data(chip->client, AD7746_REG_CFG);
306 if (ret < 0) {
307 mutex_unlock(&indio_dev->mlock);
308 return ret;
309 }
310 } while ((ret == regval) && timeout--);
311
312 mutex_unlock(&indio_dev->mlock);
313
314 return len;
315 }
316
317 static ssize_t ad7746_start_offset_calib(struct device *dev,
318 struct device_attribute *attr,
319 const char *buf,
320 size_t len)
321 {
322 struct iio_dev *indio_dev = dev_get_drvdata(dev);
323 int ret = ad7746_select_channel(indio_dev,
324 &ad7746_channels[to_iio_dev_attr(attr)->address]);
325 if (ret < 0)
326 return ret;
327
328 return ad7746_start_calib(dev, attr, buf, len,
329 AD7746_CONF_MODE_OFFS_CAL);
330 }
331
332 static ssize_t ad7746_start_gain_calib(struct device *dev,
333 struct device_attribute *attr,
334 const char *buf,
335 size_t len)
336 {
337 struct iio_dev *indio_dev = dev_get_drvdata(dev);
338 int ret = ad7746_select_channel(indio_dev,
339 &ad7746_channels[to_iio_dev_attr(attr)->address]);
340 if (ret < 0)
341 return ret;
342
343 return ad7746_start_calib(dev, attr, buf, len,
344 AD7746_CONF_MODE_GAIN_CAL);
345 }
346
347 static IIO_DEVICE_ATTR(in_capacitance0_calibbias_calibration,
348 S_IWUSR, NULL, ad7746_start_offset_calib, CIN1);
349 static IIO_DEVICE_ATTR(in_capacitance1_calibbias_calibration,
350 S_IWUSR, NULL, ad7746_start_offset_calib, CIN2);
351 static IIO_DEVICE_ATTR(in_capacitance0_calibscale_calibration,
352 S_IWUSR, NULL, ad7746_start_gain_calib, CIN1);
353 static IIO_DEVICE_ATTR(in_capacitance1_calibscale_calibration,
354 S_IWUSR, NULL, ad7746_start_gain_calib, CIN2);
355 static IIO_DEVICE_ATTR(in_voltage0_calibscale_calibration,
356 S_IWUSR, NULL, ad7746_start_gain_calib, VIN);
357
358 static ssize_t ad7746_show_cap_filter_rate_setup(struct device *dev,
359 struct device_attribute *attr,
360 char *buf)
361 {
362 struct iio_dev *indio_dev = dev_get_drvdata(dev);
363 struct ad7746_chip_info *chip = iio_priv(indio_dev);
364
365 return sprintf(buf, "%d\n", ad7746_cap_filter_rate_table[
366 (chip->config >> 3) & 0x7][0]);
367 }
368
369 static ssize_t ad7746_store_cap_filter_rate_setup(struct device *dev,
370 struct device_attribute *attr,
371 const char *buf,
372 size_t len)
373 {
374 struct iio_dev *indio_dev = dev_get_drvdata(dev);
375 struct ad7746_chip_info *chip = iio_priv(indio_dev);
376 u8 data;
377 int ret, i;
378
379 ret = kstrtou8(buf, 10, &data);
380 if (ret < 0)
381 return ret;
382
383 for (i = 0; i < ARRAY_SIZE(ad7746_cap_filter_rate_table); i++)
384 if (data >= ad7746_cap_filter_rate_table[i][0])
385 break;
386
387 if (i >= ARRAY_SIZE(ad7746_cap_filter_rate_table))
388 i = ARRAY_SIZE(ad7746_cap_filter_rate_table) - 1;
389
390 mutex_lock(&indio_dev->mlock);
391 chip->config &= ~AD7746_CONF_CAPFS(0x7);
392 chip->config |= AD7746_CONF_CAPFS(i);
393 mutex_unlock(&indio_dev->mlock);
394
395 return len;
396 }
397
398 static ssize_t ad7746_show_vt_filter_rate_setup(struct device *dev,
399 struct device_attribute *attr,
400 char *buf)
401 {
402 struct iio_dev *indio_dev = dev_get_drvdata(dev);
403 struct ad7746_chip_info *chip = iio_priv(indio_dev);
404
405 return sprintf(buf, "%d\n", ad7746_vt_filter_rate_table[
406 (chip->config >> 6) & 0x3][0]);
407 }
408
409 static ssize_t ad7746_store_vt_filter_rate_setup(struct device *dev,
410 struct device_attribute *attr,
411 const char *buf,
412 size_t len)
413 {
414 struct iio_dev *indio_dev = dev_get_drvdata(dev);
415 struct ad7746_chip_info *chip = iio_priv(indio_dev);
416 u8 data;
417 int ret, i;
418
419 ret = kstrtou8(buf, 10, &data);
420 if (ret < 0)
421 return ret;
422
423 for (i = 0; i < ARRAY_SIZE(ad7746_vt_filter_rate_table); i++)
424 if (data >= ad7746_vt_filter_rate_table[i][0])
425 break;
426
427 if (i >= ARRAY_SIZE(ad7746_vt_filter_rate_table))
428 i = ARRAY_SIZE(ad7746_vt_filter_rate_table) - 1;
429
430 mutex_lock(&indio_dev->mlock);
431 chip->config &= ~AD7746_CONF_VTFS(0x3);
432 chip->config |= AD7746_CONF_VTFS(i);
433 mutex_unlock(&indio_dev->mlock);
434
435 return len;
436 }
437
438 static IIO_DEVICE_ATTR(in_capacitance_sampling_frequency,
439 S_IRUGO | S_IWUSR, ad7746_show_cap_filter_rate_setup,
440 ad7746_store_cap_filter_rate_setup, 0);
441
442 static IIO_DEVICE_ATTR(in_voltage_sampling_frequency,
443 S_IRUGO | S_IWUSR, ad7746_show_vt_filter_rate_setup,
444 ad7746_store_vt_filter_rate_setup, 0);
445
446 static IIO_CONST_ATTR(in_voltage_sampling_frequency_available, "50 31 16 8");
447 static IIO_CONST_ATTR(in_capacitance_sampling_frequency_available,
448 "91 84 50 26 16 13 11 9");
449
450 static struct attribute *ad7746_attributes[] = {
451 &iio_dev_attr_in_capacitance_sampling_frequency.dev_attr.attr,
452 &iio_dev_attr_in_voltage_sampling_frequency.dev_attr.attr,
453 &iio_dev_attr_in_capacitance0_calibbias_calibration.dev_attr.attr,
454 &iio_dev_attr_in_capacitance0_calibscale_calibration.dev_attr.attr,
455 &iio_dev_attr_in_capacitance1_calibscale_calibration.dev_attr.attr,
456 &iio_dev_attr_in_capacitance1_calibbias_calibration.dev_attr.attr,
457 &iio_dev_attr_in_voltage0_calibscale_calibration.dev_attr.attr,
458 &iio_const_attr_in_voltage_sampling_frequency_available.dev_attr.attr,
459 &iio_const_attr_in_capacitance_sampling_frequency_available.
460 dev_attr.attr,
461 NULL,
462 };
463
464 static const struct attribute_group ad7746_attribute_group = {
465 .attrs = ad7746_attributes,
466 };
467
468 static int ad7746_write_raw(struct iio_dev *indio_dev,
469 struct iio_chan_spec const *chan,
470 int val,
471 int val2,
472 long mask)
473 {
474 struct ad7746_chip_info *chip = iio_priv(indio_dev);
475 int ret, reg;
476
477 mutex_lock(&indio_dev->mlock);
478
479 switch (mask) {
480 case IIO_CHAN_INFO_CALIBSCALE:
481 if (val != 1) {
482 ret = -EINVAL;
483 goto out;
484 }
485
486 val = (val2 * 1024) / 15625;
487
488 switch (chan->type) {
489 case IIO_CAPACITANCE:
490 reg = AD7746_REG_CAP_GAINH;
491 break;
492 case IIO_VOLTAGE:
493 reg = AD7746_REG_VOLT_GAINH;
494 break;
495 default:
496 ret = -EINVAL;
497 goto out;
498 }
499
500 ret = i2c_smbus_write_word_data(chip->client, reg, swab16(val));
501 if (ret < 0)
502 goto out;
503
504 ret = 0;
505 break;
506 case IIO_CHAN_INFO_CALIBBIAS:
507 if ((val < 0) | (val > 0xFFFF)) {
508 ret = -EINVAL;
509 goto out;
510 }
511 ret = i2c_smbus_write_word_data(chip->client,
512 AD7746_REG_CAP_OFFH, swab16(val));
513 if (ret < 0)
514 goto out;
515
516 ret = 0;
517 break;
518 case IIO_CHAN_INFO_OFFSET:
519 if ((val < 0) | (val > 43008000)) { /* 21pF */
520 ret = -EINVAL;
521 goto out;
522 }
523
524 /* CAPDAC Scale = 21pF_typ / 127
525 * CIN Scale = 8.192pF / 2^24
526 * Offset Scale = CAPDAC Scale / CIN Scale = 338646
527 * */
528
529 val /= 338646;
530
531 chip->capdac[chan->channel][chan->differential] = (val > 0 ?
532 AD7746_CAPDAC_DACP(val) | AD7746_CAPDAC_DACEN : 0);
533
534 ret = i2c_smbus_write_byte_data(chip->client,
535 AD7746_REG_CAPDACA,
536 chip->capdac[chan->channel][0]);
537 if (ret < 0)
538 goto out;
539 ret = i2c_smbus_write_byte_data(chip->client,
540 AD7746_REG_CAPDACB,
541 chip->capdac[chan->channel][1]);
542 if (ret < 0)
543 goto out;
544
545 chip->capdac_set = chan->channel;
546
547 ret = 0;
548 break;
549 default:
550 ret = -EINVAL;
551 }
552
553 out:
554 mutex_unlock(&indio_dev->mlock);
555 return ret;
556 }
557
558 static int ad7746_read_raw(struct iio_dev *indio_dev,
559 struct iio_chan_spec const *chan,
560 int *val, int *val2,
561 long mask)
562 {
563 struct ad7746_chip_info *chip = iio_priv(indio_dev);
564 int ret, delay;
565 u8 regval, reg;
566
567 union {
568 u32 d32;
569 u8 d8[4];
570 } data;
571
572 mutex_lock(&indio_dev->mlock);
573
574 switch (mask) {
575 case 0:
576 ret = ad7746_select_channel(indio_dev, chan);
577 if (ret < 0)
578 goto out;
579 delay = ret;
580
581 regval = chip->config | AD7746_CONF_MODE_SINGLE_CONV;
582 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG,
583 regval);
584 if (ret < 0)
585 goto out;
586
587 msleep(delay);
588 /* Now read the actual register */
589
590 ret = i2c_smbus_read_i2c_block_data(chip->client,
591 chan->address >> 8, 3, &data.d8[1]);
592
593 if (ret < 0)
594 goto out;
595
596 *val = (be32_to_cpu(data.d32) & 0xFFFFFF) - 0x800000;
597
598 switch (chan->type) {
599 case IIO_TEMP:
600 /* temperature in milli degrees Celsius
601 * T = ((*val / 2048) - 4096) * 1000
602 */
603 *val = (*val * 125) / 256;
604 break;
605 case IIO_VOLTAGE:
606 if (chan->channel == 1) /* supply_raw*/
607 *val = *val * 6;
608 break;
609 default:
610 break;
611 }
612
613 ret = IIO_VAL_INT;
614 break;
615 case IIO_CHAN_INFO_CALIBSCALE:
616 switch (chan->type) {
617 case IIO_CAPACITANCE:
618 reg = AD7746_REG_CAP_GAINH;
619 break;
620 case IIO_VOLTAGE:
621 reg = AD7746_REG_VOLT_GAINH;
622 break;
623 default:
624 ret = -EINVAL;
625 goto out;
626 }
627
628 ret = i2c_smbus_read_word_data(chip->client, reg);
629 if (ret < 0)
630 goto out;
631 /* 1 + gain_val / 2^16 */
632 *val = 1;
633 *val2 = (15625 * swab16(ret)) / 1024;
634
635 ret = IIO_VAL_INT_PLUS_MICRO;
636 break;
637 case IIO_CHAN_INFO_CALIBBIAS:
638 ret = i2c_smbus_read_word_data(chip->client,
639 AD7746_REG_CAP_OFFH);
640 if (ret < 0)
641 goto out;
642 *val = swab16(ret);
643
644 ret = IIO_VAL_INT;
645 break;
646 case IIO_CHAN_INFO_OFFSET:
647 *val = AD7746_CAPDAC_DACP(chip->capdac[chan->channel]
648 [chan->differential]) * 338646;
649
650 ret = IIO_VAL_INT;
651 break;
652 case IIO_CHAN_INFO_SCALE:
653 switch (chan->type) {
654 case IIO_CAPACITANCE:
655 /* 8.192pf / 2^24 */
656 *val2 = 488;
657 *val = 0;
658 break;
659 case IIO_VOLTAGE:
660 /* 1170mV / 2^23 */
661 *val2 = 139475;
662 *val = 0;
663 break;
664 default:
665 ret = -EINVAL;
666 goto out;
667 }
668
669 ret = IIO_VAL_INT_PLUS_NANO;
670 break;
671 default:
672 ret = -EINVAL;
673 };
674 out:
675 mutex_unlock(&indio_dev->mlock);
676 return ret;
677 }
678
679 static const struct iio_info ad7746_info = {
680 .attrs = &ad7746_attribute_group,
681 .read_raw = &ad7746_read_raw,
682 .write_raw = &ad7746_write_raw,
683 .driver_module = THIS_MODULE,
684 };
685
686 /*
687 * device probe and remove
688 */
689
690 static int __devinit ad7746_probe(struct i2c_client *client,
691 const struct i2c_device_id *id)
692 {
693 struct ad7746_platform_data *pdata = client->dev.platform_data;
694 struct ad7746_chip_info *chip;
695 struct iio_dev *indio_dev;
696 int ret = 0;
697 unsigned char regval = 0;
698
699 indio_dev = iio_allocate_device(sizeof(*chip));
700 if (indio_dev == NULL) {
701 ret = -ENOMEM;
702 goto error_ret;
703 }
704 chip = iio_priv(indio_dev);
705 /* this is only used for device removal purposes */
706 i2c_set_clientdata(client, indio_dev);
707
708 chip->client = client;
709 chip->capdac_set = -1;
710
711 /* Establish that the iio_dev is a child of the i2c device */
712 indio_dev->name = id->name;
713 indio_dev->dev.parent = &client->dev;
714 indio_dev->info = &ad7746_info;
715 indio_dev->channels = ad7746_channels;
716 if (id->driver_data == 7746)
717 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels);
718 else
719 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels) - 2;
720 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels);
721 indio_dev->modes = INDIO_DIRECT_MODE;
722
723 if (pdata) {
724 if (pdata->exca_en) {
725 if (pdata->exca_inv_en)
726 regval |= AD7746_EXCSETUP_NEXCA;
727 else
728 regval |= AD7746_EXCSETUP_EXCA;
729 }
730
731 if (pdata->excb_en) {
732 if (pdata->excb_inv_en)
733 regval |= AD7746_EXCSETUP_NEXCB;
734 else
735 regval |= AD7746_EXCSETUP_EXCB;
736 }
737
738 regval |= AD7746_EXCSETUP_EXCLVL(pdata->exclvl);
739 } else {
740 dev_warn(&client->dev, "No platform data? using default\n");
741 regval = AD7746_EXCSETUP_EXCA | AD7746_EXCSETUP_EXCB |
742 AD7746_EXCSETUP_EXCLVL(3);
743 }
744
745 ret = i2c_smbus_write_byte_data(chip->client,
746 AD7746_REG_EXC_SETUP, regval);
747 if (ret < 0)
748 goto error_free_dev;
749
750 ret = iio_device_register(indio_dev);
751 if (ret)
752 goto error_free_dev;
753
754 dev_info(&client->dev, "%s capacitive sensor registered\n", id->name);
755
756 return 0;
757
758 error_free_dev:
759 iio_free_device(indio_dev);
760 error_ret:
761 return ret;
762 }
763
764 static int __devexit ad7746_remove(struct i2c_client *client)
765 {
766 struct iio_dev *indio_dev = i2c_get_clientdata(client);
767
768 iio_device_unregister(indio_dev);
769 iio_free_device(indio_dev);
770
771 return 0;
772 }
773
774 static const struct i2c_device_id ad7746_id[] = {
775 { "ad7745", 7745 },
776 { "ad7746", 7746 },
777 { "ad7747", 7747 },
778 {}
779 };
780
781 MODULE_DEVICE_TABLE(i2c, ad7746_id);
782
783 static struct i2c_driver ad7746_driver = {
784 .driver = {
785 .name = KBUILD_MODNAME,
786 },
787 .probe = ad7746_probe,
788 .remove = __devexit_p(ad7746_remove),
789 .id_table = ad7746_id,
790 };
791 module_i2c_driver(ad7746_driver);
792
793 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
794 MODULE_DESCRIPTION("Analog Devices AD7746/5/7 capacitive sensor driver");
795 MODULE_LICENSE("GPL v2");