1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <net/mac80211.h>
34 #include "iwl-eeprom.h"
39 #include "iwl-helpers.h"
42 * iwl_legacy_txq_update_write_ptr - Send new write index to hardware
45 iwl_legacy_txq_update_write_ptr(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
48 int txq_id
= txq
->q
.id
;
50 if (txq
->need_update
== 0)
53 /* if we're trying to save power */
54 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
55 /* wake up nic if it's powered down ...
56 * uCode will wake up, and interrupt us again, so next
57 * time we'll skip this part. */
58 reg
= iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
60 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
62 "Tx queue %d requesting wakeup,"
63 " GP1 = 0x%x\n", txq_id
, reg
);
64 iwl_legacy_set_bit(priv
, CSR_GP_CNTRL
,
65 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
69 iwl_legacy_write_direct32(priv
, HBUS_TARG_WRPTR
,
70 txq
->q
.write_ptr
| (txq_id
<< 8));
73 * else not in power-save mode,
74 * uCode will never sleep when we're
75 * trying to tx (during RFKILL, we're not trying to tx).
78 iwl_write32(priv
, HBUS_TARG_WRPTR
,
79 txq
->q
.write_ptr
| (txq_id
<< 8));
82 EXPORT_SYMBOL(iwl_legacy_txq_update_write_ptr
);
85 * iwl_legacy_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
87 void iwl_legacy_tx_queue_unmap(struct iwl_priv
*priv
, int txq_id
)
89 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
90 struct iwl_queue
*q
= &txq
->q
;
95 while (q
->write_ptr
!= q
->read_ptr
) {
96 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
97 q
->read_ptr
= iwl_legacy_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
100 EXPORT_SYMBOL(iwl_legacy_tx_queue_unmap
);
103 * iwl_legacy_tx_queue_free - Deallocate DMA queue.
104 * @txq: Transmit queue to deallocate.
106 * Empty queue by removing and destroying all BD's.
108 * 0-fill, but do not free "txq" descriptor structure.
110 void iwl_legacy_tx_queue_free(struct iwl_priv
*priv
, int txq_id
)
112 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
113 struct device
*dev
= &priv
->pci_dev
->dev
;
116 iwl_legacy_tx_queue_unmap(priv
, txq_id
);
118 /* De-alloc array of command/tx buffers */
119 for (i
= 0; i
< TFD_TX_CMD_SLOTS
; i
++)
122 /* De-alloc circular buffer of TFDs */
124 dma_free_coherent(dev
, priv
->hw_params
.tfd_size
*
125 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
127 /* De-alloc array of per-TFD driver data */
131 /* deallocate arrays */
137 /* 0-fill queue descriptor structure */
138 memset(txq
, 0, sizeof(*txq
));
140 EXPORT_SYMBOL(iwl_legacy_tx_queue_free
);
143 * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
145 void iwl_legacy_cmd_queue_unmap(struct iwl_priv
*priv
)
147 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
148 struct iwl_queue
*q
= &txq
->q
;
154 while (q
->read_ptr
!= q
->write_ptr
) {
155 i
= iwl_legacy_get_cmd_index(q
, q
->read_ptr
, 0);
157 if (txq
->meta
[i
].flags
& CMD_MAPPED
) {
158 pci_unmap_single(priv
->pci_dev
,
159 dma_unmap_addr(&txq
->meta
[i
], mapping
),
160 dma_unmap_len(&txq
->meta
[i
], len
),
161 PCI_DMA_BIDIRECTIONAL
);
162 txq
->meta
[i
].flags
= 0;
165 q
->read_ptr
= iwl_legacy_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
169 if (txq
->meta
[i
].flags
& CMD_MAPPED
) {
170 pci_unmap_single(priv
->pci_dev
,
171 dma_unmap_addr(&txq
->meta
[i
], mapping
),
172 dma_unmap_len(&txq
->meta
[i
], len
),
173 PCI_DMA_BIDIRECTIONAL
);
174 txq
->meta
[i
].flags
= 0;
177 EXPORT_SYMBOL(iwl_legacy_cmd_queue_unmap
);
180 * iwl_legacy_cmd_queue_free - Deallocate DMA queue.
181 * @txq: Transmit queue to deallocate.
183 * Empty queue by removing and destroying all BD's.
185 * 0-fill, but do not free "txq" descriptor structure.
187 void iwl_legacy_cmd_queue_free(struct iwl_priv
*priv
)
189 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
190 struct device
*dev
= &priv
->pci_dev
->dev
;
193 iwl_legacy_cmd_queue_unmap(priv
);
195 /* De-alloc array of command/tx buffers */
196 for (i
= 0; i
<= TFD_CMD_SLOTS
; i
++)
199 /* De-alloc circular buffer of TFDs */
201 dma_free_coherent(dev
, priv
->hw_params
.tfd_size
* txq
->q
.n_bd
,
202 txq
->tfds
, txq
->q
.dma_addr
);
204 /* deallocate arrays */
210 /* 0-fill queue descriptor structure */
211 memset(txq
, 0, sizeof(*txq
));
213 EXPORT_SYMBOL(iwl_legacy_cmd_queue_free
);
215 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
218 * Theory of operation
220 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
221 * of buffer descriptors, each of which points to one or more data buffers for
222 * the device to read from or fill. Driver and device exchange status of each
223 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
224 * entries in each circular buffer, to protect against confusing empty and full
227 * The device reads or writes the data in the queues via the device's several
228 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
230 * For Tx queue, there are low mark and high mark limits. If, after queuing
231 * the packet for Tx, free space become < low mark, Tx queue stopped. When
232 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
235 * See more detailed info in iwl-4965-hw.h.
236 ***************************************************/
238 int iwl_legacy_queue_space(const struct iwl_queue
*q
)
240 int s
= q
->read_ptr
- q
->write_ptr
;
242 if (q
->read_ptr
> q
->write_ptr
)
247 /* keep some reserve to not confuse empty and full situations */
253 EXPORT_SYMBOL(iwl_legacy_queue_space
);
257 * iwl_legacy_queue_init - Initialize queue's high/low-water and read/write indexes
259 static int iwl_legacy_queue_init(struct iwl_priv
*priv
, struct iwl_queue
*q
,
260 int count
, int slots_num
, u32 id
)
263 q
->n_window
= slots_num
;
266 /* count must be power-of-two size, otherwise iwl_legacy_queue_inc_wrap
267 * and iwl_legacy_queue_dec_wrap are broken. */
268 BUG_ON(!is_power_of_2(count
));
270 /* slots_num must be power-of-two size, otherwise
271 * iwl_legacy_get_cmd_index is broken. */
272 BUG_ON(!is_power_of_2(slots_num
));
274 q
->low_mark
= q
->n_window
/ 4;
278 q
->high_mark
= q
->n_window
/ 8;
279 if (q
->high_mark
< 2)
282 q
->write_ptr
= q
->read_ptr
= 0;
288 * iwl_legacy_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
290 static int iwl_legacy_tx_queue_alloc(struct iwl_priv
*priv
,
291 struct iwl_tx_queue
*txq
, u32 id
)
293 struct device
*dev
= &priv
->pci_dev
->dev
;
294 size_t tfd_sz
= priv
->hw_params
.tfd_size
* TFD_QUEUE_SIZE_MAX
;
296 /* Driver private data, only for Tx (not command) queues,
297 * not shared with device. */
298 if (id
!= priv
->cmd_queue
) {
299 txq
->txb
= kzalloc(sizeof(txq
->txb
[0]) *
300 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
302 IWL_ERR(priv
, "kmalloc for auxiliary BD "
303 "structures failed\n");
310 /* Circular buffer of transmit frame descriptors (TFDs),
311 * shared with device */
312 txq
->tfds
= dma_alloc_coherent(dev
, tfd_sz
, &txq
->q
.dma_addr
,
315 IWL_ERR(priv
, "pci_alloc_consistent(%zd) failed\n", tfd_sz
);
330 * iwl_legacy_tx_queue_init - Allocate and initialize one tx/cmd queue
332 int iwl_legacy_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
333 int slots_num
, u32 txq_id
)
337 int actual_slots
= slots_num
;
340 * Alloc buffer array for commands (Tx or other types of commands).
341 * For the command queue (#4/#9), allocate command space + one big
342 * command for scan, since scan command is very huge; the system will
343 * not have two scans at the same time, so only one is needed.
344 * For normal Tx queues (all other queues), no super-size command
347 if (txq_id
== priv
->cmd_queue
)
350 txq
->meta
= kzalloc(sizeof(struct iwl_cmd_meta
) * actual_slots
,
352 txq
->cmd
= kzalloc(sizeof(struct iwl_device_cmd
*) * actual_slots
,
355 if (!txq
->meta
|| !txq
->cmd
)
356 goto out_free_arrays
;
358 len
= sizeof(struct iwl_device_cmd
);
359 for (i
= 0; i
< actual_slots
; i
++) {
360 /* only happens for cmd queue */
362 len
= IWL_MAX_CMD_SIZE
;
364 txq
->cmd
[i
] = kmalloc(len
, GFP_KERNEL
);
369 /* Alloc driver data array and TFD circular buffer */
370 ret
= iwl_legacy_tx_queue_alloc(priv
, txq
, txq_id
);
374 txq
->need_update
= 0;
377 * For the default queues 0-3, set up the swq_id
378 * already -- all others need to get one later
379 * (if they need one at all).
382 iwl_legacy_set_swq_id(txq
, txq_id
, txq_id
);
384 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
385 * iwl_legacy_queue_inc_wrap and iwl_legacy_queue_dec_wrap are broken. */
386 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
388 /* Initialize queue's high/low-water marks, and head/tail indexes */
389 iwl_legacy_queue_init(priv
, &txq
->q
,
390 TFD_QUEUE_SIZE_MAX
, slots_num
, txq_id
);
392 /* Tell device where to find queue */
393 priv
->cfg
->ops
->lib
->txq_init(priv
, txq
);
397 for (i
= 0; i
< actual_slots
; i
++)
405 EXPORT_SYMBOL(iwl_legacy_tx_queue_init
);
407 void iwl_legacy_tx_queue_reset(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
408 int slots_num
, u32 txq_id
)
410 int actual_slots
= slots_num
;
412 if (txq_id
== priv
->cmd_queue
)
415 memset(txq
->meta
, 0, sizeof(struct iwl_cmd_meta
) * actual_slots
);
417 txq
->need_update
= 0;
419 /* Initialize queue's high/low-water marks, and head/tail indexes */
420 iwl_legacy_queue_init(priv
, &txq
->q
,
421 TFD_QUEUE_SIZE_MAX
, slots_num
, txq_id
);
423 /* Tell device where to find queue */
424 priv
->cfg
->ops
->lib
->txq_init(priv
, txq
);
426 EXPORT_SYMBOL(iwl_legacy_tx_queue_reset
);
428 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
431 * iwl_legacy_enqueue_hcmd - enqueue a uCode command
432 * @priv: device private data point
433 * @cmd: a point to the ucode command structure
435 * The function returns < 0 values to indicate the operation is
436 * failed. On success, it turns the index (> 0) of command in the
439 int iwl_legacy_enqueue_hcmd(struct iwl_priv
*priv
, struct iwl_host_cmd
*cmd
)
441 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
442 struct iwl_queue
*q
= &txq
->q
;
443 struct iwl_device_cmd
*out_cmd
;
444 struct iwl_cmd_meta
*out_meta
;
445 dma_addr_t phys_addr
;
451 cmd
->len
= priv
->cfg
->ops
->utils
->get_hcmd_size(cmd
->id
, cmd
->len
);
452 fix_size
= (u16
)(cmd
->len
+ sizeof(out_cmd
->hdr
));
454 /* If any of the command structures end up being larger than
455 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
456 * we will need to increase the size of the TFD entries
457 * Also, check to see if command buffer should not exceed the size
458 * of device_cmd and max_cmd_size. */
459 BUG_ON((fix_size
> TFD_MAX_PAYLOAD_SIZE
) &&
460 !(cmd
->flags
& CMD_SIZE_HUGE
));
461 BUG_ON(fix_size
> IWL_MAX_CMD_SIZE
);
463 if (iwl_legacy_is_rfkill(priv
) || iwl_legacy_is_ctkill(priv
)) {
464 IWL_WARN(priv
, "Not sending command - %s KILL\n",
465 iwl_legacy_is_rfkill(priv
) ? "RF" : "CT");
469 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
471 if (iwl_legacy_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
472 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
474 IWL_ERR(priv
, "Restarting adapter due to command queue full\n");
475 queue_work(priv
->workqueue
, &priv
->restart
);
479 idx
= iwl_legacy_get_cmd_index(q
, q
->write_ptr
, cmd
->flags
& CMD_SIZE_HUGE
);
480 out_cmd
= txq
->cmd
[idx
];
481 out_meta
= &txq
->meta
[idx
];
483 if (WARN_ON(out_meta
->flags
& CMD_MAPPED
)) {
484 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
488 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
489 out_meta
->flags
= cmd
->flags
| CMD_MAPPED
;
490 if (cmd
->flags
& CMD_WANT_SKB
)
491 out_meta
->source
= cmd
;
492 if (cmd
->flags
& CMD_ASYNC
)
493 out_meta
->callback
= cmd
->callback
;
495 out_cmd
->hdr
.cmd
= cmd
->id
;
496 memcpy(&out_cmd
->cmd
.payload
, cmd
->data
, cmd
->len
);
498 /* At this point, the out_cmd now has all of the incoming cmd
501 out_cmd
->hdr
.flags
= 0;
502 out_cmd
->hdr
.sequence
= cpu_to_le16(QUEUE_TO_SEQ(priv
->cmd_queue
) |
503 INDEX_TO_SEQ(q
->write_ptr
));
504 if (cmd
->flags
& CMD_SIZE_HUGE
)
505 out_cmd
->hdr
.sequence
|= SEQ_HUGE_FRAME
;
506 len
= sizeof(struct iwl_device_cmd
);
507 if (idx
== TFD_CMD_SLOTS
)
508 len
= IWL_MAX_CMD_SIZE
;
510 #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
511 switch (out_cmd
->hdr
.cmd
) {
512 case REPLY_TX_LINK_QUALITY_CMD
:
513 case SENSITIVITY_CMD
:
514 IWL_DEBUG_HC_DUMP(priv
,
515 "Sending command %s (#%x), seq: 0x%04X, "
516 "%d bytes at %d[%d]:%d\n",
517 iwl_legacy_get_cmd_string(out_cmd
->hdr
.cmd
),
519 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
520 q
->write_ptr
, idx
, priv
->cmd_queue
);
523 IWL_DEBUG_HC(priv
, "Sending command %s (#%x), seq: 0x%04X, "
524 "%d bytes at %d[%d]:%d\n",
525 iwl_legacy_get_cmd_string(out_cmd
->hdr
.cmd
),
527 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
528 q
->write_ptr
, idx
, priv
->cmd_queue
);
531 txq
->need_update
= 1;
533 if (priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl
)
534 /* Set up entry in queue's byte count circular buffer */
535 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
, 0);
537 phys_addr
= pci_map_single(priv
->pci_dev
, &out_cmd
->hdr
,
538 fix_size
, PCI_DMA_BIDIRECTIONAL
);
539 dma_unmap_addr_set(out_meta
, mapping
, phys_addr
);
540 dma_unmap_len_set(out_meta
, len
, fix_size
);
542 trace_iwlwifi_legacy_dev_hcmd(priv
, &out_cmd
->hdr
,
543 fix_size
, cmd
->flags
);
545 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
546 phys_addr
, fix_size
, 1,
549 /* Increment and update queue's write index */
550 q
->write_ptr
= iwl_legacy_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
551 iwl_legacy_txq_update_write_ptr(priv
, txq
);
553 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
558 * iwl_legacy_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
560 * When FW advances 'R' index, all entries between old and new 'R' index
561 * need to be reclaimed. As result, some free space forms. If there is
562 * enough free space (> low mark), wake the stack that feeds us.
564 static void iwl_legacy_hcmd_queue_reclaim(struct iwl_priv
*priv
, int txq_id
,
565 int idx
, int cmd_idx
)
567 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
568 struct iwl_queue
*q
= &txq
->q
;
571 if ((idx
>= q
->n_bd
) || (iwl_legacy_queue_used(q
, idx
) == 0)) {
572 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
573 "is out of range [0-%d] %d %d.\n", txq_id
,
574 idx
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
578 for (idx
= iwl_legacy_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
579 q
->read_ptr
= iwl_legacy_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
582 IWL_ERR(priv
, "HCMD skipped: index (%d) %d %d\n", idx
,
583 q
->write_ptr
, q
->read_ptr
);
584 queue_work(priv
->workqueue
, &priv
->restart
);
591 * iwl_legacy_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
592 * @rxb: Rx buffer to reclaim
594 * If an Rx buffer has an async callback associated with it the callback
595 * will be executed. The attached skb (if present) will only be freed
596 * if the callback returns 1
599 iwl_legacy_tx_cmd_complete(struct iwl_priv
*priv
, struct iwl_rx_mem_buffer
*rxb
)
601 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
602 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
603 int txq_id
= SEQ_TO_QUEUE(sequence
);
604 int index
= SEQ_TO_INDEX(sequence
);
606 bool huge
= !!(pkt
->hdr
.sequence
& SEQ_HUGE_FRAME
);
607 struct iwl_device_cmd
*cmd
;
608 struct iwl_cmd_meta
*meta
;
609 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
612 /* If a Tx command is being handled and it isn't in the actual
613 * command queue then there a command routing bug has been introduced
614 * in the queue management code. */
615 if (WARN(txq_id
!= priv
->cmd_queue
,
616 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
617 txq_id
, priv
->cmd_queue
, sequence
,
618 priv
->txq
[priv
->cmd_queue
].q
.read_ptr
,
619 priv
->txq
[priv
->cmd_queue
].q
.write_ptr
)) {
620 iwl_print_hex_error(priv
, pkt
, 32);
624 cmd_index
= iwl_legacy_get_cmd_index(&txq
->q
, index
, huge
);
625 cmd
= txq
->cmd
[cmd_index
];
626 meta
= &txq
->meta
[cmd_index
];
628 pci_unmap_single(priv
->pci_dev
,
629 dma_unmap_addr(meta
, mapping
),
630 dma_unmap_len(meta
, len
),
631 PCI_DMA_BIDIRECTIONAL
);
633 /* Input error checking is done when commands are added to queue. */
634 if (meta
->flags
& CMD_WANT_SKB
) {
635 meta
->source
->reply_page
= (unsigned long)rxb_addr(rxb
);
637 } else if (meta
->callback
)
638 meta
->callback(priv
, cmd
, pkt
);
640 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
642 iwl_legacy_hcmd_queue_reclaim(priv
, txq_id
, index
, cmd_index
);
644 if (!(meta
->flags
& CMD_ASYNC
)) {
645 clear_bit(STATUS_HCMD_ACTIVE
, &priv
->status
);
646 IWL_DEBUG_INFO(priv
, "Clearing HCMD_ACTIVE for command %s\n",
647 iwl_legacy_get_cmd_string(cmd
->hdr
.cmd
));
648 wake_up_interruptible(&priv
->wait_command_queue
);
651 /* Mark as unmapped */
654 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
656 EXPORT_SYMBOL(iwl_legacy_tx_cmd_complete
);