1 /* linux/arch/arm/plat-s3c24xx/pwm-clock.c
3 * Copyright (c) 2007 Simtec Electronics
4 * Copyright (c) 2007, 2008 Ben Dooks
5 * Ben Dooks <ben-linux@fluff.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/errno.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
21 #include <mach/hardware.h>
24 #include <mach/regs-clock.h>
25 #include <mach/regs-gpio.h>
27 #include <asm/plat-s3c24xx/clock.h>
28 #include <asm/plat-s3c24xx/cpu.h>
30 #include <asm/plat-s3c/regs-timer.h>
32 /* Each of the timers 0 through 5 go through the following
33 * clock tree, with the inputs depending on the timers.
35 * pclk ---- [ prescaler 0 ] -+---> timer 0
38 * pclk ---- [ prescaler 1 ] -+---> timer 2
42 * Which are fed into the timers as so:
44 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
46 * tclk 0 ------------------------------/
48 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
50 * tclk 0 ------------------------------/
53 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
55 * tclk 1 ------------------------------/
57 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
59 * tclk 1 ------------------------------/
61 * prescaled 1 ---- [ div 2,4,8, 16 ] --\
63 * tclk 1 ------------------------------/
65 * Since the mux and the divider are tied together in the
66 * same register space, it is impossible to set the parent
67 * and the rate at the same time. To avoid this, we add an
68 * intermediate 'prescaled-and-divided' clock to select
69 * as the parent for the timer input clock called tdiv.
71 * prescaled clk --> pwm-tdiv ---\
73 * tclk -------------------------/
76 static unsigned long clk_pwm_scaler_getrate(struct clk
*clk
)
78 unsigned long tcfg0
= __raw_readl(S3C2410_TCFG0
);
81 tcfg0
&= S3C2410_TCFG_PRESCALER1_MASK
;
82 tcfg0
>>= S3C2410_TCFG_PRESCALER1_SHIFT
;
84 tcfg0
&= S3C2410_TCFG_PRESCALER0_MASK
;
87 return clk_get_rate(clk
->parent
) / (tcfg0
+ 1);
90 /* TODO - add set rate calls. */
92 static struct clk clk_timer_scaler
[] = {
94 .name
= "pwm-scaler0",
96 .get_rate
= clk_pwm_scaler_getrate
,
99 .name
= "pwm-scaler1",
101 .get_rate
= clk_pwm_scaler_getrate
,
105 static struct clk clk_timer_tclk
[] = {
116 struct pwm_tdiv_clk
{
118 unsigned int divisor
;
121 static inline struct pwm_tdiv_clk
*to_tdiv(struct clk
*clk
)
123 return container_of(clk
, struct pwm_tdiv_clk
, clk
);
126 static inline unsigned long tcfg_to_divisor(unsigned long tcfg1
)
128 return 1 << (1 + tcfg1
);
131 static unsigned long clk_pwm_tdiv_get_rate(struct clk
*clk
)
133 unsigned long tcfg1
= __raw_readl(S3C2410_TCFG1
);
134 unsigned int divisor
;
136 tcfg1
>>= S3C2410_TCFG1_SHIFT(clk
->id
);
137 tcfg1
&= S3C2410_TCFG1_MUX_MASK
;
139 if (tcfg1
== S3C2410_TCFG1_MUX_TCLK
)
140 divisor
= to_tdiv(clk
)->divisor
;
142 divisor
= tcfg_to_divisor(tcfg1
);
144 return clk_get_rate(clk
->parent
) / divisor
;
147 static unsigned long clk_pwm_tdiv_round_rate(struct clk
*clk
,
150 unsigned long parent_rate
;
151 unsigned long divisor
;
153 parent_rate
= clk_get_rate(clk
->parent
);
154 divisor
= parent_rate
/ rate
;
158 else if (divisor
<= 4)
160 else if (divisor
<= 8)
165 return parent_rate
/ divisor
;
168 static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk
*divclk
)
172 switch (divclk
->divisor
) {
174 bits
= S3C2410_TCFG1_MUX_DIV2
;
177 bits
= S3C2410_TCFG1_MUX_DIV4
;
180 bits
= S3C2410_TCFG1_MUX_DIV8
;
184 bits
= S3C2410_TCFG1_MUX_DIV16
;
191 static void clk_pwm_tdiv_update(struct pwm_tdiv_clk
*divclk
)
193 unsigned long tcfg1
= __raw_readl(S3C2410_TCFG1
);
194 unsigned long bits
= clk_pwm_tdiv_bits(divclk
);
196 unsigned long shift
= S3C2410_TCFG1_SHIFT(divclk
->clk
.id
);
198 local_irq_save(flags
);
200 tcfg1
= __raw_readl(S3C2410_TCFG1
);
201 tcfg1
&= ~(S3C2410_TCFG1_MUX_MASK
<< shift
);
202 tcfg1
|= bits
<< shift
;
203 __raw_writel(tcfg1
, S3C2410_TCFG1
);
205 local_irq_restore(flags
);
208 static int clk_pwm_tdiv_set_rate(struct clk
*clk
, unsigned long rate
)
210 struct pwm_tdiv_clk
*divclk
= to_tdiv(clk
);
211 unsigned long tcfg1
= __raw_readl(S3C2410_TCFG1
);
212 unsigned long parent_rate
= clk_get_rate(clk
->parent
);
213 unsigned long divisor
;
215 tcfg1
>>= S3C2410_TCFG1_SHIFT(clk
->id
);
216 tcfg1
&= S3C2410_TCFG1_MUX_MASK
;
218 rate
= clk_round_rate(clk
, rate
);
219 divisor
= parent_rate
/ rate
;
224 divclk
->divisor
= divisor
;
226 /* Update the current MUX settings if we are currently
227 * selected as the clock source for this clock. */
229 if (tcfg1
!= S3C2410_TCFG1_MUX_TCLK
)
230 clk_pwm_tdiv_update(divclk
);
235 static struct pwm_tdiv_clk clk_timer_tdiv
[] = {
239 .parent
= &clk_timer_scaler
[0],
240 .get_rate
= clk_pwm_tdiv_get_rate
,
241 .set_rate
= clk_pwm_tdiv_set_rate
,
242 .round_rate
= clk_pwm_tdiv_round_rate
,
248 .parent
= &clk_timer_scaler
[0],
249 .get_rate
= clk_pwm_tdiv_get_rate
,
250 .set_rate
= clk_pwm_tdiv_set_rate
,
251 .round_rate
= clk_pwm_tdiv_round_rate
,
257 .parent
= &clk_timer_scaler
[1],
258 .get_rate
= clk_pwm_tdiv_get_rate
,
259 .set_rate
= clk_pwm_tdiv_set_rate
,
260 .round_rate
= clk_pwm_tdiv_round_rate
,
266 .parent
= &clk_timer_scaler
[1],
267 .get_rate
= clk_pwm_tdiv_get_rate
,
268 .set_rate
= clk_pwm_tdiv_set_rate
,
269 .round_rate
= clk_pwm_tdiv_round_rate
,
275 .parent
= &clk_timer_scaler
[1],
276 .get_rate
= clk_pwm_tdiv_get_rate
,
277 .set_rate
= clk_pwm_tdiv_set_rate
,
278 .round_rate
= clk_pwm_tdiv_round_rate
,
283 static int __init
clk_pwm_tdiv_register(unsigned int id
)
285 struct pwm_tdiv_clk
*divclk
= &clk_timer_tdiv
[id
];
286 unsigned long tcfg1
= __raw_readl(S3C2410_TCFG1
);
288 tcfg1
>>= S3C2410_TCFG1_SHIFT(id
);
289 tcfg1
&= S3C2410_TCFG1_MUX_MASK
;
292 divclk
->divisor
= tcfg_to_divisor(tcfg1
);
294 return s3c24xx_register_clock(&divclk
->clk
);
297 static inline struct clk
*s3c24xx_pwmclk_tclk(unsigned int id
)
299 return (id
>= 2) ? &clk_timer_tclk
[1] : &clk_timer_tclk
[0];
302 static inline struct clk
*s3c24xx_pwmclk_tdiv(unsigned int id
)
304 return &clk_timer_tdiv
[id
].clk
;
307 static int clk_pwm_tin_set_parent(struct clk
*clk
, struct clk
*parent
)
309 unsigned int id
= clk
->id
;
313 unsigned long shift
= S3C2410_TCFG1_SHIFT(id
);
315 if (parent
== s3c24xx_pwmclk_tclk(id
))
316 bits
= S3C2410_TCFG1_MUX_TCLK
<< shift
;
317 else if (parent
== s3c24xx_pwmclk_tdiv(id
))
318 bits
= clk_pwm_tdiv_bits(to_tdiv(clk
)) << shift
;
322 clk
->parent
= parent
;
324 local_irq_save(flags
);
326 tcfg1
= __raw_readl(S3C2410_TCFG1
);
327 tcfg1
&= ~(S3C2410_TCFG1_MUX_MASK
<< shift
);
328 __raw_writel(tcfg1
| bits
, S3C2410_TCFG1
);
330 local_irq_restore(flags
);
335 static struct clk clk_tin
[] = {
339 .set_parent
= clk_pwm_tin_set_parent
,
344 .set_parent
= clk_pwm_tin_set_parent
,
349 .set_parent
= clk_pwm_tin_set_parent
,
354 .set_parent
= clk_pwm_tin_set_parent
,
359 .set_parent
= clk_pwm_tin_set_parent
,
363 static __init
int clk_pwm_tin_register(struct clk
*pwm
)
365 unsigned long tcfg1
= __raw_readl(S3C2410_TCFG1
);
366 unsigned int id
= pwm
->id
;
371 ret
= s3c24xx_register_clock(pwm
);
375 tcfg1
>>= S3C2410_TCFG1_SHIFT(id
);
376 tcfg1
&= S3C2410_TCFG1_MUX_MASK
;
378 if (tcfg1
== S3C2410_TCFG1_MUX_TCLK
)
379 parent
= s3c24xx_pwmclk_tclk(id
);
381 parent
= s3c24xx_pwmclk_tdiv(id
);
383 return clk_set_parent(pwm
, parent
);
386 static __init
int s3c24xx_pwmclk_init(void)
388 struct clk
*clk_timers
;
392 clk_timers
= clk_get(NULL
, "timers");
393 if (IS_ERR(clk_timers
)) {
394 printk(KERN_ERR
"%s: no parent clock\n", __func__
);
398 for (clk
= 0; clk
< ARRAY_SIZE(clk_timer_scaler
); clk
++) {
399 clk_timer_scaler
[clk
].parent
= clk_timers
;
400 ret
= s3c24xx_register_clock(&clk_timer_scaler
[clk
]);
402 printk(KERN_ERR
"error adding pwm scaler%d clock\n", clk
);
407 for (clk
= 0; clk
< ARRAY_SIZE(clk_timer_tclk
); clk
++) {
408 ret
= s3c24xx_register_clock(&clk_timer_tclk
[clk
]);
410 printk(KERN_ERR
"error adding pww tclk%d\n", clk
);
415 for (clk
= 0; clk
< ARRAY_SIZE(clk_timer_tdiv
); clk
++) {
416 ret
= clk_pwm_tdiv_register(clk
);
418 printk(KERN_ERR
"error adding pwm%d tdiv clock\n", clk
);
423 for (clk
= 0; clk
< ARRAY_SIZE(clk_tin
); clk
++) {
424 ret
= clk_pwm_tin_register(&clk_tin
[clk
]);
426 printk(KERN_ERR
"error adding pwm%d tin clock\n", clk
);
437 arch_initcall(s3c24xx_pwmclk_init
);