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staging: brcm80211: remove redundant CHIPREV macro
[zen-stable.git] / drivers / staging / brcm80211 / util / siutils.c
blob29d2d68354f684c3ead52f5cfb334fc754f72434
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/delay.h>
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <bcmdefs.h>
21 #ifdef BRCM_FULLMAC
22 #include <linux/netdevice.h>
23 #endif
24 #include <osl.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <bcmutils.h>
28 #include <siutils.h>
29 #include <bcmdevs.h>
30 #include <hndsoc.h>
31 #include <sbchipc.h>
32 #include <pci_core.h>
33 #include <pcie_core.h>
34 #include <nicpci.h>
35 #include <bcmnvram.h>
36 #include <bcmsrom.h>
37 #include <pcicfg.h>
38 #include <sbsocram.h>
39 #ifdef BCMSDIO
40 #include <bcmsdh.h>
41 #include <sdio.h>
42 #include <sbsdio.h>
43 #include <sbhnddma.h>
44 #include <sbsdpcmdev.h>
45 #include <bcmsdpcm.h>
46 #endif /* BCMSDIO */
47 #include <hndpmu.h>
48
49 /* this file now contains only definitions for sb functions, only necessary
50 *for devices using Sonics backplanes (bcm4329)
51 */
52
53 /* if an amba SDIO device is supported, please further restrict the inclusion
54 * of this file
55 */
56 #ifdef BCMSDIO
57 #include "siutils_priv.h"
58 #endif
59
60 /* local prototypes */
61 static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
62 void *regs, uint bustype, void *sdh, char **vars,
63 uint *varsz);
64 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
65 void *sdh);
66 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
67 u32 savewin, uint *origidx, void *regs);
68 static void si_nvram_process(si_info_t *sii, char *pvars);
69
70 /* dev path concatenation util */
71 static char *si_devpathvar(si_t *sih, char *var, int len, const char *name);
72 static bool _si_clkctl_cc(si_info_t *sii, uint mode);
73 static bool si_ispcie(si_info_t *sii);
74 static uint socram_banksize(si_info_t *sii, sbsocramregs_t *r,
75 u8 idx, u8 mtype);
76
77 /* global variable to indicate reservation/release of gpio's */
78 static u32 si_gpioreservation;
79
80 /*
81 * Allocate a si handle.
82 * devid - pci device id (used to determine chip#)
83 * osh - opaque OS handle
84 * regs - virtual address of initial core registers
85 * bustype - pci/sb/sdio/etc
86 * vars - pointer to a pointer area for "environment" variables
87 * varsz - pointer to int to return the size of the vars
88 */
89 si_t *si_attach(uint devid, struct osl_info *osh, void *regs, uint bustype,
90 void *sdh, char **vars, uint *varsz)
91 {
92 si_info_t *sii;
93
94 /* alloc si_info_t */
95 sii = kmalloc(sizeof(si_info_t), GFP_ATOMIC);
96 if (sii == NULL) {
97 SI_ERROR(("si_attach: malloc failed!\n"));
98 return NULL;
99 }
100
101 if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) ==
102 NULL) {
103 kfree(sii);
104 return NULL;
105 }
106 sii->vars = vars ? *vars : NULL;
107 sii->varsz = varsz ? *varsz : 0;
108
109 return (si_t *) sii;
110 }
111
112 /* global kernel resource */
113 static si_info_t ksii;
114
115 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
116 void *sdh)
117 {
118
119 #ifndef BRCM_FULLMAC
120 /* kludge to enable the clock on the 4306 which lacks a slowclock */
121 if (bustype == PCI_BUS && !si_ispcie(sii))
122 si_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
123 #endif
124
125 #if defined(BCMSDIO)
126 if (bustype == SDIO_BUS) {
127 int err;
128 u8 clkset;
129
130 /* Try forcing SDIO core to do ALPAvail request only */
131 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
132 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
133 clkset, &err);
134 if (!err) {
135 u8 clkval;
136
137 /* If register supported, wait for ALPAvail and then force ALP */
138 clkval =
139 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
140 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
141 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
142 SPINWAIT(((clkval =
143 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
144 SBSDIO_FUNC1_CHIPCLKCSR,
145 NULL)),
146 !SBSDIO_ALPAV(clkval)),
147 PMU_MAX_TRANSITION_DLY);
148 if (!SBSDIO_ALPAV(clkval)) {
149 SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", clkval));
150 return false;
151 }
152 clkset =
153 SBSDIO_FORCE_HW_CLKREQ_OFF |
154 SBSDIO_FORCE_ALP;
155 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
156 SBSDIO_FUNC1_CHIPCLKCSR,
157 clkset, &err);
158 udelay(65);
159 }
160 }
161
162 /* Also, disable the extra SDIO pull-ups */
163 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
164 NULL);
165 }
166 #endif /* defined(BCMSDIO) */
167
168 return true;
169 }
170
171 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
172 u32 savewin, uint *origidx, void *regs)
173 {
174 bool pci, pcie;
175 uint i;
176 uint pciidx, pcieidx, pcirev, pcierev;
177
178 cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
179 ASSERT(cc);
180
181 /* get chipcommon rev */
182 sii->pub.ccrev = (int)si_corerev(&sii->pub);
183
184 /* get chipcommon chipstatus */
185 if (sii->pub.ccrev >= 11)
186 sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
187
188 /* get chipcommon capabilites */
189 sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
190 /* get chipcommon extended capabilities */
191
192 #ifndef BRCM_FULLMAC
193 if (sii->pub.ccrev >= 35)
194 sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
195 #endif
196 /* get pmu rev and caps */
197 if (sii->pub.cccaps & CC_CAP_PMU) {
198 sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
199 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
200 }
201
202 /*
203 SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n",
204 sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
205 sii->pub.pmucaps));
206 */
207
208 /* figure out bus/orignal core idx */
209 sii->pub.buscoretype = NODEV_CORE_ID;
210 sii->pub.buscorerev = NOREV;
211 sii->pub.buscoreidx = BADIDX;
212
213 pci = pcie = false;
214 pcirev = pcierev = NOREV;
215 pciidx = pcieidx = BADIDX;
216
217 for (i = 0; i < sii->numcores; i++) {
218 uint cid, crev;
219
220 si_setcoreidx(&sii->pub, i);
221 cid = si_coreid(&sii->pub);
222 crev = si_corerev(&sii->pub);
223
224 /* Display cores found */
225 SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
226 i, cid, crev, sii->coresba[i], sii->regs[i]));
227
228 if (bustype == PCI_BUS) {
229 if (cid == PCI_CORE_ID) {
230 pciidx = i;
231 pcirev = crev;
232 pci = true;
233 } else if (cid == PCIE_CORE_ID) {
234 pcieidx = i;
235 pcierev = crev;
236 pcie = true;
237 }
238 }
239 #ifdef BCMSDIO
240 else if (((bustype == SDIO_BUS) ||
241 (bustype == SPI_BUS)) &&
242 ((cid == PCMCIA_CORE_ID) || (cid == SDIOD_CORE_ID))) {
243 sii->pub.buscorerev = crev;
244 sii->pub.buscoretype = cid;
245 sii->pub.buscoreidx = i;
246 }
247 #endif /* BCMSDIO */
248
249 /* find the core idx before entering this func. */
250 if ((savewin && (savewin == sii->coresba[i])) ||
251 (regs == sii->regs[i]))
252 *origidx = i;
253 }
254
255 #ifdef BRCM_FULLMAC
256 SI_MSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,
257 sii->pub.buscoretype, sii->pub.buscorerev));
258
259 /* Make sure any on-chip ARM is off (in case strapping is wrong),
260 * or downloaded code was
261 * already running.
262 */
263 if ((bustype == SDIO_BUS) || (bustype == SPI_BUS)) {
264 if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) ||
265 si_setcore(&sii->pub, ARMCM3_CORE_ID, 0))
266 si_core_disable(&sii->pub, 0);
267 }
268 #else
269 if (pci && pcie) {
270 if (si_ispcie(sii))
271 pci = false;
272 else
273 pcie = false;
274 }
275 if (pci) {
276 sii->pub.buscoretype = PCI_CORE_ID;
277 sii->pub.buscorerev = pcirev;
278 sii->pub.buscoreidx = pciidx;
279 } else if (pcie) {
280 sii->pub.buscoretype = PCIE_CORE_ID;
281 sii->pub.buscorerev = pcierev;
282 sii->pub.buscoreidx = pcieidx;
283 }
284
285 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,
286 sii->pub.buscoretype, sii->pub.buscorerev));
287
288 /* fixup necessary chip/core configurations */
289 if (sii->pub.bustype == PCI_BUS) {
290 if (SI_FAST(sii)) {
291 if (!sii->pch) {
292 sii->pch = (void *)pcicore_init(
293 &sii->pub, sii->osh,
294 (void *)PCIEREGS(sii));
295 if (sii->pch == NULL)
296 return false;
297 }
298 }
299 if (si_pci_fixcfg(&sii->pub)) {
300 SI_ERROR(("si_doattach: sb_pci_fixcfg failed\n"));
301 return false;
302 }
303 }
304 #endif
305 /* return to the original core */
306 si_setcoreidx(&sii->pub, *origidx);
307
308 return true;
309 }
310
311 static __used void si_nvram_process(si_info_t *sii, char *pvars)
312 {
313 uint w = 0;
314
315 /* get boardtype and boardrev */
316 switch (sii->pub.bustype) {
317 case PCI_BUS:
318 /* do a pci config read to get subsystem id and subvendor id */
319 pci_read_config_dword(sii->osh->pdev, PCI_CFG_SVID, &w);
320 /* Let nvram variables override subsystem Vend/ID */
321 sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub,
322 "boardvendor");
323 if (sii->pub.boardvendor == 0)
324 sii->pub.boardvendor = w & 0xffff;
325 else
326 SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii->pub.boardvendor, w & 0xffff));
327 sii->pub.boardtype = (u16)si_getdevpathintvar(&sii->pub,
328 "boardtype");
329 if (sii->pub.boardtype == 0)
330 sii->pub.boardtype = (w >> 16) & 0xffff;
331 else
332 SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", sii->pub.boardtype, (w >> 16) & 0xffff));
333 break;
334
335 #ifdef BCMSDIO
336 case SDIO_BUS:
337 #endif
338 sii->pub.boardvendor = getintvar(pvars, "manfid");
339 sii->pub.boardtype = getintvar(pvars, "prodid");
340 break;
341
342 #ifdef BCMSDIO
343 case SPI_BUS:
344 sii->pub.boardvendor = VENDOR_BROADCOM;
345 sii->pub.boardtype = SPI_BOARD;
346 break;
347 #endif
348
349 case SI_BUS:
350 case JTAG_BUS:
351 sii->pub.boardvendor = VENDOR_BROADCOM;
352 sii->pub.boardtype = getintvar(pvars, "prodid");
353 if (pvars == NULL || (sii->pub.boardtype == 0)) {
354 sii->pub.boardtype = getintvar(NULL, "boardtype");
355 if (sii->pub.boardtype == 0)
356 sii->pub.boardtype = 0xffff;
357 }
358 break;
359 }
360
361 if (sii->pub.boardtype == 0) {
362 SI_ERROR(("si_doattach: unknown board type\n"));
363 ASSERT(sii->pub.boardtype);
364 }
365
366 sii->pub.boardflags = getintvar(pvars, "boardflags");
367 }
368
369 /* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */
370 /* this has been customized for the bcm 4329 ONLY */
371 #ifdef BCMSDIO
372 static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
373 void *regs, uint bustype, void *sdh,
374 char **vars, uint *varsz)
375 {
376 struct si_pub *sih = &sii->pub;
377 u32 w, savewin;
378 chipcregs_t *cc;
379 char *pvars = NULL;
380 uint origidx;
381
382 ASSERT(GOODREGS(regs));
383
384 memset((unsigned char *) sii, 0, sizeof(si_info_t));
385
386 savewin = 0;
387
388 sih->buscoreidx = BADIDX;
389
390 sii->curmap = regs;
391 sii->sdh = sdh;
392 sii->osh = osh;
393
394 /* find Chipcommon address */
395 cc = (chipcregs_t *) sii->curmap;
396 sih->bustype = bustype;
397
398 /* bus/core/clk setup for register access */
399 if (!si_buscore_prep(sii, bustype, devid, sdh)) {
400 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
401 bustype));
402 return NULL;
403 }
404
405 /* ChipID recognition.
406 * We assume we can read chipid at offset 0 from the regs arg.
407 * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
408 * some way of recognizing them needs to be added here.
409 */
410 w = R_REG(osh, &cc->chipid);
411 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
412 /* Might as wll fill in chip id rev & pkg */
413 sih->chip = w & CID_ID_MASK;
414 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
415 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
416
417 if ((sih->chip == BCM4329_CHIP_ID) &&
418 (sih->chippkg != BCM4329_289PIN_PKG_ID))
419 sih->chippkg = BCM4329_182PIN_PKG_ID;
420
421 sih->issim = IS_SIM(sih->chippkg);
422
423 /* scan for cores */
424 /* SI_MSG(("Found chip type SB (0x%08x)\n", w)); */
425 sb_scan(&sii->pub, regs, devid);
426
427 /* no cores found, bail out */
428 if (sii->numcores == 0) {
429 SI_ERROR(("si_doattach: could not find any cores\n"));
430 return NULL;
431 }
432 /* bus/core/clk setup */
433 origidx = SI_CC_IDX;
434 if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
435 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
436 goto exit;
437 }
438
439 #ifdef BRCM_FULLMAC
440 pvars = NULL;
441 #else
442 /* Init nvram from flash if it exists */
443 nvram_init((void *)&(sii->pub));
444
445 /* Init nvram from sprom/otp if they exist */
446 if (srom_var_init
447 (&sii->pub, bustype, regs, sii->osh, vars, varsz)) {
448 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
449 goto exit;
450 }
451 pvars = vars ? *vars : NULL;
452 si_nvram_process(sii, pvars);
453 #endif
454
455 /* === NVRAM, clock is ready === */
456
457 #ifdef BRCM_FULLMAC
458 if (sii->pub.ccrev >= 20) {
459 #endif
460 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
461 W_REG(osh, &cc->gpiopullup, 0);
462 W_REG(osh, &cc->gpiopulldown, 0);
463 sb_setcoreidx(sih, origidx);
464 #ifdef BRCM_FULLMAC
465 }
466 #endif
467
468 #ifndef BRCM_FULLMAC
469 /* PMU specific initializations */
470 if (PMUCTL_ENAB(sih)) {
471 u32 xtalfreq;
472 si_pmu_init(sih, sii->osh);
473 si_pmu_chip_init(sih, sii->osh);
474 xtalfreq = getintvar(pvars, "xtalfreq");
475 /* If xtalfreq var not available, try to measure it */
476 if (xtalfreq == 0)
477 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh);
478 si_pmu_pll_init(sih, sii->osh, xtalfreq);
479 si_pmu_res_init(sih, sii->osh);
480 si_pmu_swreg_init(sih, sii->osh);
481 }
482
483 /* setup the GPIO based LED powersave register */
484 w = getintvar(pvars, "leddc");
485 if (w == 0)
486 w = DEFAULT_GPIOTIMERVAL;
487 sb_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
488
489 #ifdef BCMDBG
490 /* clear any previous epidiag-induced target abort */
491 sb_taclear(sih, false);
492 #endif /* BCMDBG */
493 #endif
494
495 return sii;
496
497 exit:
498 return NULL;
499 }
500
501 #else /* BCMSDIO */
502 static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
503 void *regs, uint bustype, void *sdh,
504 char **vars, uint *varsz)
505 {
506 struct si_pub *sih = &sii->pub;
507 u32 w, savewin;
508 chipcregs_t *cc;
509 char *pvars = NULL;
510 uint origidx;
511
512 ASSERT(GOODREGS(regs));
513
514 memset((unsigned char *) sii, 0, sizeof(si_info_t));
515
516 savewin = 0;
517
518 sih->buscoreidx = BADIDX;
519
520 sii->curmap = regs;
521 sii->sdh = sdh;
522 sii->osh = osh;
523
524 /* check to see if we are a si core mimic'ing a pci core */
525 if (bustype == PCI_BUS) {
526 pci_read_config_dword(sii->osh->pdev, PCI_SPROM_CONTROL, &w);
527 if (w == 0xffffffff) {
528 SI_ERROR(("%s: incoming bus is PCI but it's a lie, "
529 " switching to SI devid:0x%x\n",
530 __func__, devid));
531 bustype = SI_BUS;
532 }
533 }
534
535 /* find Chipcommon address */
536 if (bustype == PCI_BUS) {
537 pci_read_config_dword(sii->osh->pdev, PCI_BAR0_WIN, &savewin);
538 if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
539 savewin = SI_ENUM_BASE;
540 pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN,
541 SI_ENUM_BASE);
542 cc = (chipcregs_t *) regs;
543 } else {
544 cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
545 }
546
547 sih->bustype = bustype;
548
549 /* bus/core/clk setup for register access */
550 if (!si_buscore_prep(sii, bustype, devid, sdh)) {
551 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
552 bustype));
553 return NULL;
554 }
555
556 /* ChipID recognition.
557 * We assume we can read chipid at offset 0 from the regs arg.
558 * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
559 * some way of recognizing them needs to be added here.
560 */
561 w = R_REG(osh, &cc->chipid);
562 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
563 /* Might as wll fill in chip id rev & pkg */
564 sih->chip = w & CID_ID_MASK;
565 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
566 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
567
568 sih->issim = IS_SIM(sih->chippkg);
569
570 /* scan for cores */
571 if (sii->pub.socitype == SOCI_AI) {
572 SI_MSG(("Found chip type AI (0x%08x)\n", w));
573 /* pass chipc address instead of original core base */
574 ai_scan(&sii->pub, (void *)cc, devid);
575 } else {
576 SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));
577 return NULL;
578 }
579 /* no cores found, bail out */
580 if (sii->numcores == 0) {
581 SI_ERROR(("si_doattach: could not find any cores\n"));
582 return NULL;
583 }
584 /* bus/core/clk setup */
585 origidx = SI_CC_IDX;
586 if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
587 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
588 goto exit;
589 }
590
591 /* assume current core is CC */
592 if ((sii->pub.ccrev == 0x25)
593 &&
594 ((sih->chip == BCM43236_CHIP_ID
595 || sih->chip == BCM43235_CHIP_ID
596 || sih->chip == BCM43238_CHIP_ID)
597 && (sii->pub.chiprev <= 2))) {
598
599 if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
600 uint clkdiv;
601 clkdiv = R_REG(osh, &cc->clkdiv);
602 /* otp_clk_div is even number, 120/14 < 9mhz */
603 clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);
604 W_REG(osh, &cc->clkdiv, clkdiv);
605 SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));
606 }
607 udelay(10);
608 }
609
610 /* Init nvram from flash if it exists */
611 nvram_init((void *)&(sii->pub));
612
613 /* Init nvram from sprom/otp if they exist */
614 if (srom_var_init
615 (&sii->pub, bustype, regs, sii->osh, vars, varsz)) {
616 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
617 goto exit;
618 }
619 pvars = vars ? *vars : NULL;
620 si_nvram_process(sii, pvars);
621
622 /* === NVRAM, clock is ready === */
623 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
624 W_REG(osh, &cc->gpiopullup, 0);
625 W_REG(osh, &cc->gpiopulldown, 0);
626 si_setcoreidx(sih, origidx);
627
628 /* PMU specific initializations */
629 if (PMUCTL_ENAB(sih)) {
630 u32 xtalfreq;
631 si_pmu_init(sih, sii->osh);
632 si_pmu_chip_init(sih, sii->osh);
633 xtalfreq = getintvar(pvars, "xtalfreq");
634 /* If xtalfreq var not available, try to measure it */
635 if (xtalfreq == 0)
636 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh);
637 si_pmu_pll_init(sih, sii->osh, xtalfreq);
638 si_pmu_res_init(sih, sii->osh);
639 si_pmu_swreg_init(sih, sii->osh);
640 }
641
642 /* setup the GPIO based LED powersave register */
643 w = getintvar(pvars, "leddc");
644 if (w == 0)
645 w = DEFAULT_GPIOTIMERVAL;
646 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
647
648 if (PCIE(sii)) {
649 ASSERT(sii->pch != NULL);
650 pcicore_attach(sii->pch, pvars, SI_DOATTACH);
651 }
652
653 if ((sih->chip == BCM43224_CHIP_ID) ||
654 (sih->chip == BCM43421_CHIP_ID)) {
655 /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */
656 if (sih->chiprev == 0) {
657 SI_MSG(("Applying 43224A0 WARs\n"));
658 si_corereg(sih, SI_CC_IDX,
659 offsetof(chipcregs_t, chipcontrol),
660 CCTRL43224_GPIO_TOGGLE,
661 CCTRL43224_GPIO_TOGGLE);
662 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
663 CCTRL_43224A0_12MA_LED_DRIVE);
664 }
665 if (sih->chiprev >= 1) {
666 SI_MSG(("Applying 43224B0+ WARs\n"));
667 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
668 CCTRL_43224B0_12MA_LED_DRIVE);
669 }
670 }
671
672 if (sih->chip == BCM4313_CHIP_ID) {
673 /* enable 12 mA drive strenth for 4313 and set chipControl register bit 1 */
674 SI_MSG(("Applying 4313 WARs\n"));
675 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
676 CCTRL_4313_12MA_LED_DRIVE);
677 }
678
679 if (sih->chip == BCM4331_CHIP_ID) {
680 /* Enable Ext PA lines depending on chip package option */
681 si_chipcontrl_epa4331(sih, true);
682 }
683
684 return sii;
685 exit:
686 if (sih->bustype == PCI_BUS) {
687 if (sii->pch)
688 pcicore_deinit(sii->pch);
689 sii->pch = NULL;
690 }
691
692 return NULL;
693 }
694 #endif /* BCMSDIO */
695
696 /* may be called with core in reset */
697 void si_detach(si_t *sih)
698 {
699 si_info_t *sii;
700 uint idx;
701
702 struct si_pub *si_local = NULL;
703 bcopy(&sih, &si_local, sizeof(si_t **));
704
705 sii = SI_INFO(sih);
706
707 if (sii == NULL)
708 return;
709
710 if (sih->bustype == SI_BUS)
711 for (idx = 0; idx < SI_MAXCORES; idx++)
712 if (sii->regs[idx]) {
713 REG_UNMAP(sii->regs[idx]);
714 sii->regs[idx] = NULL;
715 }
716
717 #ifndef BRCM_FULLMAC
718 nvram_exit((void *)si_local); /* free up nvram buffers */
719
720 if (sih->bustype == PCI_BUS) {
721 if (sii->pch)
722 pcicore_deinit(sii->pch);
723 sii->pch = NULL;
724 }
725 #endif
726 #if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)
727 if (sii != &ksii)
728 #endif /* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */
729 kfree(sii);
730 }
731
732 void *si_osh(si_t *sih)
733 {
734 si_info_t *sii;
735
736 sii = SI_INFO(sih);
737 return sii->osh;
738 }
739
740 /* register driver interrupt disabling and restoring callback functions */
741 void
742 si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
743 void *intrsenabled_fn, void *intr_arg)
744 {
745 si_info_t *sii;
746
747 sii = SI_INFO(sih);
748 sii->intr_arg = intr_arg;
749 sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn;
750 sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn;
751 sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn;
752 /* save current core id. when this function called, the current core
753 * must be the core which provides driver functions(il, et, wl, etc.)
754 */
755 sii->dev_coreid = sii->coreid[sii->curidx];
756 }
757
758 void si_deregister_intr_callback(si_t *sih)
759 {
760 si_info_t *sii;
761
762 sii = SI_INFO(sih);
763 sii->intrsoff_fn = NULL;
764 }
765
766 uint si_flag(si_t *sih)
767 {
768 if (sih->socitype == SOCI_AI)
769 return ai_flag(sih);
770 else {
771 ASSERT(0);
772 return 0;
773 }
774 }
775
776 void si_setint(si_t *sih, int siflag)
777 {
778 if (sih->socitype == SOCI_AI)
779 ai_setint(sih, siflag);
780 else
781 ASSERT(0);
782 }
783
784 #ifndef BCMSDIO
785 uint si_coreid(si_t *sih)
786 {
787 si_info_t *sii;
788
789 sii = SI_INFO(sih);
790 return sii->coreid[sii->curidx];
791 }
792 #endif
793
794 uint si_coreidx(si_t *sih)
795 {
796 si_info_t *sii;
797
798 sii = SI_INFO(sih);
799 return sii->curidx;
800 }
801
802 bool si_backplane64(si_t *sih)
803 {
804 return (sih->cccaps & CC_CAP_BKPLN64) != 0;
805 }
806
807 #ifndef BCMSDIO
808 uint si_corerev(si_t *sih)
809 {
810 if (sih->socitype == SOCI_AI)
811 return ai_corerev(sih);
812 else {
813 ASSERT(0);
814 return 0;
815 }
816 }
817 #endif
818
819 /* return index of coreid or BADIDX if not found */
820 uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit)
821 {
822 si_info_t *sii;
823 uint found;
824 uint i;
825
826 sii = SI_INFO(sih);
827
828 found = 0;
829
830 for (i = 0; i < sii->numcores; i++)
831 if (sii->coreid[i] == coreid) {
832 if (found == coreunit)
833 return i;
834 found++;
835 }
836
837 return BADIDX;
838 }
839
840 /*
841 * This function changes logical "focus" to the indicated core;
842 * must be called with interrupts off.
843 * Moreover, callers should keep interrupts off during switching out of and back to d11 core
844 */
845 void *si_setcore(si_t *sih, uint coreid, uint coreunit)
846 {
847 uint idx;
848
849 idx = si_findcoreidx(sih, coreid, coreunit);
850 if (!GOODIDX(idx))
851 return NULL;
852
853 if (sih->socitype == SOCI_AI)
854 return ai_setcoreidx(sih, idx);
855 else {
856 #ifdef BCMSDIO
857 return sb_setcoreidx(sih, idx);
858 #else
859 ASSERT(0);
860 return NULL;
861 #endif
862 }
863 }
864
865 #ifndef BCMSDIO
866 void *si_setcoreidx(si_t *sih, uint coreidx)
867 {
868 if (sih->socitype == SOCI_AI)
869 return ai_setcoreidx(sih, coreidx);
870 else {
871 ASSERT(0);
872 return NULL;
873 }
874 }
875 #endif
876
877 /* Turn off interrupt as required by sb_setcore, before switch core */
878 void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
879 {
880 void *cc;
881 si_info_t *sii;
882
883 sii = SI_INFO(sih);
884
885 if (SI_FAST(sii)) {
886 /* Overloading the origidx variable to remember the coreid,
887 * this works because the core ids cannot be confused with
888 * core indices.
889 */
890 *origidx = coreid;
891 if (coreid == CC_CORE_ID)
892 return (void *)CCREGS_FAST(sii);
893 else if (coreid == sih->buscoretype)
894 return (void *)PCIEREGS(sii);
895 }
896 INTR_OFF(sii, *intr_val);
897 *origidx = sii->curidx;
898 cc = si_setcore(sih, coreid, 0);
899 ASSERT(cc != NULL);
900
901 return cc;
902 }
903
904 /* restore coreidx and restore interrupt */
905 void si_restore_core(si_t *sih, uint coreid, uint intr_val)
906 {
907 si_info_t *sii;
908
909 sii = SI_INFO(sih);
910 if (SI_FAST(sii)
911 && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
912 return;
913
914 si_setcoreidx(sih, coreid);
915 INTR_RESTORE(sii, intr_val);
916 }
917
918 u32 si_core_cflags(si_t *sih, u32 mask, u32 val)
919 {
920 if (sih->socitype == SOCI_AI)
921 return ai_core_cflags(sih, mask, val);
922 else {
923 ASSERT(0);
924 return 0;
925 }
926 }
927
928 u32 si_core_sflags(si_t *sih, u32 mask, u32 val)
929 {
930 if (sih->socitype == SOCI_AI)
931 return ai_core_sflags(sih, mask, val);
932 else {
933 ASSERT(0);
934 return 0;
935 }
936 }
937
938 bool si_iscoreup(si_t *sih)
939 {
940 if (sih->socitype == SOCI_AI)
941 return ai_iscoreup(sih);
942 else {
943 #ifdef BCMSDIO
944 return sb_iscoreup(sih);
945 #else
946 ASSERT(0);
947 return false;
948 #endif
949 }
950 }
951
952 void si_write_wrapperreg(si_t *sih, u32 offset, u32 val)
953 {
954 /* only for 4319, no requirement for SOCI_SB */
955 if (sih->socitype == SOCI_AI) {
956 ai_write_wrap_reg(sih, offset, val);
957 }
958 }
959
960 uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
961 {
962
963 if (sih->socitype == SOCI_AI)
964 return ai_corereg(sih, coreidx, regoff, mask, val);
965 else {
966 #ifdef BCMSDIO
967 return sb_corereg(sih, coreidx, regoff, mask, val);
968 #else
969 ASSERT(0);
970 return 0;
971 #endif
972 }
973 }
974
975 void si_core_disable(si_t *sih, u32 bits)
976 {
977
978 if (sih->socitype == SOCI_AI)
979 ai_core_disable(sih, bits);
980 #ifdef BCMSDIO
981 else
982 sb_core_disable(sih, bits);
983 #endif
984 }
985
986 void si_core_reset(si_t *sih, u32 bits, u32 resetbits)
987 {
988 if (sih->socitype == SOCI_AI)
989 ai_core_reset(sih, bits, resetbits);
990 #ifdef BCMSDIO
991 else
992 sb_core_reset(sih, bits, resetbits);
993 #endif
994 }
995
996 u32 si_alp_clock(si_t *sih)
997 {
998 if (PMUCTL_ENAB(sih))
999 return si_pmu_alp_clock(sih, si_osh(sih));
1000
1001 return ALP_CLOCK;
1002 }
1003
1004 u32 si_ilp_clock(si_t *sih)
1005 {
1006 if (PMUCTL_ENAB(sih))
1007 return si_pmu_ilp_clock(sih, si_osh(sih));
1008
1009 return ILP_CLOCK;
1010 }
1011
1012 /* set chip watchdog reset timer to fire in 'ticks' */
1013 #ifdef BRCM_FULLMAC
1014 void
1015 si_watchdog(si_t *sih, uint ticks)
1016 {
1017 if (PMUCTL_ENAB(sih)) {
1018
1019 if ((sih->chip == BCM4319_CHIP_ID) && (sih->chiprev == 0) &&
1020 (ticks != 0)) {
1021 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t,
1022 clk_ctl_st), ~0, 0x2);
1023 si_setcore(sih, USB20D_CORE_ID, 0);
1024 si_core_disable(sih, 1);
1025 si_setcore(sih, CC_CORE_ID, 0);
1026 }
1027
1028 if (ticks == 1)
1029 ticks = 2;
1030 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog),
1031 ~0, ticks);
1032 } else {
1033 /* instant NMI */
1034 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog),
1035 ~0, ticks);
1036 }
1037 }
1038 #else
1039 void si_watchdog(si_t *sih, uint ticks)
1040 {
1041 uint nb, maxt;
1042
1043 if (PMUCTL_ENAB(sih)) {
1044
1045 if ((sih->chip == BCM4319_CHIP_ID) &&
1046 (sih->chiprev == 0) && (ticks != 0)) {
1047 si_corereg(sih, SI_CC_IDX,
1048 offsetof(chipcregs_t, clk_ctl_st), ~0, 0x2);
1049 si_setcore(sih, USB20D_CORE_ID, 0);
1050 si_core_disable(sih, 1);
1051 si_setcore(sih, CC_CORE_ID, 0);
1052 }
1053
1054 nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24);
1055 /* The mips compiler uses the sllv instruction,
1056 * so we specially handle the 32-bit case.
1057 */
1058 if (nb == 32)
1059 maxt = 0xffffffff;
1060 else
1061 maxt = ((1 << nb) - 1);
1062
1063 if (ticks == 1)
1064 ticks = 2;
1065 else if (ticks > maxt)
1066 ticks = maxt;
1067
1068 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog),
1069 ~0, ticks);
1070 } else {
1071 /* make sure we come up in fast clock mode; or if clearing, clear clock */
1072 si_clkctl_cc(sih, ticks ? CLK_FAST : CLK_DYNAMIC);
1073 maxt = (1 << 28) - 1;
1074 if (ticks > maxt)
1075 ticks = maxt;
1076
1077 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), ~0,
1078 ticks);
1079 }
1080 }
1081 #endif
1082
1083 /* return the slow clock source - LPO, XTAL, or PCI */
1084 static uint si_slowclk_src(si_info_t *sii)
1085 {
1086 chipcregs_t *cc;
1087 u32 val;
1088
1089 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
1090
1091 if (sii->pub.ccrev < 6) {
1092 if (sii->pub.bustype == PCI_BUS) {
1093 pci_read_config_dword(sii->osh->pdev, PCI_GPIO_OUT,
1094 &val);
1095 if (val & PCI_CFG_GPIO_SCS)
1096 return SCC_SS_PCI;
1097 }
1098 return SCC_SS_XTAL;
1099 } else if (sii->pub.ccrev < 10) {
1100 cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx);
1101 return R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK;
1102 } else /* Insta-clock */
1103 return SCC_SS_XTAL;
1104 }
1105
1106 /* return the ILP (slowclock) min or max frequency */
1107 static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
1108 {
1109 u32 slowclk;
1110 uint div;
1111
1112 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
1113
1114 /* shouldn't be here unless we've established the chip has dynamic clk control */
1115 ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);
1116
1117 slowclk = si_slowclk_src(sii);
1118 if (sii->pub.ccrev < 6) {
1119 if (slowclk == SCC_SS_PCI)
1120 return max_freq ? (PCIMAXFREQ / 64)
1121 : (PCIMINFREQ / 64);
1122 else
1123 return max_freq ? (XTALMAXFREQ / 32)
1124 : (XTALMINFREQ / 32);
1125 } else if (sii->pub.ccrev < 10) {
1126 div = 4 *
1127 (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >>
1128 SCC_CD_SHIFT) + 1);
1129 if (slowclk == SCC_SS_LPO)
1130 return max_freq ? LPOMAXFREQ : LPOMINFREQ;
1131 else if (slowclk == SCC_SS_XTAL)
1132 return max_freq ? (XTALMAXFREQ / div)
1133 : (XTALMINFREQ / div);
1134 else if (slowclk == SCC_SS_PCI)
1135 return max_freq ? (PCIMAXFREQ / div)
1136 : (PCIMINFREQ / div);
1137 else
1138 ASSERT(0);
1139 } else {
1140 /* Chipc rev 10 is InstaClock */
1141 div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
1142 div = 4 * (div + 1);
1143 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
1144 }
1145 return 0;
1146 }
1147
1148 static void si_clkctl_setdelay(si_info_t *sii, void *chipcregs)
1149 {
1150 chipcregs_t *cc = (chipcregs_t *) chipcregs;
1151 uint slowmaxfreq, pll_delay, slowclk;
1152 uint pll_on_delay, fref_sel_delay;
1153
1154 pll_delay = PLL_DELAY;
1155
1156 /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
1157 * since the xtal will also be powered down by dynamic clk control logic.
1158 */
1159
1160 slowclk = si_slowclk_src(sii);
1161 if (slowclk != SCC_SS_XTAL)
1162 pll_delay += XTAL_ON_DELAY;
1163
1164 /* Starting with 4318 it is ILP that is used for the delays */
1165 slowmaxfreq =
1166 si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc);
1167
1168 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
1169 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
1170
1171 W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay);
1172 W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay);
1173 }
1174
1175 /* initialize power control delay registers */
1176 void si_clkctl_init(si_t *sih)
1177 {
1178 si_info_t *sii;
1179 uint origidx = 0;
1180 chipcregs_t *cc;
1181 bool fast;
1182
1183 if (!CCCTL_ENAB(sih))
1184 return;
1185
1186 sii = SI_INFO(sih);
1187 fast = SI_FAST(sii);
1188 if (!fast) {
1189 origidx = sii->curidx;
1190 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
1191 if (cc == NULL)
1192 return;
1193 } else {
1194 cc = (chipcregs_t *) CCREGS_FAST(sii);
1195 if (cc == NULL)
1196 return;
1197 }
1198 ASSERT(cc != NULL);
1199
1200 /* set all Instaclk chip ILP to 1 MHz */
1201 if (sih->ccrev >= 10)
1202 SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
1203 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
1204
1205 si_clkctl_setdelay(sii, (void *)cc);
1206
1207 if (!fast)
1208 si_setcoreidx(sih, origidx);
1209 }
1210
1211 /* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
1212 u16 si_clkctl_fast_pwrup_delay(si_t *sih)
1213 {
1214 si_info_t *sii;
1215 uint origidx = 0;
1216 chipcregs_t *cc;
1217 uint slowminfreq;
1218 u16 fpdelay;
1219 uint intr_val = 0;
1220 bool fast;
1221
1222 sii = SI_INFO(sih);
1223 if (PMUCTL_ENAB(sih)) {
1224 INTR_OFF(sii, intr_val);
1225 fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh);
1226 INTR_RESTORE(sii, intr_val);
1227 return fpdelay;
1228 }
1229
1230 if (!CCCTL_ENAB(sih))
1231 return 0;
1232
1233 fast = SI_FAST(sii);
1234 fpdelay = 0;
1235 if (!fast) {
1236 origidx = sii->curidx;
1237 INTR_OFF(sii, intr_val);
1238 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
1239 if (cc == NULL)
1240 goto done;
1241 } else {
1242 cc = (chipcregs_t *) CCREGS_FAST(sii);
1243 if (cc == NULL)
1244 goto done;
1245 }
1246 ASSERT(cc != NULL);
1247
1248 slowminfreq = si_slowclk_freq(sii, false, cc);
1249 fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) +
1250 (slowminfreq - 1)) / slowminfreq;
1251
1252 done:
1253 if (!fast) {
1254 si_setcoreidx(sih, origidx);
1255 INTR_RESTORE(sii, intr_val);
1256 }
1257 return fpdelay;
1258 }
1259
1260 /* turn primary xtal and/or pll off/on */
1261 int si_clkctl_xtal(si_t *sih, uint what, bool on)
1262 {
1263 si_info_t *sii;
1264 u32 in, out, outen;
1265
1266 sii = SI_INFO(sih);
1267
1268 switch (sih->bustype) {
1269
1270 #ifdef BCMSDIO
1271 case SDIO_BUS:
1272 return -1;
1273 #endif /* BCMSDIO */
1274
1275 case PCI_BUS:
1276 /* pcie core doesn't have any mapping to control the xtal pu */
1277 if (PCIE(sii))
1278 return -1;
1279
1280 pci_read_config_dword(sii->osh->pdev, PCI_GPIO_IN, &in);
1281 pci_read_config_dword(sii->osh->pdev, PCI_GPIO_OUT, &out);
1282 pci_read_config_dword(sii->osh->pdev, PCI_GPIO_OUTEN, &outen);
1283
1284 /*
1285 * Avoid glitching the clock if GPRS is already using it.
1286 * We can't actually read the state of the PLLPD so we infer it
1287 * by the value of XTAL_PU which *is* readable via gpioin.
1288 */
1289 if (on && (in & PCI_CFG_GPIO_XTAL))
1290 return 0;
1291
1292 if (what & XTAL)
1293 outen |= PCI_CFG_GPIO_XTAL;
1294 if (what & PLL)
1295 outen |= PCI_CFG_GPIO_PLL;
1296
1297 if (on) {
1298 /* turn primary xtal on */
1299 if (what & XTAL) {
1300 out |= PCI_CFG_GPIO_XTAL;
1301 if (what & PLL)
1302 out |= PCI_CFG_GPIO_PLL;
1303 pci_write_config_dword(sii->osh->pdev,
1304 PCI_GPIO_OUT, out);
1305 pci_write_config_dword(sii->osh->pdev,
1306 PCI_GPIO_OUTEN, outen);
1307 udelay(XTAL_ON_DELAY);
1308 }
1309
1310 /* turn pll on */
1311 if (what & PLL) {
1312 out &= ~PCI_CFG_GPIO_PLL;
1313 pci_write_config_dword(sii->osh->pdev,
1314 PCI_GPIO_OUT, out);
1315 mdelay(2);
1316 }
1317 } else {
1318 if (what & XTAL)
1319 out &= ~PCI_CFG_GPIO_XTAL;
1320 if (what & PLL)
1321 out |= PCI_CFG_GPIO_PLL;
1322 pci_write_config_dword(sii->osh->pdev,
1323 PCI_GPIO_OUT, out);
1324 pci_write_config_dword(sii->osh->pdev,
1325 PCI_GPIO_OUTEN, outen);
1326 }
1327
1328 default:
1329 return -1;
1330 }
1331
1332 return 0;
1333 }
1334
1335 /*
1336 * clock control policy function throught chipcommon
1337 *
1338 * set dynamic clk control mode (forceslow, forcefast, dynamic)
1339 * returns true if we are forcing fast clock
1340 * this is a wrapper over the next internal function
1341 * to allow flexible policy settings for outside caller
1342 */
1343 bool si_clkctl_cc(si_t *sih, uint mode)
1344 {
1345 si_info_t *sii;
1346
1347 sii = SI_INFO(sih);
1348
1349 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1350 if (sih->ccrev < 6)
1351 return false;
1352
1353 if (PCI_FORCEHT(sii))
1354 return mode == CLK_FAST;
1355
1356 return _si_clkctl_cc(sii, mode);
1357 }
1358
1359 /* clk control mechanism through chipcommon, no policy checking */
1360 static bool _si_clkctl_cc(si_info_t *sii, uint mode)
1361 {
1362 uint origidx = 0;
1363 chipcregs_t *cc;
1364 u32 scc;
1365 uint intr_val = 0;
1366 bool fast = SI_FAST(sii);
1367
1368 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1369 if (sii->pub.ccrev < 6)
1370 return false;
1371
1372 /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
1373 ASSERT(sii->pub.ccrev != 10);
1374
1375 if (!fast) {
1376 INTR_OFF(sii, intr_val);
1377 origidx = sii->curidx;
1378
1379 if ((sii->pub.bustype == SI_BUS) &&
1380 si_setcore(&sii->pub, MIPS33_CORE_ID, 0) &&
1381 (si_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))
1382 goto done;
1383
1384 cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0);
1385 } else {
1386 cc = (chipcregs_t *) CCREGS_FAST(sii);
1387 if (cc == NULL)
1388 goto done;
1389 }
1390 ASSERT(cc != NULL);
1391
1392 if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
1393 goto done;
1394
1395 switch (mode) {
1396 case CLK_FAST: /* FORCEHT, fast (pll) clock */
1397 if (sii->pub.ccrev < 10) {
1398 /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
1399 si_clkctl_xtal(&sii->pub, XTAL, ON);
1400 SET_REG(sii->osh, &cc->slow_clk_ctl,
1401 (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
1402 } else if (sii->pub.ccrev < 20) {
1403 OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR);
1404 } else {
1405 OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT);
1406 }
1407
1408 /* wait for the PLL */
1409 if (PMUCTL_ENAB(&sii->pub)) {
1410 u32 htavail = CCS_HTAVAIL;
1411 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail)
1412 == 0), PMU_MAX_TRANSITION_DLY);
1413 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
1414 } else {
1415 udelay(PLL_DELAY);
1416 }
1417 break;
1418
1419 case CLK_DYNAMIC: /* enable dynamic clock control */
1420 if (sii->pub.ccrev < 10) {
1421 scc = R_REG(sii->osh, &cc->slow_clk_ctl);
1422 scc &= ~(SCC_FS | SCC_IP | SCC_XC);
1423 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
1424 scc |= SCC_XC;
1425 W_REG(sii->osh, &cc->slow_clk_ctl, scc);
1426
1427 /* for dynamic control, we have to release our xtal_pu "force on" */
1428 if (scc & SCC_XC)
1429 si_clkctl_xtal(&sii->pub, XTAL, OFF);
1430 } else if (sii->pub.ccrev < 20) {
1431 /* Instaclock */
1432 AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR);
1433 } else {
1434 AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT);
1435 }
1436 break;
1437
1438 default:
1439 ASSERT(0);
1440 }
1441
1442 done:
1443 if (!fast) {
1444 si_setcoreidx(&sii->pub, origidx);
1445 INTR_RESTORE(sii, intr_val);
1446 }
1447 return mode == CLK_FAST;
1448 }
1449
1450 /* Build device path. Support SI, PCI, and JTAG for now. */
1451 int si_devpath(si_t *sih, char *path, int size)
1452 {
1453 int slen;
1454
1455 ASSERT(path != NULL);
1456 ASSERT(size >= SI_DEVPATH_BUFSZ);
1457
1458 if (!path || size <= 0)
1459 return -1;
1460
1461 switch (sih->bustype) {
1462 case SI_BUS:
1463 case JTAG_BUS:
1464 slen = snprintf(path, (size_t) size, "sb/%u/", si_coreidx(sih));
1465 break;
1466 case PCI_BUS:
1467 ASSERT((SI_INFO(sih))->osh != NULL);
1468 slen = snprintf(path, (size_t) size, "pci/%u/%u/",
1469 OSL_PCI_BUS((SI_INFO(sih))->osh),
1470 OSL_PCI_SLOT((SI_INFO(sih))->osh));
1471 break;
1472
1473 #ifdef BCMSDIO
1474 case SDIO_BUS:
1475 SI_ERROR(("si_devpath: device 0 assumed\n"));
1476 slen = snprintf(path, (size_t) size, "sd/%u/", si_coreidx(sih));
1477 break;
1478 #endif
1479 default:
1480 slen = -1;
1481 ASSERT(0);
1482 break;
1483 }
1484
1485 if (slen < 0 || slen >= size) {
1486 path[0] = '\0';
1487 return -1;
1488 }
1489
1490 return 0;
1491 }
1492
1493 /* Get a variable, but only if it has a devpath prefix */
1494 char *si_getdevpathvar(si_t *sih, const char *name)
1495 {
1496 char varname[SI_DEVPATH_BUFSZ + 32];
1497
1498 si_devpathvar(sih, varname, sizeof(varname), name);
1499
1500 return getvar(NULL, varname);
1501 }
1502
1503 /* Get a variable, but only if it has a devpath prefix */
1504 int si_getdevpathintvar(si_t *sih, const char *name)
1505 {
1506 #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
1507 return getintvar(NULL, name);
1508 #else
1509 char varname[SI_DEVPATH_BUFSZ + 32];
1510
1511 si_devpathvar(sih, varname, sizeof(varname), name);
1512
1513 return getintvar(NULL, varname);
1514 #endif
1515 }
1516
1517 char *si_getnvramflvar(si_t *sih, const char *name)
1518 {
1519 return getvar(NULL, name);
1520 }
1521
1522 /* Concatenate the dev path with a varname into the given 'var' buffer
1523 * and return the 'var' pointer.
1524 * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned.
1525 * On overflow, the first char will be set to '\0'.
1526 */
1527 static char *si_devpathvar(si_t *sih, char *var, int len, const char *name)
1528 {
1529 uint path_len;
1530
1531 if (!var || len <= 0)
1532 return var;
1533
1534 if (si_devpath(sih, var, len) == 0) {
1535 path_len = strlen(var);
1536
1537 if (strlen(name) + 1 > (uint) (len - path_len))
1538 var[0] = '\0';
1539 else
1540 strncpy(var + path_len, name, len - path_len - 1);
1541 }
1542
1543 return var;
1544 }
1545
1546 /* return true if PCIE capability exists in the pci config space */
1547 static __used bool si_ispcie(si_info_t *sii)
1548 {
1549 u8 cap_ptr;
1550
1551 if (sii->pub.bustype != PCI_BUS)
1552 return false;
1553
1554 cap_ptr =
1555 pcicore_find_pci_capability(sii->osh, PCI_CAP_PCIECAP_ID, NULL,
1556 NULL);
1557 if (!cap_ptr)
1558 return false;
1559
1560 return true;
1561 }
1562
1563 #ifdef BCMSDIO
1564 /* initialize the sdio core */
1565 void si_sdio_init(si_t *sih)
1566 {
1567 si_info_t *sii = SI_INFO(sih);
1568
1569 if (((sih->buscoretype == PCMCIA_CORE_ID) && (sih->buscorerev >= 8)) ||
1570 (sih->buscoretype == SDIOD_CORE_ID)) {
1571 uint idx;
1572 sdpcmd_regs_t *sdpregs;
1573
1574 /* get the current core index */
1575 idx = sii->curidx;
1576 ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0));
1577
1578 /* switch to sdio core */
1579 sdpregs = (sdpcmd_regs_t *) si_setcore(sih, PCMCIA_CORE_ID, 0);
1580 if (!sdpregs)
1581 sdpregs =
1582 (sdpcmd_regs_t *) si_setcore(sih, SDIOD_CORE_ID, 0);
1583 ASSERT(sdpregs);
1584
1585 SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs));
1586
1587 /* enable backplane error and core interrupts */
1588 W_REG(sii->osh, &sdpregs->hostintmask, I_SBINT);
1589 W_REG(sii->osh, &sdpregs->sbintmask,
1590 (I_SB_SERR | I_SB_RESPERR | (1 << idx)));
1591
1592 /* switch back to previous core */
1593 si_setcoreidx(sih, idx);
1594 }
1595
1596 /* enable interrupts */
1597 bcmsdh_intr_enable(sii->sdh);
1598
1599 }
1600 #endif /* BCMSDIO */
1601
1602 bool si_pci_war16165(si_t *sih)
1603 {
1604 si_info_t *sii;
1605
1606 sii = SI_INFO(sih);
1607
1608 return PCI(sii) && (sih->buscorerev <= 10);
1609 }
1610
1611 void si_pci_up(si_t *sih)
1612 {
1613 si_info_t *sii;
1614
1615 sii = SI_INFO(sih);
1616
1617 /* if not pci bus, we're done */
1618 if (sih->bustype != PCI_BUS)
1619 return;
1620
1621 if (PCI_FORCEHT(sii))
1622 _si_clkctl_cc(sii, CLK_FAST);
1623
1624 if (PCIE(sii))
1625 pcicore_up(sii->pch, SI_PCIUP);
1626
1627 }
1628
1629 /* Unconfigure and/or apply various WARs when system is going to sleep mode */
1630 void si_pci_sleep(si_t *sih)
1631 {
1632 si_info_t *sii;
1633
1634 sii = SI_INFO(sih);
1635
1636 pcicore_sleep(sii->pch);
1637 }
1638
1639 /* Unconfigure and/or apply various WARs when going down */
1640 void si_pci_down(si_t *sih)
1641 {
1642 si_info_t *sii;
1643
1644 sii = SI_INFO(sih);
1645
1646 /* if not pci bus, we're done */
1647 if (sih->bustype != PCI_BUS)
1648 return;
1649
1650 /* release FORCEHT since chip is going to "down" state */
1651 if (PCI_FORCEHT(sii))
1652 _si_clkctl_cc(sii, CLK_DYNAMIC);
1653
1654 pcicore_down(sii->pch, SI_PCIDOWN);
1655 }
1656
1657 /*
1658 * Configure the pci core for pci client (NIC) action
1659 * coremask is the bitvec of cores by index to be enabled.
1660 */
1661 void si_pci_setup(si_t *sih, uint coremask)
1662 {
1663 si_info_t *sii;
1664 struct sbpciregs *pciregs = NULL;
1665 u32 siflag = 0, w;
1666 uint idx = 0;
1667
1668 sii = SI_INFO(sih);
1669
1670 if (sii->pub.bustype != PCI_BUS)
1671 return;
1672
1673 ASSERT(PCI(sii) || PCIE(sii));
1674 ASSERT(sii->pub.buscoreidx != BADIDX);
1675
1676 if (PCI(sii)) {
1677 /* get current core index */
1678 idx = sii->curidx;
1679
1680 /* we interrupt on this backplane flag number */
1681 siflag = si_flag(sih);
1682
1683 /* switch over to pci core */
1684 pciregs = (struct sbpciregs *)si_setcoreidx(sih, sii->pub.buscoreidx);
1685 }
1686
1687 /*
1688 * Enable sb->pci interrupts. Assume
1689 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
1690 */
1691 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
1692 /* pci config write to set this core bit in PCIIntMask */
1693 pci_read_config_dword(sii->osh->pdev, PCI_INT_MASK, &w);
1694 w |= (coremask << PCI_SBIM_SHIFT);
1695 pci_write_config_dword(sii->osh->pdev, PCI_INT_MASK, w);
1696 } else {
1697 /* set sbintvec bit for our flag number */
1698 si_setint(sih, siflag);
1699 }
1700
1701 if (PCI(sii)) {
1702 OR_REG(sii->osh, &pciregs->sbtopci2,
1703 (SBTOPCI_PREF | SBTOPCI_BURST));
1704 if (sii->pub.buscorerev >= 11) {
1705 OR_REG(sii->osh, &pciregs->sbtopci2,
1706 SBTOPCI_RC_READMULTI);
1707 w = R_REG(sii->osh, &pciregs->clkrun);
1708 W_REG(sii->osh, &pciregs->clkrun,
1709 (w | PCI_CLKRUN_DSBL));
1710 w = R_REG(sii->osh, &pciregs->clkrun);
1711 }
1712
1713 /* switch back to previous core */
1714 si_setcoreidx(sih, idx);
1715 }
1716 }
1717
1718 /*
1719 * Fixup SROMless PCI device's configuration.
1720 * The current core may be changed upon return.
1721 */
1722 int si_pci_fixcfg(si_t *sih)
1723 {
1724 uint origidx, pciidx;
1725 struct sbpciregs *pciregs = NULL;
1726 sbpcieregs_t *pcieregs = NULL;
1727 void *regs = NULL;
1728 u16 val16, *reg16 = NULL;
1729
1730 si_info_t *sii = SI_INFO(sih);
1731
1732 ASSERT(sii->pub.bustype == PCI_BUS);
1733
1734 /* Fixup PI in SROM shadow area to enable the correct PCI core access */
1735 /* save the current index */
1736 origidx = si_coreidx(&sii->pub);
1737
1738 /* check 'pi' is correct and fix it if not */
1739 if (sii->pub.buscoretype == PCIE_CORE_ID) {
1740 pcieregs =
1741 (sbpcieregs_t *) si_setcore(&sii->pub, PCIE_CORE_ID, 0);
1742 regs = pcieregs;
1743 ASSERT(pcieregs != NULL);
1744 reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
1745 } else if (sii->pub.buscoretype == PCI_CORE_ID) {
1746 pciregs = (struct sbpciregs *)si_setcore(&sii->pub, PCI_CORE_ID, 0);
1747 regs = pciregs;
1748 ASSERT(pciregs != NULL);
1749 reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
1750 }
1751 pciidx = si_coreidx(&sii->pub);
1752 val16 = R_REG(sii->osh, reg16);
1753 if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {
1754 val16 =
1755 (u16) (pciidx << SRSH_PI_SHIFT) | (val16 &
1756 ~SRSH_PI_MASK);
1757 W_REG(sii->osh, reg16, val16);
1758 }
1759
1760 /* restore the original index */
1761 si_setcoreidx(&sii->pub, origidx);
1762
1763 pcicore_hwup(sii->pch);
1764 return 0;
1765 }
1766
1767 /* mask&set gpiocontrol bits */
1768 u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)
1769 {
1770 uint regoff;
1771
1772 regoff = 0;
1773
1774 /* gpios could be shared on router platforms
1775 * ignore reservation if it's high priority (e.g., test apps)
1776 */
1777 if ((priority != GPIO_HI_PRIORITY) &&
1778 (sih->bustype == SI_BUS) && (val || mask)) {
1779 mask = priority ? (si_gpioreservation & mask) :
1780 ((si_gpioreservation | mask) & ~(si_gpioreservation));
1781 val &= mask;
1782 }
1783
1784 regoff = offsetof(chipcregs_t, gpiocontrol);
1785 return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
1786 }
1787
1788 /* Return the size of the specified SOCRAM bank */
1789 static uint
1790 socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index,
1791 u8 mem_type)
1792 {
1793 uint banksize, bankinfo;
1794 uint bankidx = index | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
1795
1796 ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM);
1797
1798 W_REG(sii->osh, &regs->bankidx, bankidx);
1799 bankinfo = R_REG(sii->osh, &regs->bankinfo);
1800 banksize =
1801 SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1);
1802 return banksize;
1803 }
1804
1805 /* Return the RAM size of the SOCRAM core */
1806 u32 si_socram_size(si_t *sih)
1807 {
1808 si_info_t *sii;
1809 uint origidx;
1810 uint intr_val = 0;
1811
1812 sbsocramregs_t *regs;
1813 bool wasup;
1814 uint corerev;
1815 u32 coreinfo;
1816 uint memsize = 0;
1817
1818 sii = SI_INFO(sih);
1819
1820 /* Block ints and save current core */
1821 INTR_OFF(sii, intr_val);
1822 origidx = si_coreidx(sih);
1823
1824 /* Switch to SOCRAM core */
1825 regs = si_setcore(sih, SOCRAM_CORE_ID, 0);
1826 if (!regs)
1827 goto done;
1828
1829 /* Get info for determining size */
1830 wasup = si_iscoreup(sih);
1831 if (!wasup)
1832 si_core_reset(sih, 0, 0);
1833 corerev = si_corerev(sih);
1834 coreinfo = R_REG(sii->osh, &regs->coreinfo);
1835
1836 /* Calculate size from coreinfo based on rev */
1837 if (corerev == 0)
1838 memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
1839 else if (corerev < 3) {
1840 memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
1841 memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
1842 } else if ((corerev <= 7) || (corerev == 12)) {
1843 uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
1844 uint bsz = (coreinfo & SRCI_SRBSZ_MASK);
1845 uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
1846 if (lss != 0)
1847 nb--;
1848 memsize = nb * (1 << (bsz + SR_BSZ_BASE));
1849 if (lss != 0)
1850 memsize += (1 << ((lss - 1) + SR_BSZ_BASE));
1851 } else {
1852 u8 i;
1853 uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
1854 for (i = 0; i < nb; i++)
1855 memsize +=
1856 socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
1857 }
1858
1859 /* Return to previous state and core */
1860 if (!wasup)
1861 si_core_disable(sih, 0);
1862 si_setcoreidx(sih, origidx);
1863
1864 done:
1865 INTR_RESTORE(sii, intr_val);
1866
1867 return memsize;
1868 }
1869
1870 void si_chipcontrl_epa4331(si_t *sih, bool on)
1871 {
1872 si_info_t *sii;
1873 chipcregs_t *cc;
1874 uint origidx;
1875 u32 val;
1876
1877 sii = SI_INFO(sih);
1878 origidx = si_coreidx(sih);
1879
1880 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
1881
1882 val = R_REG(sii->osh, &cc->chipcontrol);
1883
1884 if (on) {
1885 if (sih->chippkg == 9 || sih->chippkg == 0xb) {
1886 /* Ext PA Controls for 4331 12x9 Package */
1887 W_REG(sii->osh, &cc->chipcontrol, val |
1888 (CCTRL4331_EXTPA_EN |
1889 CCTRL4331_EXTPA_ON_GPIO2_5));
1890 } else {
1891 /* Ext PA Controls for 4331 12x12 Package */
1892 W_REG(sii->osh, &cc->chipcontrol,
1893 val | (CCTRL4331_EXTPA_EN));
1894 }
1895 } else {
1896 val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
1897 W_REG(sii->osh, &cc->chipcontrol, val);
1898 }
1899
1900 si_setcoreidx(sih, origidx);
1901 }
1902
1903 /* Enable BT-COEX & Ex-PA for 4313 */
1904 void si_epa_4313war(si_t *sih)
1905 {
1906 si_info_t *sii;
1907 chipcregs_t *cc;
1908 uint origidx;
1909
1910 sii = SI_INFO(sih);
1911 origidx = si_coreidx(sih);
1912
1913 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
1914
1915 /* EPA Fix */
1916 W_REG(sii->osh, &cc->gpiocontrol,
1917 R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
1918
1919 si_setcoreidx(sih, origidx);
1920 }
1921
1922 /* check if the device is removed */
1923 bool si_deviceremoved(si_t *sih)
1924 {
1925 u32 w;
1926 si_info_t *sii;
1927
1928 sii = SI_INFO(sih);
1929
1930 switch (sih->bustype) {
1931 case PCI_BUS:
1932 ASSERT(sii->osh != NULL);
1933 pci_read_config_dword(sii->osh->pdev, PCI_CFG_VID, &w);
1934 if ((w & 0xFFFF) != VENDOR_BROADCOM)
1935 return true;
1936 break;
1937 }
1938 return false;
1939 }
1940
1941 bool si_is_sprom_available(si_t *sih)
1942 {
1943 if (sih->ccrev >= 31) {
1944 si_info_t *sii;
1945 uint origidx;
1946 chipcregs_t *cc;
1947 u32 sromctrl;
1948
1949 if ((sih->cccaps & CC_CAP_SROM) == 0)
1950 return false;
1951
1952 sii = SI_INFO(sih);
1953 origidx = sii->curidx;
1954 cc = si_setcoreidx(sih, SI_CC_IDX);
1955 sromctrl = R_REG(sii->osh, &cc->sromcontrol);
1956 si_setcoreidx(sih, origidx);
1957 return sromctrl & SRC_PRESENT;
1958 }
1959
1960 switch (sih->chip) {
1961 case BCM4329_CHIP_ID:
1962 return (sih->chipst & CST4329_SPROM_SEL) != 0;
1963 case BCM4319_CHIP_ID:
1964 return (sih->chipst & CST4319_SPROM_SEL) != 0;
1965 case BCM4336_CHIP_ID:
1966 return (sih->chipst & CST4336_SPROM_PRESENT) != 0;
1967 case BCM4330_CHIP_ID:
1968 return (sih->chipst & CST4330_SPROM_PRESENT) != 0;
1969 case BCM4313_CHIP_ID:
1970 return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
1971 case BCM4331_CHIP_ID:
1972 return (sih->chipst & CST4331_SPROM_PRESENT) != 0;
1973 default:
1974 return true;
1975 }
1976 }
1977
1978 bool si_is_otp_disabled(si_t *sih)
1979 {
1980 switch (sih->chip) {
1981 case BCM4329_CHIP_ID:
1982 return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) ==
1983 CST4329_OTP_PWRDN;
1984 case BCM4319_CHIP_ID:
1985 return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) ==
1986 CST4319_OTP_PWRDN;
1987 case BCM4336_CHIP_ID:
1988 return (sih->chipst & CST4336_OTP_PRESENT) == 0;
1989 case BCM4330_CHIP_ID:
1990 return (sih->chipst & CST4330_OTP_PRESENT) == 0;
1991 case BCM4313_CHIP_ID:
1992 return (sih->chipst & CST4313_OTP_PRESENT) == 0;
1993 /* These chips always have their OTP on */
1994 case BCM43224_CHIP_ID:
1995 case BCM43225_CHIP_ID:
1996 case BCM43421_CHIP_ID:
1997 case BCM43235_CHIP_ID:
1998 case BCM43236_CHIP_ID:
1999 case BCM43238_CHIP_ID:
2000 case BCM4331_CHIP_ID:
2001 default:
2002 return false;
2003 }
2004 }
2005
2006 bool si_is_otp_powered(si_t *sih)
2007 {
2008 if (PMUCTL_ENAB(sih))
2009 return si_pmu_is_otp_powered(sih, si_osh(sih));
2010 return true;
2011 }
2012
2013 void si_otp_power(si_t *sih, bool on)
2014 {
2015 if (PMUCTL_ENAB(sih))
2016 si_pmu_otp_power(sih, si_osh(sih), on);
2017 udelay(1000);
2018 }
2019