| commit | 8fb54284ba6aa1f0d832ec015fde64ecf4bb0f4f | |
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | |
| Tue, 28 Jun 2011 19:42:56 +0000 (28 12:42 -0700) | ||
| committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | |
| Fri, 23 Sep 2011 06:35:30 +0000 (23 12:05 +0530) | ||
| tree | 1c9a5d9f0c57af407085f2d74ef8c3bd63ecb34e | treesnapshot (tar.gz zip) |
| parent | 48af9feab5e3bdf21af3a929ecc7c0b79d9a4a4e | commitdiff |
ARM: mm: Add strongly ordered descriptor support.
On certain architectures, there might be a need to mark certain
addresses with strongly ordered memory attributes to avoid ordering
issues at the interconnect level.
On OMAP4, the asynchronous bridge buffers can only be drained
with strongly ordered accesses and hence the need to mark the
memory strongly ordered.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
On certain architectures, there might be a need to mark certain
addresses with strongly ordered memory attributes to avoid ordering
issues at the interconnect level.
On OMAP4, the asynchronous bridge buffers can only be drained
with strongly ordered accesses and hence the need to mark the
memory strongly ordered.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
| arch/arm/include/asm/mach/map.h | diffblobblamehistory | |
| arch/arm/include/asm/pgtable.h | diffblobblamehistory | |
| arch/arm/mm/mmu.c | diffblobblamehistory |