From 5c1de069338fbb7fb033ada1fb9259ecdb2f6ce2 Mon Sep 17 00:00:00 2001 From: Alvaro Lopes Date: Sat, 11 Apr 2009 13:51:49 +0100 Subject: [PATCH] More patches from Oleg Belousov: * Move RAM/ROM declaration outside ALZPU core * Add correct UART baudrate generation, and declarations --- zpu/hdl/alzpu/v4/core/alzpu.vhd | 111 ++++------------- .../alzpu/v4/designs/benchmark/alzpu_config.vhd | 6 +- .../v4/designs/benchmark/alzpu_config_syn.vhd | 6 +- .../alzpu/v4/designs/benchmark/alzpu_system.vhd | 133 ++++++++++++++++++++- zpu/hdl/alzpu/v4/devices/uart.vhd | 5 +- 5 files changed, 164 insertions(+), 97 deletions(-) diff --git a/zpu/hdl/alzpu/v4/core/alzpu.vhd b/zpu/hdl/alzpu/v4/core/alzpu.vhd index b08bd06..cfb56c1 100644 --- a/zpu/hdl/alzpu/v4/core/alzpu.vhd +++ b/zpu/hdl/alzpu/v4/core/alzpu.vhd @@ -59,8 +59,25 @@ entity alzpu is io_i_busy: in std_logic; io_i_rd_data: in cpuword_type; io_o_en: out std_logic; - io_o_wr_en: out std_logic + io_o_wr_en: out std_logic; + -- ROM + + rom_o_addra: out std_logic_vector(alzpu_rom_num_bits-1 downto 0); + rom_o_addrb: out std_logic_vector(alzpu_rom_num_bits-1 downto 2); + rom_i_doa: in std_logic_vector(7 downto 0); + rom_i_dob: in cpuword_type; + rom_o_ena: out std_logic; + rom_o_enb: out std_logic; + + -- RAM + + ram_o_addra: out std_logic_vector(alzpu_ram_num_bits-1 downto 2); + ram_o_addrb: out std_logic_vector(alzpu_ram_num_bits-1 downto 2); + ram_i_doa: in cpuword_type; + ram_o_dib: out cpuword_type; + ram_o_ena: out std_logic_vector(3 downto 0); + ram_o_enb: out std_logic_vector(3 downto 0) ); end entity alzpu; @@ -98,47 +115,6 @@ component alzpu_tracer is ); end component; --- RAM - -component alzpu_ram is - port ( - clka: in std_logic; - clkb: in std_logic; - rst: in std_logic; - addra: in std_logic_vector(alzpu_ram_num_bits-1 downto 2); - addrb: in std_logic_vector(alzpu_ram_num_bits-1 downto 2); - doa: out cpuword_type; - dob: out cpuword_type; - dia: in cpuword_type; - dib: in cpuword_type; - ena: in std_logic_vector(3 downto 0); - enb: in std_logic_vector(3 downto 0); - wra: in std_logic; - wrb: in std_logic - ); -end component; - --- ROM - -component alzpu_rom is - port ( - clka: in std_logic; - clkb: in std_logic; - rst: in std_logic; - addra: in std_logic_vector(alzpu_rom_num_bits-1 downto 0); - addrb: in std_logic_vector(alzpu_rom_num_bits-1 downto 2); - ena: in std_logic; - enb: in std_logic; - wra: in std_logic; - wrb: in std_logic; - doa: out std_logic_vector(7 downto 0); - dob: out cpuword_type; - dia: in std_logic_vector(7 downto 0); - dib: in cpuword_type - ); - -end component; - --------------------------------------------------- --- Instruction fetcher signals --------------------------------------------------- @@ -262,55 +238,12 @@ signal io_B_wren: std_logic; --- RAM signals ---------- -------------------------- -signal ram_o_addra: std_logic_vector(alzpu_ram_num_bits-1 downto 2); -signal ram_o_addrb: std_logic_vector(alzpu_ram_num_bits-1 downto 2); -signal ram_i_doa: cpuword_type; -signal ram_o_dib: cpuword_type; -signal ram_o_ena: std_logic_vector(3 downto 0); -signal ram_o_enb: std_logic_vector(3 downto 0); - --------------------------- ---- ROM signals ---------- --------------------------- - -signal rom_i_dob: cpuword_type; -signal rom_o_enb: std_logic; - begin -myrom: alzpu_rom - port map ( - clka => clk, - clkb => clk, - rst => rst, - addra => ifu_o_mem_address, - addrb => std_logic_vector(ex_stackA(alzpu_rom_num_bits-1 downto 2)), -- Only accessed though LOAD - doa => ifu_i_mem_data, - dob => rom_i_dob, - dia => (others => DontCareValue), - dib => (others => DontCareValue), - ena => ifu_o_mem_read_enable, - enb => rom_o_enb, - wra => '0', - wrb => '0' - ); - -myram: alzpu_ram - port map ( - clka => clk, - clkb => clk, - rst => rst, - addra => ram_o_addra, - addrb => ram_o_addrb, - doa => ram_i_doa, - dob => open, - dia => (others =>DontCareValue), - dib => ram_o_dib, - ena => ram_o_ena, - enb => ram_o_enb, - wra => '0', - wrb => '1' - ); +rom_o_addra <= ifu_o_mem_address; +rom_o_addrb <= std_logic_vector(ex_stackA(alzpu_rom_num_bits-1 downto 2)); -- Only accessed though LOAD +ifu_i_mem_data <= rom_i_doa; +rom_o_ena <= ifu_o_mem_read_enable; ifu_i_freeze <= ex_o_stall or dec_o_busy or ex_o_break; ex_i_freeze <= dec_o_flush_ex or ex_o_break; diff --git a/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_config.vhd b/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_config.vhd index bbc9e4d..9ad2cb3 100644 --- a/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_config.vhd +++ b/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_config.vhd @@ -46,7 +46,7 @@ package alzpu_config is -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := '0'; -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + constant ZPU_Frequency : integer := 50; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 15; @@ -73,6 +73,10 @@ package alzpu_config is -- Generate trace output or not. constant alzpu_tracer_enabled: boolean := true; + -- UART definitions + constant uart_baud_rate: integer := 38600; + constant brgen_count: integer := (ZPU_Frequency * 1e6) / uart_baud_rate; + -- Use external validator file. Do not enable unless you know what you're doing. constant alzpu_validator_enabled: boolean := false; diff --git a/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_config_syn.vhd b/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_config_syn.vhd index 006e31e..fd9ab33 100644 --- a/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_config_syn.vhd +++ b/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_config_syn.vhd @@ -46,7 +46,7 @@ package alzpu_config is -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := '0'; -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + constant ZPU_Frequency : integer := 50; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 15; @@ -80,6 +80,10 @@ package alzpu_config is constant alzpu_debug_ram_accesses: boolean := false; + -- UART definitions + constant uart_baud_rate: integer := 38600; + constant brgen_count: integer := (ZPU_Frequency * 1e6) / uart_baud_rate; + -- Emulated instruction implementation constant implement_loadb: boolean := false; diff --git a/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_system.vhd b/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_system.vhd index 6a79d98..c8bd217 100644 --- a/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_system.vhd +++ b/zpu/hdl/alzpu/v4/designs/benchmark/alzpu_system.vhd @@ -55,9 +55,9 @@ architecture behave of alzpu_system is component alzpu is port ( clk: in std_logic; - rst: in std_logic; + rst: in std_logic; interrupt: in std_logic; - break: out std_logic; + break: out std_logic; io_o_addr: out std_logic_vector(maxAddrBit downto minAddrBit); io_o_wr_data: out cpuword_type; @@ -66,13 +66,64 @@ architecture behave of alzpu_system is io_i_busy: in std_logic; io_i_rd_data: in cpuword_type; io_o_en: out std_logic; - io_o_wr_en: out std_logic + io_o_wr_en: out std_logic; + rom_o_addra: out std_logic_vector(alzpu_rom_num_bits-1 downto 0); + rom_o_addrb: out std_logic_vector(alzpu_rom_num_bits-1 downto 2); + rom_i_doa: in std_logic_vector(7 downto 0); + rom_i_dob: in cpuword_type; + rom_o_ena: out std_logic; + rom_o_enb: out std_logic; + + ram_o_addra: out std_logic_vector(alzpu_ram_num_bits-1 downto 2); + ram_o_addrb: out std_logic_vector(alzpu_ram_num_bits-1 downto 2); + ram_i_doa: in cpuword_type; + ram_o_dib: out cpuword_type; + ram_o_ena: out std_logic_vector(3 downto 0); + ram_o_enb: out std_logic_vector(3 downto 0) + ); + end component; + + component alzpu_rom is + port ( + clka: in std_logic; + clkb: in std_logic; + rst: in std_logic; + addra: in std_logic_vector(alzpu_rom_num_bits-1 downto 0); + addrb: in std_logic_vector(alzpu_rom_num_bits-1 downto 2); + ena: in std_logic; + enb: in std_logic; + wra: in std_logic; + wrb: in std_logic; + doa: out std_logic_vector(7 downto 0); + dob: out cpuword_type; + dia: in std_logic_vector(7 downto 0); + dib: in cpuword_type ); end component; + component alzpu_ram is + port ( + clka: in std_logic; + clkb: in std_logic; + rst: in std_logic; + addra: in std_logic_vector(alzpu_ram_num_bits-1 downto 2); + addrb: in std_logic_vector(alzpu_ram_num_bits-1 downto 2); + doa: out cpuword_type; + dob: out cpuword_type; + dia: in cpuword_type; + dib: in cpuword_type; + ena: in std_logic_vector(3 downto 0); + enb: in std_logic_vector(3 downto 0); + wra: in std_logic; + wrb: in std_logic + ); + end component; component timer is + generic( + MHZ: integer range 0 to 500 := 50 + ); port( slave_in : in zpu_slave_in_type; slave_out : out zpu_slave_out_type @@ -80,6 +131,9 @@ architecture behave of alzpu_system is end component; component uart is + generic( + count : integer range 0 to 65535 + ); port( slave_in : in zpu_slave_in_type; slave_out : out zpu_slave_out_type; @@ -105,6 +159,21 @@ architecture behave of alzpu_system is signal uart_si: zpu_slave_in_type; signal uart_so: zpu_slave_out_type; signal dummy_so: zpu_slave_out_type; + + signal rom_o_addra: std_logic_vector(alzpu_rom_num_bits-1 downto 0); + signal rom_o_addrb: std_logic_vector(alzpu_rom_num_bits-1 downto 2); + signal rom_i_doa: std_logic_vector(7 downto 0); + signal rom_i_dob: cpuword_type; + signal rom_o_ena: std_logic; + signal rom_o_enb: std_logic; + + signal ram_o_addra: std_logic_vector(alzpu_ram_num_bits-1 downto 2); + signal ram_o_addrb: std_logic_vector(alzpu_ram_num_bits-1 downto 2); + signal ram_i_doa: cpuword_type; + signal ram_o_dib: cpuword_type; + signal ram_o_ena: std_logic_vector(3 downto 0); + signal ram_o_enb: std_logic_vector(3 downto 0); + begin dummy_slave: alzpu_slave_unconnected @@ -135,12 +204,18 @@ begin ); mytimer: timer + generic map ( + MHZ => ZPU_Frequency + ) port map ( slave_in => timer_si, slave_out => timer_so ); myuart: uart + generic map( + count => brgen_count + ) port map ( slave_in => uart_si, slave_out => uart_so, @@ -159,10 +234,58 @@ begin io_i_rd_data => io_i_rd_data, io_o_en => io_o_en, io_o_wr_en => io_o_wr_en, - interrupt => '0', - break => open + interrupt => '0', + break => open, + + rom_o_addra => rom_o_addra, + rom_o_addrb => rom_o_addrb, + rom_i_doa => rom_i_doa, + rom_i_dob => rom_i_dob, + rom_o_ena => rom_o_ena, + rom_o_enb => rom_o_enb, + + ram_o_addra => ram_o_addra, + ram_o_addrb => ram_o_addrb, + ram_i_doa => ram_i_doa, + ram_o_dib => ram_o_dib, + ram_o_ena => ram_o_ena, + ram_o_enb => ram_o_enb ); + rom: alzpu_rom + port map ( + clka => clk, + clkb => clk, + rst => rst, + addra => rom_o_addra, + addrb => rom_o_addrb, + doa => rom_i_doa, + dob => rom_i_dob, + dia => (others => DontCareValue), + dib => (others => DontCareValue), + ena => rom_o_ena, + enb => rom_o_enb, + wra => '0', + wrb => '0' + ); + + ram: alzpu_ram + port map ( + clka => clk, + clkb => clk, + rst => rst, + addra => ram_o_addra, + addrb => ram_o_addrb, + doa => ram_i_doa, + dob => open, + dia => (others =>DontCareValue), + dib => ram_o_dib, + ena => ram_o_ena, + enb => ram_o_enb, + wra => '0', + wrb => '1' + ); + iosi.clk <= clk; iosi.rst <= rst; iosi.dati <= std_logic_vector(io_o_wr_data); diff --git a/zpu/hdl/alzpu/v4/devices/uart.vhd b/zpu/hdl/alzpu/v4/devices/uart.vhd index aa8aa8d..b71bae1 100644 --- a/zpu/hdl/alzpu/v4/devices/uart.vhd +++ b/zpu/hdl/alzpu/v4/devices/uart.vhd @@ -7,6 +7,9 @@ library work; use work.alzpupkg.all; entity uart is + generic( + count : integer range 0 to 65535 + ); port( slave_in : in zpu_slave_in_type; slave_out : out zpu_slave_out_type; @@ -47,7 +50,7 @@ begin mybrgen: brgen generic map ( - count => 1302 + count => count ) port map ( clk_i => slave_in.clk, -- 2.11.4.GIT