design/wrapped_stack_machine.v

   1 /*
   2  * This is a version of stack machine with 16-bit data ports
   3  * on *both* Wishbone interfaces (data interface is wrapped).
   4  * CLK_I and RST_I signals are shared between interfaces.
   5  * Two interfaces can, but don't have to, be made to access the same memory map.
   6  * Instructions interface never performs writes (its WE_O is hardwired to low).
   7  *
   8  * | *WISHBONE DATASHEET*                                                      |
   9  * |---------------------------------------------------------------------------|
  10  * | *Description*                   | *Specification*                         |
  11  * |---------------------------------+-----------------------------------------|
  12  * | General description             | stack machine core data interface       |
  13  * |---------------------------------+-----------------------------------------|
  14  * | Supported cycles                | MASTER, pipelined READ/WRITE            |
  15  * |---------------------------------+-----------------------------------------|
  16  * | Data port, size                 | 16-bit                                  |
  17  * | Data port, granularity          | 16-bit                                  |
  18  * | Data port, maximum operand size | 16-bit                                  |
  19  * | Data transfer ordering          | Big endian and/or little endian         |
  20  * | Data transfer ordering          | Undefined                               |
  21  * | Address port, size              | 20-bit                                  |
  22  * |---------------------------------+-----------------------------------------|
  23  * | Clock frequency constraints     | NONE                                    |
  24  * |---------------------------------+-----------------------------------------|
  25  * |                                 | *Signal name*    | *WISHBONE Equiv.*    |
  26  * |                                 |------------------+----------------------|
  27  * |                                 | D_ACK_I          | ACK_I                |
  28  * |                                 | D_ADR_O          | ADR_O()              |
  29  * | Supported signal list and cross | CLK_I            | CLK_I                |
  30  * |     reference to equivalent     | D_DAT_I          | DAT_I()              |
  31  * |     WISHBONE signals            | D_DAT_O          | DAT_O()              |
  32  * |                                 | D_SEL_O          | SEL_O                |
  33  * |                                 | D_STB_O          | STB_O                |
  34  * |                                 | D_CYC_O          | CYC_O                |
  35  * |                                 | D_WE_O           | WE_O                 |
  36  * |                                 | RST_I            | RST_I                |
  37  * |                                 | D_STALL_I        | STALL_I              |
  38  * |---------------------------------+-----------------------------------------|
  39  * | Special requirements            | NONE                                    |
  40  *
  41  *
  42  * | *WISHBONE DATASHEET*                                                      |
  43  * |---------------------------------------------------------------------------|
  44  * | *Description*                   | *Specification*                         |
  45  * |---------------------------------+-----------------------------------------|
  46  * | General description             | stack machine core instructions         |
  47  * |                                 |     interface                           |
  48  * |---------------------------------+-----------------------------------------|
  49  * | Supported cycles                | MASTER, pipelined READ                  |
  50  * |---------------------------------+-----------------------------------------|
  51  * | Data port, size                 | 16-bit                                  |
  52  * | Data port, granularity          | 16-bit                                  |
  53  * | Data port, maximum operand size | 16-bit                                  |
  54  * | Data transfer ordering          | Big endian and/or little endian         |
  55  * | Data transfer ordering          | Undefined                               |
  56  * | Address port, size              | 20-bit                                  |
  57  * |---------------------------------+-----------------------------------------|
  58  * | Clock frequency constraints     | NONE                                    |
  59  * |---------------------------------+-----------------------------------------|
  60  * |                                 | *Signal name*    | *WISHBONE Equiv.*    |
  61  * |                                 |------------------+----------------------|
  62  * |                                 | I_ACK_I          | ACK_I                |
  63  * |                                 | I_ADR_O          | ADR_O()              |
  64  * | Supported signal list and cross | CLK_I            | CLK_I                |
  65  * |     reference to equivalent     | I_DAT_I          | DAT_I()              |
  66  * |     WISHBONE signals            | I_DAT_O          | DAT_O()              |
  67  * |                                 | I_SEL_O          | SEL_O                |
  68  * |                                 | I_STB_O          | STB_O                |
  69  * |                                 | I_CYC_O          | CYC_O                |
  70  * |                                 | I_WE_O           | WE_O                 |
  71  * |                                 | RST_I            | RST_I                |
  72  * |                                 | I_STALL_I        | STALL_I              |
  73  * |---------------------------------+-----------------------------------------|
  74  * | Special requirements            | NONE                                    |
  75  */
  76
  77 `default_nettype none
  78
  79 module wrapped_stack_machine
  80   (
  81    /* Those 2 are supposed to be common for both wishbone interfaces */
  82    input wire         CLK_I,
  83    input wire         RST_I,
  84
  85    /* Instruction reading interface */
  86    input wire         I_ACK_I,
  87    output wire [19:0] I_ADR_O,
  88    input wire [15:0]  I_DAT_I,
  89    output wire [15:0] I_DAT_O, /* Not used, interface read-only */
  90    output wire        I_STB_O,
  91    output wire        I_CYC_O,
  92    output wire        I_WE_O, /* Always 0, interface read-only */
  93    input wire         I_STALL_I,
  94
  95    /* Data interface */
  96    input wire         D_ACK_I,
  97    output wire [19:0] D_ADR_O,
  98    input wire [15:0]  D_DAT_I,
  99    output wire [15:0] D_DAT_O,
 100    output wire        D_STB_O,
 101    output wire        D_CYC_O,
 102    output wire        D_WE_O,
 103    input wire         D_STALL_I,
 104
 105    /* non-wishbone */
 106    output wire        finished
 107    );
 108
 109    wire               D_RAW_ACK_I;
 110    wire [20:0]        D_RAW_ADR_O;
 111    wire [31:0]        D_RAW_DAT_I;
 112    wire [31:0]        D_RAW_DAT_O;
 113    wire [3:0]         D_RAW_SEL_O;
 114    wire               D_RAW_STB_O;
 115    wire               D_RAW_CYC_O;
 116    wire               D_RAW_WE_O;
 117    wire               D_RAW_STALL_I;
 118
 119    stack_machine_new stack_machine
 120      (
 121       .CLK_I(CLK_I),
 122       .RST_I(RST_I),
 123
 124       /* Instruction reading interface */
 125       .I_ACK_I(I_ACK_I),
 126       .I_ADR_O(I_ADR_O),
 127       .I_DAT_I(I_DAT_I),
 128       .I_DAT_O(I_DAT_O),
 129       .I_STB_O(I_STB_O),
 130       .I_CYC_O(I_CYC_O),
 131       .I_WE_O(I_WE_O),
 132       .I_STALL_I(I_STALL_I),
 133
 134       /* Data interface */
 135       .D_ACK_I(D_RAW_ACK_I),
 136       .D_ADR_O(D_RAW_ADR_O),
 137       .D_DAT_I(D_RAW_DAT_I),
 138       .D_DAT_O(D_RAW_DAT_O),
 139       .D_SEL_O(D_RAW_SEL_O),
 140       .D_STB_O(D_RAW_STB_O),
 141       .D_CYC_O(D_RAW_CYC_O),
 142       .D_WE_O(D_RAW_WE_O),
 143       .D_STALL_I(D_RAW_STALL_I),
 144
 145       .finished(finished)
 146       );
 147
 148    interface_wrapper wrapper
 149      (
 150       .CLK_I(CLK_I),
 151       .RST_I(RST_I),
 152
 153       .RAW_ACK_I(D_RAW_ACK_I),
 154       .RAW_ADR_O(D_RAW_ADR_O),
 155       .RAW_DAT_I(D_RAW_DAT_I),
 156       .RAW_DAT_O(D_RAW_DAT_O),
 157       .RAW_SEL_O(D_RAW_SEL_O),
 158       .RAW_STB_O(D_RAW_STB_O),
 159       .RAW_CYC_O(D_RAW_CYC_O),
 160       .RAW_WE_O(D_RAW_WE_O),
 161       .RAW_STALL_I(D_RAW_STALL_I),
 162
 163       .WRAPPED_ACK_I(D_ACK_I),
 164       .WRAPPED_ADR_O(D_ADR_O),
 165       .WRAPPED_DAT_I(D_DAT_I),
 166       .WRAPPED_DAT_O(D_DAT_O),
 167       .WRAPPED_STB_O(D_STB_O),
 168       .WRAPPED_CYC_O(D_CYC_O),
 169       .WRAPPED_WE_O(D_WE_O),
 170       .WRAPPED_STALL_I(D_STALL_I)
 171       );
 172 endmodule // wrapped_stack_machine