arch/ppc-sam440/include/asm/amcc440.h

   1 #ifndef ASM_AMCC440_H
   2 #define ASM_AMCC440_H
   3
   4 #include <asm/cpu.h>
   5
   6 #define CLID_I2C_AMCC440        "hidd.i2c.amcc440"
   7
   8 typedef struct cpuregs {
   9     uint32_t    gpr[32];
  10     uint32_t    srr0;
  11     uint32_t    srr1;
  12     uint32_t    ctr;
  13     uint32_t    lr;
  14     uint32_t    xer;
  15     uint32_t    ccr;
  16     uint32_t    dar;
  17     uint32_t    dsisr;
  18 } cpuregs_t;
  19
  20 typedef struct fpuregs {
  21     double      fpr[32];
  22     uint64_t    fpscr;
  23 } fpuregs_t;
  24
  25 typedef struct AROSCPUContext {
  26     cpuregs_t   cpu;
  27     fpuregs_t   fpu;
  28 } context_t;
  29
  30 /* Machine State Register */
  31 #define MSR_POW 0x00040000
  32 #define MSR_CE  0x00020000
  33 #define MSR_EE  0x00008000
  34 #define MSR_PR  0x00004000
  35 #define MSR_FP  0x00002000
  36 #define MSR_ME  0x00001000
  37 #define MSR_FE0 0x00000800
  38 #define MSR_DWE 0x00000400
  39 #define MSR_DE  0x00000200
  40 #define MSR_FE1 0x00000100
  41 #define MSR_IS  0x00000020
  42 #define MSR_DS  0x00000010
  43
  44 /* MMU TLB word 0 */
  45 #define TLB_V   0x00000200
  46
  47 /* MMU protection bits (TLB word 2) */
  48 #define TLB_SR  0x00000001      /* Supervisor State Read Enable */
  49 #define TLB_SW  0x00000002      /* Supervisor State Write Enable */
  50 #define TLB_SX  0x00000004      /* Supervisor State Execute Enable */
  51 #define TLB_UR  0x00000008      /* User State Read Enable */
  52 #define TLB_UW  0x00000010      /* User State Write Enable */
  53 #define TLB_UX  0x00000020      /* User State Execute Enable */
  54 #define TLB_E   0x00000080      /* Little Endian Enable */
  55 #define TLB_G   0x00000100      /* Guarded */
  56 #define TLB_M   0x00000200      /* Memory Coherence Required */
  57 #define TLB_I   0x00000400      /* Caching Inhibited */
  58 #define TLB_W   0x00000800      /* Write Through */
  59
  60 /* SPR registers */
  61 #define XER     0x001   /* Integer Exception Register */
  62 #define LR      0x008   /* Link Register */
  63 #define CTR     0x009   /* Count Register */
  64 #define DEC     0x016   /* Decrementer */
  65 #define SRR0    0x01A   /* Save/Restore Register 0 */
  66 #define SRR1    0x01B   /* Save/Restore Register 1 */
  67 #define PID     0x030   /* Process ID */
  68 #define DECAR   0x036   /* Decrementer Auto-Reload */
  69 #define CSRR0   0x03A   /* Critical Save/Restore Register 0 */
  70 #define CSRR1   0x03B   /* Critical Save/Restore Register 1 */
  71 #define DEAR    0x03D   /* Data Exception Address Register */
  72 #define ESR     0x03E   /* Exception Syndrome Register */
  73 #define IVPR    0x03F   /* Interrupt Vector Prefix Register */
  74 #define USPRG0  0x100   /* User Special Purpose Register General 0 */
  75 #define SPRG4U  0x104   /* Special Purpose Register General 4. Usermode - read only */
  76 #define SPRG5U  0x105   /* Special Purpose Register General 5. Usermode - read only */
  77 #define SPRG6U  0x106   /* Special Purpose Register General 6. Usermode - read only */
  78 #define SPRG7U  0x107   /* Special Purpose Register General 7. Usermode - read only */
  79 #define TBLU    0x10C   /* Time Base Lower */
  80 #define TBUU    0x10D   /* Time Base Upper */
  81 #define SPRG0   0x110   /* Special Purpose Register General 0 */
  82 #define SPRG1   0x111   /* Special Purpose Register General 1 */
  83 #define SPRG2   0x112   /* Special Purpose Register General 2 */
  84 #define SPRG3   0x113   /* Special Purpose Register General 3 */
  85 #define SPRG4   0x114   /* Special Purpose Register General 4 */
  86 #define SPRG5   0x115   /* Special Purpose Register General 5 */
  87 #define SPRG6   0x116   /* Special Purpose Register General 6 */
  88 #define SPRG7   0x117   /* Special Purpose Register General 7 */
  89 #define TBL     0x11C   /* Time Base Lower */
  90 #define TBU     0x11D   /* Time Base Upper */
  91 #define PIR     0x11E   /* Processor ID Register */
  92 #define PVR     0x11F   /* Processor Version Register */
  93 #define DBSR    0x130   /* Debug Status Register */
  94 #define DBCR0   0x134   /* Debug Control Register 0 */
  95 #define DBCR1   0x135   /* Debug Control Register 1 */
  96 #define DBCR2   0x136   /* Debug Control Register 2 */
  97 #define IAC1    0x138   /* Instruction Address Compare 1 */
  98 #define IAC2    0x139   /* Instruction Address Compare 2 */
  99 #define IAC3    0x13A   /* Instruction Address Compare 3 */
 100 #define IAC4    0x13B   /* Instruction Address Compare 4 */
 101 #define DAC1    0x13C   /* Data Address Compare 1 */
 102 #define DAC2    0x13D   /* Data Address Compare 2 */
 103 #define DVC1    0x13E   /* Data Value Compare 1 */
 104 #define DVC2    0x13F   /* Data Value Compare 2 */
 105 #define TSR     0x150   /* Timer Status Register */
 106 #define TCR     0x154   /* Timer Control Register */
 107 #define IVOR0   0x190   /* Interrupt Vector Offset Register 0 */
 108 #define IVOR1   0x191   /* Interrupt Vector Offset Register 1 */
 109 #define IVOR2   0x192   /* Interrupt Vector Offset Register 2 */
 110 #define IVOR3   0x193   /* Interrupt Vector Offset Register 3 */
 111 #define IVOR4   0x194   /* Interrupt Vector Offset Register 4 */
 112 #define IVOR5   0x195   /* Interrupt Vector Offset Register 5 */
 113 #define IVOR6   0x196   /* Interrupt Vector Offset Register 6 */
 114 #define IVOR7   0x197   /* Interrupt Vector Offset Register 7 */
 115 #define IVOR8   0x198   /* Interrupt Vector Offset Register 8 */
 116 #define IVOR9   0x199   /* Interrupt Vector Offset Register 9 */
 117 #define IVOR10  0x19A   /* Interrupt Vector Offset Register 10 */
 118 #define IVOR11  0x19B   /* Interrupt Vector Offset Register 11 */
 119 #define IVOR12  0x19C   /* Interrupt Vector Offset Register 12 */
 120 #define IVOR13  0x19D   /* Interrupt Vector Offset Register 13 */
 121 #define IVOR14  0x19E   /* Interrupt Vector Offset Register 14 */
 122 #define IVOR15  0x19F   /* Interrupt Vector Offset Register 15 */
 123 #define MCSRR0  0x23A   /* Machine Check Save Restore Register 0 */
 124 #define MCSRR1  0x23B   /* Machine Check Save Restore Register 1 */
 125 #define MCSR    0x23C   /* Machine Check Status Register */
 126 #define INV0    0x370   /* Instruction Cache Normal Victim 0 */
 127 #define INV1    0x371   /* Instruction Cache Normal Victim 1 */
 128 #define INV2    0x372   /* Instruction Cache Normal Victim 2 */
 129 #define INV3    0x373   /* Instruction Cache Normal Victim 3 */
 130 #define ITV0    0x374   /* Instruction Cache Transient Victim 0 */
 131 #define ITV1    0x375   /* Instruction Cache Transient Victim 1 */
 132 #define ITV2    0x376   /* Instruction Cache Transient Victim 2 */
 133 #define ITV3    0x377   /* Instruction Cache Transient Victim 3 */
 134 #define CCR1    0x378   /* Core Configuration Register 1 */
 135 #define DNV0    0x390   /* Data Cache Normal Victim 0 */
 136 #define DNV1    0x391   /* Data Cache Normal Victim 1 */
 137 #define DNV2    0x392   /* Data Cache Normal Victim 2 */
 138 #define DNV3    0x393   /* Data Cache Normal Victim 3 */
 139 #define DTV0    0x394   /* Data Cache Transient Victim 0 */
 140 #define DTV1    0x395   /* Data Cache Transient Victim 1 */
 141 #define DTV2    0x396   /* Data Cache Transient Victim 2 */
 142 #define DTV3    0x397   /* Data Cache Transient Victim 3 */
 143 #define DVLIM   0x398   /* Data Cache Victim Limit */
 144 #define IVLIM   0x399   /* Instruction Cache Victim Limit */
 145 #define RSTCFG  0x39B   /* Reset Configuration */
 146 #define DCDBTRL 0x39C   /* Data Cache Debug Tag Register Low */
 147 #define DCDBTRH 0x39D   /* Data Cache Debug Tag Register High */
 148 #define ICDBTRL 0x39E   /* Instruction Cache Debug Tag Register Low */
 149 #define ICDBTRH 0x39F   /* Instruction Cache Debug Tag Register High */
 150 #define MMUCR   0x3B2   /* Memory Management Unit Control Register */
 151 #define CCR0    0x3B3   /* Core Configuration Register 0 */
 152 #define ICDBDR  0x3D3   /* Instruction Cache Debug Data Register */
 153 #define DBDR    0x3F3   /* Debug Data Register */
 154
 155 /* PVR register */
 156 #define PVR_PPC440EP_B     0x422218D3
 157 #define PVR_PPC440EP_C     0x422218D4
 158 #define PVR_PPC460EX_B     0x130218a4
 159
 160 /* TCR register */
 161 #define TCR_WP          0xc0000000
 162 #define TCR_WP21        0x00000000
 163 #define TCR_WP25        0x40000000
 164 #define TCR_WP29        0x80000000
 165 #define TCR_WP33        0xc0000000
 166 #define TCR_WRC         0x30000000
 167 #define TCR_WRC_NORESET 0x00000000
 168 #define TCR_WRC_CORE    0x10000000
 169 #define TCR_WRC_CHIP    0x20000000
 170 #define TCR_WRC_SYSTEM  0x30000000
 171 #define TCR_WIE         0x08000000
 172 #define TCR_DIE         0x04000000
 173 #define TCR_FP          0x03000000
 174 #define TCR_FP_13       0x00000000
 175 #define TCR_FP_17       0x01000000
 176 #define TCR_FP_21       0x02000000
 177 #define TCR_FP_25       0x03000000
 178 #define TCR_FIE         0x00800000
 179 #define TCR_ARE         0x00400000
 180
 181 /* TSR register */
 182 #define TSR_ENW         0x80000000
 183 #define TSR_WIS         0x40000000
 184 #define TSR_WRS         0x30000000
 185 #define TSR_WRS_NORESET 0x00000000
 186 #define TSR_WRS_CORE    0x10000000
 187 #define TSR_WRS_CHIP    0x20000000
 188 #define TSR_WRS_SYSTEM  0x30000000
 189 #define TSR_DIS         0x08000000
 190 #define TSR_FIS         0x04000000
 191
 192 /* DCR registers */
 193
 194 #define rddcr(reg) \
 195     ({ unsigned long val; asm volatile("mfdcr %0,%1":"=r"(val):"i"(reg)); val; })
 196
 197 #define wrdcr(reg, val) \
 198     do { asm volatile("mtdcr %0,%1"::"i"(reg),"r"(val)); } while(0)
 199
 200 /* System device control */
 201 #define CPR0_CFGADDR    0x000C  /* Clocking Configuration Address Register */
 202 #define CPR0_CFGDATA    0x000D  /* Clocking Configuration Data Register */
 203 #define CPR0_CLKUPD     0x0020  /* Clocking Update Register */
 204 #define CPR0_ICFG       0x0140  /* Clock/Power Configuration Register */
 205
 206 /* PPC440 specific registers */
 207 #define CPR0_PLLC0      0x0040  /* PLL Control Register */
 208 #define CPR0_PLLD0      0x0060  /* PLL Divisor Register */
 209 #define CPR0_PRIMAD0    0x0080  /* Primary A Divisor Register */
 210 #define CPR0_PRIMBD0    0x00A0  /* Primary B Divisor Register */
 211 #define CPR0_OPBD0      0x00C0  /* OPB Clock Divisor Register */
 212 #define CPR0_PERD0      0x00E0  /* Peripheral Clock Divisor Register */
 213 #define CPR0_MALD       0x0100  /* MAL Clock Divisor Register */
 214 #define CPR0_SPCID      0x0120  /* Sync PCI Clock Divisor Register */
 215
 216 /* PPC460 specific registers */
 217 #define CPR0_PLLC       0x0040  /* PLL Control Register */
 218 #define CPR0_PLLD       0x0060  /* PLL Divisor Register */
 219 #define CPR0_PLBED      0x0080  /* PLB Early Divisor Register */
 220 #define CPR0_PLB2D      0x00A0  /* PLB Divisor Register */
 221 #define CPR0_OPBD       0x00C0  /* OPB Clock Divisor Register */
 222 #define CPR0_PERD       0x00E0  /* Peripheral Clock Divisor Register */
 223 #define CPR0_AHBD       0x0100  /* AHB Clock Divisor Register */
 224
 225 #define SDR0_CFGADDR    0x000E  /* R/W System DCR Configuration Address Register */
 226 #define SDR0_CFGDATA    0x000F  /* R/W System DCR Configuration Data Register */
 227 #define SDR0_SDSTP0     0x0020  /*  R  Serial Device Strap Register 0 */
 228 #define SDR0_SDSTP1     0x0021  /*  R  Serial Device Strap Register 1 */
 229 #define SDR0_PINSTP     0x0040  /*  R  Pin Strapping Register */
 230 #define SDR0_SDCS0      0x0060  /* R/W Serial Device Controller Settings Register */
 231 #define SDR0_ECID0      0x0080  /* R/W Electronic Chip ID Register 0 */
 232 #define SDR0_ECID1      0x0081  /* R/W Electronic Chip ID Register 1 */
 233 #define SDR0_ECID2      0x0082  /* R/W Electronic Chip ID Register 2 */
 234 #define SDR0_ECID3      0x0083  /* R/W Electronic Chip ID Register 3 */
 235 #define SDR0_JTAG       0x00C0  /* R/W JTAG ID Register */
 236 #define SDR0_DDRDL0     0x00E0  /* R/W DDR Delay Line Register */
 237 #define SDR0_EBC0       0x0100  /* R/W EBC Configuration Register */
 238 #define SDR0_UART0      0x0120  /* R/W UART Configuration Register 0 */
 239 #define SDR0_UART1      0x0121  /* R/W UART Configuration Register 1 */
 240 #define SDR0_UART2      0x0122  /* R/W UART Configuration Register 2 */
 241 #define SDR0_UART3      0x0123  /* R/W UART Configuration Register 3 */
 242 #define SDR0_CP440      0x0180  /* R/W 440CPU Control Register */
 243 #define SDR0_SRST0      0x0200  /* R/W Individual Core Reset Control Register 0 */
 244 #define SDR0_SRST1      0x0201  /* R/W Individual Core Reset Control Register 1 */
 245 #define SDR0_SLPIPE0    0x0220  /* R/W PLB Slave Address Pipeline Disabling Register */
 246 #define SDR0_AMP0       0x0240  /* R/W Alternate PLB4 Master Priority Register */
 247 #define SDR0_AMP1       0x0241  /* R/W Alternate PLB3 Master Priority Register */
 248 #define SDR0_MIRQ0      0x0260  /* R/W Master Interrupt Request Register 0 (PLB3) */
 249 #define SDR0_MALTBL     0x0280  /* R/W MAL Transmit Burst Length Register */
 250 #define SDR0_MALRBL     0x02A0  /* R/W MAL Receive Burst Length Register */
 251 #define SDR0_MALTBS     0x02C0  /* R/W Reserved */
 252 #define SDR0_MALRBS     0x02E0  /* R/W Reserved */
 253 #define SDR0_PCI0       0x0300  /* R/W PCI Control Register */
 254 #define SDR0_USB0       0x0320  /*  R  Universal Serial Bus Register 0 */
 255 #define SDR0_CUST0      0x4000  /* R/W Register0 Reserved for Customer Use */
 256 #define SDR0_SDSTP2     0x4001  /*  R  Read Only Version of SDR0_CUST0 */
 257 #define SDR0_CUST1      0x4002  /* R/W Register1 Reserved for Customer Use */
 258 #define SDR0_SDSTP3     0x4003  /*  R  Read Only Version of SDR0_CUST1 */
 259 #define SDR0_PFC0       0x4100  /* R/W Pin Function Control Register 0 */
 260 #define SDR0_PFC1       0x4101  /* R/W Pin Function Control Register 1 */
 261 #define SDR0_MFR        0x4300  /* R/W Miscellaneous Function Register */
 262 #define SDR0_EMAC0RXST  0x4301  /* R/W EMAC0 RX Status Register */
 263 #define SDR0_EMAC0TXST  0x4302  /* R/W EMAC0 TX Status Register */
 264 #define SDR0_EMAC0REJCNT 0x4303 /*  R  EMAC0 RX Packet Reject Counter */
 265 #define SDR0_EMAC1RXST  0x4304  /* R/W EMAC1 RX Status Register */
 266 #define SDR0_EMAC1TXST  0x4305  /* R/W EMAC1 TX Status Register */
 267 #define SDR0_EMAC1REJCNT 0x4306 /*  R  EMAC1 RX Packet Reject Counter */
 268 #define SDR0_HSF        0x4400  /* R/W DDR Hardware Self Refresh Register */
 269
 270 #define SDR0_MFR_ZMII_MODE_MASK         0x30000000
 271
 272 #define SDR0_MFR_ZMII_MODE_MII          0x00000000
 273 #define SDR0_MFR_ZMII_MODE_SMII         0x10000000
 274 #define SDR0_MFR_ZMII_MODE_RMII_10M     0x20000000
 275 #define SDR0_MFR_ZMII_MODE_RMII_100M    0x30000000
 276
 277 /* 440EP DDR SDRAM Controller */
 278 #define SDRAM0_CFGADDR  0x0010  /* R/W DDR-SDRAM Address Register */
 279 #define SDRAM0_CFGDATA  0x0011  /* R/W DDR-SDRAM Data Register */
 280 #define SDRAM0_B0CR     0x0040  /* R/W DDR SDRAM Bank 0 Configuration */
 281 #define SDRAM0_B1CR     0x0044  /* R/W DDR SDRAM Bank 1 Configuration */
 282 #define SDRAM0_B2CR     0x0048  /* R/W DDR SDRAM Bank 2 Configuration */
 283 #define SDRAM0_B3CR     0x004C  /* R/W DDR SDRAM Bank 3 Configuration */
 284
 285 #define SDRAM_SDSZ_MASK  0x000E0000
 286 #define SDRAM_SDSZ_256MB 0x000C0000
 287 #define SDRAM_SDSZ_128MB 0x000A0000
 288 #define SDRAM_SDSZ_64MB  0x00080000
 289 #define SDRAM_SDSZ_32MB  0x00060000
 290 #define SDRAM_SDSZ_16MB  0x00040000
 291 #define SDRAM_SDSZ_8MB   0x00020000
 292
 293 /* 460EX DDR MQ Controller */
 294 #define MQ0_B0BAS       0x0040
 295 #define MQ0_B1BAS       0x0041
 296 #define MQ0_B2BAS       0x0042
 297 #define MQ0_B3BAS       0x0043
 298
 299 #define MQ0_BASSZ_MASK  0x0000FFC0
 300 #define MQ0_BASSZ_0MB    0x0000
 301 #define MQ0_BASSZ_8MB    0xFFC0
 302 #define MQ0_BASSZ_16MB   0xFF80
 303 #define MQ0_BASSZ_32MB   0xFF00
 304 #define MQ0_BASSZ_64MB   0xFE00
 305 #define MQ0_BASSZ_128MB  0xFC00
 306 #define MQ0_BASSZ_256MB  0xF800
 307 #define MQ0_BASSZ_512MB  0xF000
 308 #define MQ0_BASSZ_1024MB 0xE000
 309 #define MQ0_BASSZ_2048MB 0xC000
 310 #define MQ0_BASSZ_4096MB 0x8000
 311
 312 /* Universal Interrupt Controller 0 */
 313 #define UIC0_SR         0x00C0 /* R/Clear UIC 0 Status Register */
 314 #define UIC0_SRS        0x00C1 /* W/Set   UIC 0 Status Register Set (reserved for debug only) */
 315 #define UIC0_ER         0x00C2 /*  R/W    UIC 0 Enable Register */
 316 #define UIC0_CR         0x00C3 /*  R/W    UIC 0 Critical Register */
 317 #define UIC0_PR         0x00C4 /*  R/W    UIC 0 Polarity Register */
 318 #define UIC0_TR         0x00C5 /*  R/W    UIC 0 Triggering Register */
 319 #define UIC0_MSR        0x00C6 /*   R     UIC 0 Masked Status Register */
 320 #define UIC0_VR         0x00C7 /*   R     UIC 0 Vector Register */
 321 #define UIC0_VCR        0x00C8 /*   W     UIC 0 Vector Configuration Register */
 322
 323 /* Universal Interrupt Controller 1 */
 324 #define UIC1_SR         0x00D0 /* R/Clear UIC 1 Status Register */
 325 #define UIC1_SRS        0x00D1 /* W/Set   UIC 1 Status Register Set (reserved for debug only) */
 326 #define UIC1_ER         0x00D2 /*  R/W    UIC 1 Enable Register */
 327 #define UIC1_CR         0x00D3 /*  R/W    UIC 1 Critical Register */
 328 #define UIC1_PR         0x00D4 /*  R/W    UIC 1 Polarity Register */
 329 #define UIC1_TR         0x00D5 /*  R/W    UIC 1 Triggering Register */
 330 #define UIC1_MSR        0x00D6 /*   R     UIC 1 Masked Status Register */
 331 #define UIC1_VR         0x00D7 /*   R     UIC 1 Vector Register */
 332 #define UIC1_VCR        0x00D8 /*   W     UIC 1 Vector Configuration Register */
 333
 334 /* 460EX only */
 335
 336 /* Universal Interrupt Controller 2 */
 337 #define UIC2_SR         0x00E0 /* R/Clear UIC 2 Status Register */
 338 #define UIC2_SRS        0x00E1 /* W/Set   UIC 2 Status Register Set (reserved for debug only) */
 339 #define UIC2_ER         0x00E2 /*  R/W    UIC 2 Enable Register */
 340 #define UIC2_CR         0x00E3 /*  R/W    UIC 2 Critical Register */
 341 #define UIC2_PR         0x00E4 /*  R/W    UIC 2 Polarity Register */
 342 #define UIC2_TR         0x00E5 /*  R/W    UIC 2 Triggering Register */
 343 #define UIC2_MSR        0x00E6 /*   R     UIC 2 Masked Status Register */
 344 #define UIC2_VR         0x00E7 /*   R     UIC 2 Vector Register */
 345 #define UIC2_VCR        0x00E8 /*   W     UIC 2 Vector Configuration Register */
 346
 347 /* Universal Interrupt Controller 3 */
 348 #define UIC3_SR         0x00F0 /* R/Clear UIC 3 Status Register */
 349 #define UIC3_SRS        0x00F1 /* W/Set   UIC 3 Status Register Set (reserved for debug only) */
 350 #define UIC3_ER         0x00F2 /*  R/W    UIC 3 Enable Register */
 351 #define UIC3_CR         0x00F3 /*  R/W    UIC 3 Critical Register */
 352 #define UIC3_PR         0x00F4 /*  R/W    UIC 3 Polarity Register */
 353 #define UIC3_TR         0x00F5 /*  R/W    UIC 3 Triggering Register */
 354 #define UIC3_MSR        0x00F6 /*   R     UIC 3 Masked Status Register */
 355 #define UIC3_VR         0x00F7 /*   R     UIC 3 Vector Register */
 356 #define UIC3_VCR        0x00F8 /*   W     UIC 3 Vector Configuration Register */
 357
 358 /* External 440 interrupt sources */
 359 #define INTR_U0         0       /* UART0 Interrupt Status*/
 360 #define INTR_U1         1       /* UART1 Interrupt Status*/
 361 #define INTR_IIC0       2       /* IIC0 Interrupt Status*/
 362 #define INTR_U2         3       /* UART2 Interrupt Status*/
 363 #define INTR_U3         4       /* UART3 Interrupt Status*/
 364 #define INTR_PCRW       5       /* PCI Command Register Write Interrupt Status */
 365 #define INTR_PCIPM      6       /* PCI Power Management Interrupt Status */
 366 #define INTR_IIC1       7       /* IIC1 Interrupt Status */
 367 #define INTR_SPI        8       /* SPI Interrupt Status */
 368 #define INTR_EPS        9       /* Ext PCI SERR Interrupt Status */
 369 #define INTR_MTE        10      /* MAL TX EOB Interrupt Status */
 370 #define INTR_MRE        11      /* MAL RX EOB Interrupt Status */
 371 #define INTR_D0         12      /* DMA2P30 Channel 0 Interrupt Status */
 372 #define INTR_D1         13      /* DMA2P30 Channel 1 Interrupt Status */
 373 #define INTR_D2         14      /* DMA2P30 Channel 2 Interrupt Status */
 374 #define INTR_D3         15      /* DMA2P30 Channel 3 Interrupt Status */
 375 #define INTR_CT5        16      /* GPT Compare Timer 5 Interrupt Status */
 376 #define INTR_CT6        17      /* GPT Compare Timer 6 Interrupt Status */
 377 #define INTR_CT0        18      /* GPT Compare Timer 0 Interrupt Status */
 378 #define INTR_CT1        19      /* GPT Compare Timer 1 Interrupt Status */
 379 #define INTR_CT2        20      /* GPT Compare Timer 2 Interrupt Status */
 380 #define INTR_CT3        21      /* GPT Compare Timer 3 Interrupt Status */
 381 #define INTR_CT4        22      /* GPT Compare Timer 4 Interrupt Status */
 382 #define INTR_EIR0       23      /* External IRQ 0 Interrupt Status */
 383 #define INTR_EIR1       24      /* External IRQ 1 Interrupt Status */
 384 #define INTR_EIR2       25      /* External IRQ 2 Interrupt Status */
 385 #define INTR_EIR3       26      /* External IRQ 3 Interrupt Status */
 386 #define INTR_EIR4       27      /* External IRQ 4 Interrupt Status */
 387 #define INTR_EIR5       28      /* External IRQ 5 Interrupt Status */
 388 #define INTR_EIR6       29      /* External IRQ 6 Interrupt Status */
 389
 390 #define INTR_MS         32      /* MAL SERR Interrupt Status */
 391 #define INTR_MTDE       33      /* MAL TXDE Interrupt Status */
 392 #define INTR_MRDE       34      /* MAL RXDE Interrupt Status */
 393 #define INTR_DEUE       35      /* DDRSDRAM ECC Uncorrectable Error Interrupt Status */
 394 #define INTR_DECE       36      /* DDRSDRAM ECC Correctable Error Interrupt Status */
 395 #define INTR_EBC        37      /* EBC Interrupt Status */
 396 #define INTR_NDFC       38      /* NDFC Interrupt Status */
 397 #define INTR_OPB        39      /* OPB to PLB Bridge Interrupt Status */
 398 #define INTR_USB1H1     40      /* USB1.1 Host 1 Interrupt Status */
 399 #define INTR_USB1H2     41      /* USB1.1 Host 2 interrupt Status */
 400 #define INTR_P2P0       42      /* PLB3 to PLB4 Bridge 0 Interrupt Status */
 401 #define INTR_P2P1       43      /* PLB3 to PLB4 Bridge 1 Interrupt Status */
 402 #define INTR_P2P2       44      /* PLB3 to PLB4 Bridge 2 Interrupt Status */
 403 #define INTR_P2P3       45      /* PLB3 to PLB4 Bridge 3 Interrupt Status */
 404 #define INTR_P2P4       46      /* PLB3 to PLB4 Bridge 4 Interrupt Status */
 405 #define INTR_P2P5       47      /* PLB3 to PLB4 Bridge 5 Interrupt Status */
 406 #define INTR_UDMA0      48      /* UDMA0 Interrupt Status */
 407 #define INTR_UDMA1      49      /* UDMA1 Interrupt Status */
 408 #define INTR_EIR7       50      /* External IRQ 7 Interrupt Status */
 409 #define INTR_EIR8       51      /* External IRQ 8 Interrupt Status */
 410 #define INTR_EIR9       52      /* External IRQ 9 Interrupt Status */
 411 #define INTR_UDMA2      53      /* UDMA2 Interrupt Status */
 412 #define INTR_UDMA3      54      /* UDMA3 Interrupt Status */
 413 #define INTR_USBD       55      /* USB1.1 USB2.0 Device Interrupt Status */
 414 #define INTR_SRE        56      /* Serial ROM Error Interrupt Status */
 415 #define INTR_GDP        57      /* GPT Decrement Pulse Interrupt Status */
 416 #define INTR_PPM        58      /* PLB Performance Monitor Interrupt Status */
 417 #define INTR_EPP        59      /* EXT_PCI_PERR (parity) Interrupt Status */
 418 #define INTR_ETH0       60      /* Ethernet 0 Interrupt Status */
 419 #define INTR_EWU0       61      /* Ethernet 0 Wake-up Interrupt Status */
 420 #define INTR_ETH1       62      /* Ethernet 1 Interrupt Status */
 421 #define INTR_EWU1       63      /* Ethernet 1 Wake-up Interrupt Status */
 422
 423 /* 460ex Interrupts       [High/Low Polarity,Level Sensitivity]
 424  *  UIC0                  [   Rising/Falling,Edge Sensitivity ] */
 425 #define INTR_UIC0_BASE           0
 426 #define INTR_UIC0_CRITICAL       0x00104001
 427 #define INTR_UIC0_POLARITY       0xffffffff
 428 #define INTR_UIC0_TRIGGER        0x01800800
 429 #define INTR_UIC0_CASCADE        0x0030c003
 430 #define INTR_UIC0_UART1         (INTR_UIC0_BASE +  1)      // H L  UART1
 431 #define INTR_UIC0_IIC0          (INTR_UIC0_BASE +  2)      // H L
 432 #define INTR_UIC0_IIC1          (INTR_UIC0_BASE +  3)      // H L
 433 #define INTR_UIC0_PCI0_IN       (INTR_UIC0_BASE +  4)      // H L  PCI0 Inbound Message
 434 #define INTR_UIC0_PCI0_CWR      (INTR_UIC0_BASE +  5)      // H L  PCI0 Command Write Register
 435 #define INTR_UIC0_PCI0_PWR      (INTR_UIC0_BASE +  6)      // H L  PCI0 Power management
 436 #define INTR_UIC0_PCI0_VPD      (INTR_UIC0_BASE +  7)      // R E  PCI0 VPD Access
 437 #define INTR_UIC0_PCI0_MSI0     (INTR_UIC0_BASE +  8)      // R E  PCI0 MSI Level 0
 438 #define INTR_UIC0_EXT_IRQ0      (INTR_UIC0_BASE +  9)      // ? ?  External IRQ 0
 439 #define INTR_UIC0_UIC2_NC       (INTR_UIC0_BASE + 10)      // H L  UIC2 Cascade (Non-Critical)
 440 #define INTR_UIC0_UIC2_CR       (INTR_UIC0_BASE + 11)      // H L  UIC2 Cascade (Critical)
 441 #define INTR_UIC0_DMA2P40_CH0   (INTR_UIC0_BASE + 12)      // H L  DMA2P40 Channel 0
 442 #define INTR_UIC0_DMA2P40_CH1   (INTR_UIC0_BASE + 13)      // H L  DMA2P40 Channel 1
 443 #define INTR_UIC0_DMA2P40_CH2   (INTR_UIC0_BASE + 14)      // H L  DMA2P40 Channel 2
 444 #define INTR_UIC0_DMA2P40_CH3   (INTR_UIC0_BASE + 15)      // H L  DMA2P40 Channel 3
 445 #define INTR_UIC0_UIC3_NC       (INTR_UIC0_BASE + 16)      // H L  UIC3 Cascade (Non-Critical)
 446 #define INTR_UIC0_UIC3_CR       (INTR_UIC0_BASE + 17)      // H L  UIC3 Cascade (Critical)
 447 #define INTR_UIC0_EXT_IRQ1      (INTR_UIC0_BASE + 18)      // ? ?  External IRQ 1
 448 #define INTR_UIC0_TRNG_READY    (INTR_UIC0_BASE + 19)      // H L  TRNG ready
 449 #define INTR_UIC0_PKA           (INTR_UIC0_BASE + 20)      // R E  PKA Ready
 450 #define INTR_UIC0_HSDMA_FULL    (INTR_UIC0_BASE + 21)      // H L  HSDMA Command Pointer FIFO Full
 451 #define INTR_UIC0_HSDMA_STATUS  (INTR_UIC0_BASE + 22)      // H L  HSDMA Command Status FIFO
 452 #define INTR_UIC0_I2O_DOORBELL  (INTR_UIC0_BASE + 23)      // H L  I2O Inbound Doorbell
 453 #define INTR_UIC0_I2O_N_EMPTY   (INTR_UIC0_BASE + 24)      // H L  I2O Inbound FIFO Not Empty
 454 #define INTR_UIC0_I2O_LLW0      (INTR_UIC0_BASE + 25)      // H L  I2O Region 0 Low Latency PLB Write
 455 #define INTR_UIC0_I2O_LLW1      (INTR_UIC0_BASE + 26)      // H L  I2O Region 1 Low Latency PLB Write
 456 #define INTR_UIC0_I2O_HBW0      (INTR_UIC0_BASE + 27)      // H L  I2O Region 0 High Bandwidth PLB Write
 457 #define INTR_UIC0_I2O_HBW1      (INTR_UIC0_BASE + 28)      // H L  I2O Region 1 High Bandwidth PLB Write
 458 #define INTR_UIC0_EIP94         (INTR_UIC0_BASE + 29)      // H L  Security EIP-94
 459 #define INTR_UIC0_UIC1_NC       (INTR_UIC0_BASE + 30)      // H L  UIC1 Cascade (Non-Critical)
 460 #define INTR_UIC0_UIC1_CR       (INTR_UIC0_BASE + 31)      // H L  UIC1 Cascade (Critical)
 461
 462 /* 460ex Interrupts       [High/Low Polarity,Level Sensitivity]
 463  *  UIC1                  [   Rising/Falling,Edge Sensitivity ] */
 464 #define INTR_UIC1_BASE          32
 465 #define INTR_UIC1_CRITICAL       0x00000000
 466 #define INTR_UIC1_POLARITY       0xffffffff
 467 #define INTR_UIC1_TRIGGER        0x00fff000
 468 #define INTR_UIC1_EXT_IRQ2      (INTR_UIC1_BASE +  0)      // ? ?  External IRQ 2
 469 #define INTR_UIC1_UART0         (INTR_UIC1_BASE +  1)      // H L  Uart 0
 470 #define INTR_UIC1_SPI           (INTR_UIC1_BASE +  2)      // H L  SPI
 471 #define INTR_UIC1_TRNG_ALARM    (INTR_UIC1_BASE +  3)      // H L  TRNG Alarm
 472 #define INTR_UIC1_ECC           (INTR_UIC1_BASE +  4)      // H L
 473 #define INTR_UIC1_EBC           (INTR_UIC1_BASE +  5)      // H L
 474 #define INTR_UIC1_NDFC          (INTR_UIC1_BASE +  6)      // H L
 475 #define INTR_UIC1_EIPPKP_SLAVE  (INTR_UIC1_BASE +  7)      // H L
 476 #define INTR_UIC1_PCI0_MSI1     (INTR_UIC1_BASE +  8)      // R E  PCI MSI Level 1
 477 #define INTR_UIC1_PCI0_MSI2     (INTR_UIC1_BASE +  9)      // R E  PCI MSI Level 2
 478 #define INTR_UIC1_PCI0_MSI3     (INTR_UIC1_BASE + 10)      // R E  PCI MSI Level 3
 479 #define INTR_UIC1_L2            (INTR_UIC1_BASE + 11)      // R E
 480 #define INTR_UIC1_GPT_CMP0      (INTR_UIC1_BASE + 12)      // R E  GPT Compare Timer 0
 481 #define INTR_UIC1_GPT_CMP1      (INTR_UIC1_BASE + 13)      // R E  GPT Compare Timer 1
 482 #define INTR_UIC1_GPT_CMP2      (INTR_UIC1_BASE + 14)      // R E  GPT Compare Timer 2
 483 #define INTR_UIC1_GPT_CMP3      (INTR_UIC1_BASE + 15)      // R E  GPT Compare Timer 3
 484 #define INTR_UIC1_GPT_CMP4      (INTR_UIC1_BASE + 16)      // R E  GPT Compare Timer 4
 485 #define INTR_UIC1_GPT_CMP5      (INTR_UIC1_BASE + 17)      // R E  GPT Compare Timer 5
 486 #define INTR_UIC1_GPT_CMP6      (INTR_UIC1_BASE + 18)      // R E  GPT Compare Timer 6
 487 #define INTR_UIC1_GPT_DCT       (INTR_UIC1_BASE + 19)      // R E  GPT Down Count Timer
 488 #define INTR_UIC1_EXT_IRQ3      (INTR_UIC1_BASE + 20)      // ? ?
 489 #define INTR_UIC1_EXT_IRQ4      (INTR_UIC1_BASE + 21)      // ? ?
 490 #define INTR_UIC1_HSDMA_ERR     (INTR_UIC1_BASE + 22)      // H L
 491 #define INTR_UIC1_I2O_ERR       (INTR_UIC1_BASE + 23)      // H L
 492 #define INTR_UIC1_SROM_ERR      (INTR_UIC1_BASE + 24)      // H L
 493 #define INTR_UIC1_PCI0_ERROR    (INTR_UIC1_BASE + 25)      // H L
 494 #define INTR_UIC1_EXT_IRQ5      (INTR_UIC1_BASE + 26)      // ? ?
 495 #define INTR_UIC1_EXT_IRQ6      (INTR_UIC1_BASE + 27)      // ? ?
 496 #define INTR_UIC1_UART2         (INTR_UIC1_BASE + 28)      // H L
 497 #define INTR_UIC1_UART3         (INTR_UIC1_BASE + 29)      // H L
 498 #define INTR_UIC1_EXT_IRQ7      (INTR_UIC1_BASE + 30)      // ? ?
 499 #define INTR_UIC1_EXT_IRQ8      (INTR_UIC1_BASE + 31)      // ? ?
 500
 501 /* 460ex Interrupts       [High/Low Polarity,Level Sensitivity]
 502  *  UIC2                  [   Rising/Falling,Edge Sensitivity ] */
 503 #define INTR_UIC2_BASE          64
 504 #define INTR_UIC2_CRITICAL       0x00000000
 505 #define INTR_UIC2_POLARITY       0xffffffff
 506 #define INTR_UIC2_TRIGGER        0x00ff0000
 507 #define INTR_UIC2_TAHOE0        (INTR_UIC2_BASE +  0)      // H L
 508 #define INTR_UIC2_TAHOE1        (INTR_UIC2_BASE +  1)      // H L
 509 #define INTR_UIC2_EXT_IRQ9      (INTR_UIC2_BASE +  2)      // ? ?
 510 #define INTR_UIC2_MAL_SERR      (INTR_UIC2_BASE +  3)      // H L
 511 #define INTR_UIC2_MAL_TXDE      (INTR_UIC2_BASE +  4)      // H L
 512 #define INTR_UIC2_MAL_RXDE      (INTR_UIC2_BASE +  5)      // H L
 513 #define INTR_UIC2_MAL_TX_EOB    (INTR_UIC2_BASE +  6)      // H L
 514 #define INTR_UIC2_MAL_RX_EOB    (INTR_UIC2_BASE +  7)      // H L
 515 #define INTR_UIC2_MAL_TX0       (INTR_UIC2_BASE +  8)      // R E
 516 #define INTR_UIC2_MAL_TX1       (INTR_UIC2_BASE +  9)      // R E
 517 #define INTR_UIC2_MAL_TX2       (INTR_UIC2_BASE + 10)      // R E
 518 #define INTR_UIC2_MAL_TX3       (INTR_UIC2_BASE + 11)      // R E
 519 #define INTR_UIC2_MAL_RX0       (INTR_UIC2_BASE + 12)      // R E
 520 #define INTR_UIC2_MAL_RX1       (INTR_UIC2_BASE + 13)      // R E
 521 #define INTR_UIC2_MAL_RX2       (INTR_UIC2_BASE + 14)      // R E
 522 #define INTR_UIC2_MAL_RX3       (INTR_UIC2_BASE + 15)      // R E
 523 #define INTR_UIC2_EMAC0         (INTR_UIC2_BASE + 16)      // H L
 524 #define INTR_UIC2_EMAC1         (INTR_UIC2_BASE + 17)      // H L
 525 #define INTR_UIC2_EMAC2         (INTR_UIC2_BASE + 18)      // H L
 526 #define INTR_UIC2_EMAC3         (INTR_UIC2_BASE + 19)      // H L
 527 #define INTR_UIC2_EMAC0_WAKE    (INTR_UIC2_BASE + 20)      // H L
 528 #define INTR_UIC2_EMAC1_WAKE    (INTR_UIC2_BASE + 21)      // H L
 529 #define INTR_UIC2_EMAC2_WAKE    (INTR_UIC2_BASE + 22)      // H L
 530 #define INTR_UIC2_EMAC3_WAKE    (INTR_UIC2_BASE + 23)      // H L
 531 #define INTR_UIC2_EXT_IRQ10     (INTR_UIC2_BASE + 24)      // H L
 532 #define INTR_UIC2_EXT_IRQ11     (INTR_UIC2_BASE + 25)      // ? ?
 533 /* UIC1, IRQ port (INTR_UIC2_BASE + 26) is reserved */
 534 #define INTR_UIC2_AHBARB_ERR    (INTR_UIC2_BASE + 27)      // H L
 535 #define INTR_UIC2_USB_OTG       (INTR_UIC2_BASE + 28)      // H L
 536 #define INTR_UIC2_USB_EHCI      (INTR_UIC2_BASE + 29)      // H L
 537 #define INTR_UIC2_USB_OHCI      (INTR_UIC2_BASE + 30)      // H L
 538 #define INTR_UIC2_USB_OHCI_SMI  (INTR_UIC2_BASE + 31)      // H L
 539
 540 /* 460ex Interrupts       [High/Low Polarity,Level Sensitivity]
 541  *  UIC3                  [   Rising/Falling,Edge Sensitivity ] */
 542 #define INTR_UIC3_BASE          96
 543 #define INTR_UIC3_CRITICAL       0x00000000
 544 #define INTR_UIC3_POLARITY       0xf7dfffff
 545 #define INTR_UIC3_TRIGGER        0x69a000ff
 546 #define INTR_UIC3_PE0_AL        (INTR_UIC3_BASE +  0)      // H L  PCIE0 (if SATA is disabled)
 547 #define INTR_UIC3_SATA          (INTR_UIC3_BASE +  0)      // H L  SATA (if PCIE0 is disabled)
 548 #define INTR_UIC3_PE0_VPD       (INTR_UIC3_BASE +  1)      // R E
 549 #define INTR_UIC3_PE0_HOTPLUG   (INTR_UIC3_BASE +  2)      // R E
 550 #define INTR_UIC3_PE0_TCR       (INTR_UIC3_BASE +  3)      // H L
 551 #define INTR_UIC3_PE0_VCO       (INTR_UIC3_BASE +  4)      // F E
 552 #define INTR_UIC3_PE0_DCR       (INTR_UIC3_BASE +  5)      // H L
 553 #define INTR_UIC3_PE1_AL        (INTR_UIC3_BASE +  6)      // H L
 554 #define INTR_UIC3_PE1_VPD       (INTR_UIC3_BASE +  7)      // R E
 555 #define INTR_UIC3_PE1_HOTPLUG   (INTR_UIC3_BASE +  8)      // R E
 556 #define INTR_UIC3_PE1_TCR       (INTR_UIC3_BASE +  9)      // H L
 557 #define INTR_UIC3_PE1_VCO       (INTR_UIC3_BASE + 10)      // F E
 558 #define INTR_UIC3_PE1_DCR       (INTR_UIC3_BASE + 11)      // H L
 559 #define INTR_UIC3_PE0_INTA      (INTR_UIC3_BASE + 12)      // H L
 560 #define INTR_UIC3_PE0_INTB      (INTR_UIC3_BASE + 13)      // H L
 561 #define INTR_UIC3_PE0_INTC      (INTR_UIC3_BASE + 14)      // H L
 562 #define INTR_UIC3_PE0_INTD      (INTR_UIC3_BASE + 15)      // H L
 563 #define INTR_UIC3_PE1_INTA      (INTR_UIC3_BASE + 16)      // H L
 564 #define INTR_UIC3_PE1_INTB      (INTR_UIC3_BASE + 17)      // H L
 565 #define INTR_UIC3_PE1_INTC      (INTR_UIC3_BASE + 18)      // H L
 566 #define INTR_UIC3_PE1_INTD      (INTR_UIC3_BASE + 19)      // H L
 567 #define INTR_UIC3_EXT_IRQ12     (INTR_UIC3_BASE + 20)      // ? ?
 568 #define INTR_UIC3_EXT_IRQ13     (INTR_UIC3_BASE + 21)      // ? ?
 569 #define INTR_UIC3_EXT_IRQ14     (INTR_UIC3_BASE + 22)      // ? ?
 570 #define INTR_UIC3_EXT_IRQ15     (INTR_UIC3_BASE + 23)      // ? ?
 571 #define INTR_UIC3_PE_MSI0       (INTR_UIC3_BASE + 24)      // R E
 572 #define INTR_UIC3_PE_MSI1       (INTR_UIC3_BASE + 25)      // R E
 573 #define INTR_UIC3_PE_MSI2       (INTR_UIC3_BASE + 26)      // R E
 574 #define INTR_UIC3_PE_MSI3       (INTR_UIC3_BASE + 27)      // R E
 575 #define INTR_UIC3_PE_MSI4       (INTR_UIC3_BASE + 28)      // R E
 576 #define INTR_UIC3_PE_MSI5       (INTR_UIC3_BASE + 29)      // R E
 577 #define INTR_UIC3_PE_MSI6       (INTR_UIC3_BASE + 30)      // R E
 578 #define INTR_UIC3_PE_MSI7       (INTR_UIC3_BASE + 31)      // R E
 579
 580 /* UART registers */
 581
 582 #define IIC0_XTCNTLSS           0xEF60070F
 583 #define IIC0_DIRECTCNTL 0xEF600710
 584
 585 #define IIC1_XTCNTLSS           0xEF60080F
 586 #define IIC1_DIRECTCNTL 0xEF600810
 587
 588 #define IIC_XTCNTLSS_SRST               0x01
 589
 590 #define IIC_DIRECTCNTL_SDAC     0x08
 591 #define IIC_DIRECTCNTL_SCLC     0x04
 592 #define IIC_DIRECTCNTL_MSDA     0x02
 593 #define IIC_DIRECTCNTL_MSCL     0x01
 594
 595 /* UART0 */
 596 #define UART0_RBR       0xEF600300
 597 #define UART0_THR       0xEF600300
 598 #define UART0_IER       0xEF600301
 599 #define UART0_IIR       0xEF600302
 600 #define UART0_FCR       0xEF600302
 601 #define UART0_LCR       0xEF600303
 602 #define UART0_MCR       0xEF600304
 603 #define UART0_LSR       0xEF600305
 604 #define UART0_MSR       0xEF600306
 605 #define UART0_SCR       0xEF600307
 606 #define UART0_DLL       0xEF600300
 607 #define UART0_DLM       0xEF600301
 608
 609 /* UART1 */
 610 #define UART1_RBR       0xEF600400
 611 #define UART1_THR       0xEF600400
 612 #define UART1_IER       0xEF600401
 613 #define UART1_IIR       0xEF600402
 614 #define UART1_FCR       0xEF600402
 615 #define UART1_LCR       0xEF600403
 616 #define UART1_MCR       0xEF600404
 617 #define UART1_LSR       0xEF600405
 618 #define UART1_MSR       0xEF600406
 619 #define UART1_SCR       0xEF600407
 620 #define UART1_DLL       0xEF600400
 621 #define UART1_DLM       0xEF600401
 622
 623 /* UART2 */
 624 #define UART2_RBR       0xEF600500
 625 #define UART2_THR       0xEF600500
 626 #define UART2_IER       0xEF600501
 627 #define UART2_IIR       0xEF600502
 628 #define UART2_FCR       0xEF600502
 629 #define UART2_LCR       0xEF600503
 630 #define UART2_MCR       0xEF600504
 631 #define UART2_LSR       0xEF600505
 632 #define UART2_MSR       0xEF600506
 633 #define UART2_SCR       0xEF600507
 634 #define UART2_DLL       0xEF600500
 635 #define UART2_DLM       0xEF600501
 636
 637 /* UART3 */
 638 #define UART3_RBR       0xEF600600
 639 #define UART3_THR       0xEF600600
 640 #define UART3_IER       0xEF600601
 641 #define UART3_IIR       0xEF600602
 642 #define UART3_FCR       0xEF600602
 643 #define UART3_LCR       0xEF600603
 644 #define UART3_MCR       0xEF600604
 645 #define UART3_LSR       0xEF600605
 646 #define UART3_MSR       0xEF600606
 647 #define UART3_SCR       0xEF600607
 648 #define UART3_DLL       0xEF600600
 649 #define UART3_DLM       0xEF600601
 650
 651 #define UART_IER_EDSSI  0x08
 652 #define UART_IER_ELSI   0x04
 653 #define UART_IER_ETBEI  0x02
 654 #define UART_IER_ERBFI  0x01
 655
 656 #define UART_IIR_FE             0xc0
 657 #define UART_IIR_FE_ENABLED     0xc0
 658 #define UART_IIR_FE_DISABLED    0x00
 659 #define UART_IIR_INTID          0x0e
 660 #define UART_IIR_INTID_4        0x00
 661 #define UART_IIR_INTID_3        0x02
 662 #define UART_IIR_INTID_2        0x04
 663 #define UART_IIR_INITD_1        0x06
 664 #define UART_IIR_INTID_0        0x0c
 665 #define UART_IIR_INTP           0x01
 666
 667 #define UART_FCR_RFTL       0xc0
 668 #define UART_FCR_RFTL_01    0x00
 669 #define UART_FCR_RFTL_16    0x40
 670 #define UART_FCR_RFTL_32    0x80
 671 #define UART_FCR_RFTL_56    0xc0
 672 #define UART_FCR_DMS        0x08
 673 #define UART_FCR_TFR        0x04
 674 #define UART_FCR_RFR        0x02
 675 #define UART_FCR_FE         0x01
 676
 677 #define UART_LCR_DLAB       0x80
 678 #define UART_LCR_SB         0x40
 679 #define UART_LCR_SP         0x20
 680 #define UART_LCR_EPS        0x10
 681 #define UART_LCR_PEN        0x08
 682 #define UART_LCR_SBS        0x04
 683 #define UART_LCR_WLS        0x03
 684 #define UART_LCR_WLS_5      0x00
 685 #define UART_LCR_WLS_6      0x01
 686 #define UART_LCR_WLS_7      0x02
 687 #define UART_LCR_WLS_8      0x03
 688
 689 #define UART_MCR_AFC        0x20
 690 #define UART_MCR_LOOP       0x10
 691 #define UART_MCR_OUT2       0x08
 692 #define UART_MCR_OUT1       0x04
 693 #define UART_MCR_RTS        0x02
 694 #define UART_MCR_DTR        0x01
 695
 696 #define UART_LSR_RFE    0x80
 697 #define UART_LSR_TEMT   0x40
 698 #define UART_LSR_THRE   0x20
 699 #define UART_LSR_BI     0x10
 700 #define UART_LSR_FE     0x08
 701 #define UART_LSR_PE     0x04
 702 #define UART_LSR_OE     0x02
 703 #define UART_LSR_DR     0x01
 704
 705 #define UART_MSR_DCD    0x80
 706 #define UART_LSR_RI     0x40
 707 #define UART_LSR_DSR    0x20
 708 #define UART_LSR_CTS    0x10
 709 #define UART_LSR_DDCD   0x08
 710 #define UART_LSR_TERI   0x04
 711 #define UART_LSR_DDSR   0x02
 712 #define UART_LSR_DCTS   0x01
 713
 714 #define PCI0_IO        0xe8000000
 715 #define PCI0_IO_SIZE   0x04000000
 716 #define PCI0_MEM       0x80000000
 717 #define PCI0_MEM_SIZE  0x20000000
 718
 719 #define PCI0_CFGADDR   0xeec00000
 720 #define PCI0_CFGDATA   0xeec00004
 721
 722 #define PCI0_BAR0L     0xeec80010
 723 #define PCI0_BAR0H     0xeec80014
 724
 725 #define PCI0_POM0LAL   0xeec80068
 726 #define PCI0_POM0LAH   0xeec8006c
 727 #define PCI0_POM0SA    0xeec80070
 728 #define PCI0_POM0PCIAL 0xeec80074
 729 #define PCI0_POM0PCIAH 0xeec80078
 730
 731 #define PCI0_POM1LAL   0xeec8007c
 732 #define PCI0_POM1LAH   0xeec80080
 733 #define PCI0_POM1SA    0xeec80084
 734 #define PCI0_POM1PCIAL 0xeec80088
 735 #define PCI0_POM1PCIAH 0xeec8008c
 736
 737 #define PCI0_PIM0SAL   0xeec80098
 738 #define PCI0_PIM0SAH   0xeec800f8
 739 #define PCI0_PIM0LAL   0xeec8009c
 740 #define PCI0_PIM0LAH   0xeec800a0
 741
 742 #define GPT0_TBC        0xef600000
 743 #define GPT0_DCT0       0xef600110
 744 #define GPT0_DCIS       0xef60011c
 745 #define GPT0_DCIS_DCIS  0x80000000
 746
 747 /* ZMII interface */
 748 #define ZMII_FER        0xef600d00
 749 #define ZMII_SSR        0xef600d04
 750 #define ZMII_SMIISR     0xef600d08
 751
 752 #define ZMII_RMII       0x22000000
 753 #define ZMII_MDI0       0x80000000
 754
 755 #define ZMII_FER_DIS    0x0
 756 #define ZMII_FER_MDI    0x8
 757 #define ZMII_FER_SMII   0x4
 758 #define ZMII_FER_RMII   0x2
 759 #define ZMII_FER_MII    0x1
 760
 761 #define ZMII_FER_RSVD11         (0x00200000)
 762 #define ZMII_FER_RSVD10         (0x00100000)
 763 #define ZMII_FER_RSVD14_31      (0x0003FFFF)
 764
 765 #define ZMII_FER_V(__x)         (((3 - __x) * 4) + 16)
 766
 767 /* ZMII Speed Selection Register Bit Definitions */
 768 #define ZMII_SSR_SCI            (0x4)
 769 #define ZMII_SSR_FSS            (0x2)
 770 #define ZMII_SSR_SP             (0x1)
 771 #define ZMII_SSR_RSVD16_31      (0x0000FFFF)
 772
 773 #define ZMII_SSR_V(__x)         (((3 - __x) * 4) + 16)
 774
 775 /* ZMII SMII Status Register Bit Definitions */
 776 #define ZMII_SMIISR_E1          (0x80)
 777 #define ZMII_SMIISR_EC          (0x40)
 778 #define ZMII_SMIISR_EN          (0x20)
 779 #define ZMII_SMIISR_EJ          (0x10)
 780 #define ZMII_SMIISR_EL          (0x08)
 781 #define ZMII_SMIISR_ED          (0x04)
 782 #define ZMII_SMIISR_ES          (0x02)
 783 #define ZMII_SMIISR_EF          (0x01)
 784
 785 #define ZMII_SMIISR_V(__x)      ((3 - __x) * 8)
 786
 787 #define EMAC_M0                 (0)
 788 #define EMAC_M1                 (4)
 789 #define EMAC_TXM0               (8)
 790 #define EMAC_TXM1               (12)
 791 #define EMAC_RXM                (16)
 792 #define EMAC_ISR                (20)
 793 #define EMAC_IER                (24)
 794 #define EMAC_IAH                (28)
 795 #define EMAC_IAL                (32)
 796 #define EMAC_PAUSE_TIME_REG     (44)
 797 #define EMAC_I_FRAME_GAP_REG    (88)
 798 #define EMAC_STACR              (92)
 799 #define EMAC_TRTR               (96)
 800 #define EMAC_RX_HI_LO_WMARK     (100)
 801
 802 #define EMAC0_BASE               0xef600e00
 803 #define EMAC1_BASE               0xef600f00
 804
 805 /* bit definitions */
 806 /* MODE REG 0 */
 807 #define EMAC_M0_RXI             (0x80000000)
 808 #define EMAC_M0_TXI             (0x40000000)
 809 #define EMAC_M0_SRST            (0x20000000)
 810 #define EMAC_M0_TXE             (0x10000000)
 811 #define EMAC_M0_RXE             (0x08000000)
 812 #define EMAC_M0_WKE             (0x04000000)
 813
 814 #define EMAC_M1_FDE             0x80000000
 815 #define EMAC_M1_ILE             0x40000000
 816 #define EMAC_M1_VLE             0x20000000
 817 #define EMAC_M1_EIFC            0x10000000
 818 #define EMAC_M1_APP             0x08000000
 819 #define EMAC_M1_AEMI            0x02000000
 820 #define EMAC_M1_IST             0x01000000
 821 #define EMAC_M1_MF_1000MBPS     0x00800000      /* 0's for 10MBPS */
 822 #define EMAC_M1_MF_100MBPS      0x00400000
 823 #define EMAC_M1_RFS_4K          0x00300000      /* ~4k for 512 byte */
 824 #define EMAC_M1_RFS_2K          0x00200000
 825 #define EMAC_M1_RFS_1K          0x00100000
 826 #define EMAC_M1_TX_FIFO_2K      0x00080000      /* 0's for 512 byte */
 827 #define EMAC_M1_TX_FIFO_1K      0x00040000
 828 #define EMAC_M1_TR0_DEPEND      0x00010000      /* 0'x for single packet */
 829 #define EMAC_M1_TR0_MULTI       0x00008000
 830 #define EMAC_M1_TR1_DEPEND      0x00004000
 831 #define EMAC_M1_TR1_MULTI       0x00002000
 832 #define EMAC_M1_JUMBO_ENABLE    0x00001000
 833
 834 /* Transmit Mode Register 0 */
 835 #define EMAC_TXM0_GNP0          (0x80000000)
 836 #define EMAC_TXM0_GNP1          (0x40000000)
 837 #define EMAC_TXM0_GNPD          (0x20000000)
 838 #define EMAC_TXM0_FC            (0x10000000)
 839
 840 /* Receive Mode Register */
 841 #define EMAC_RMR_SP             (0x80000000)
 842 #define EMAC_RMR_SFCS           (0x40000000)
 843 #define EMAC_RMR_ARRP           (0x20000000)
 844 #define EMAC_RMR_ARP            (0x10000000)
 845 #define EMAC_RMR_AROP           (0x08000000)
 846 #define EMAC_RMR_ARPI           (0x04000000)
 847 #define EMAC_RMR_PPP            (0x02000000)
 848 #define EMAC_RMR_PME            (0x01000000)
 849 #define EMAC_RMR_PMME           (0x00800000)
 850 #define EMAC_RMR_IAE            (0x00400000)
 851 #define EMAC_RMR_MIAE           (0x00200000)
 852 #define EMAC_RMR_BAE            (0x00100000)
 853 #define EMAC_RMR_MAE            (0x00080000)
 854
 855 /* Interrupt Status & enable Regs */
 856 #define EMAC_ISR_OVR            (0x02000000)
 857 #define EMAC_ISR_PP             (0x01000000)
 858 #define EMAC_ISR_BP             (0x00800000)
 859 #define EMAC_ISR_RP             (0x00400000)
 860 #define EMAC_ISR_SE             (0x00200000)
 861 #define EMAC_ISR_SYE            (0x00100000)
 862 #define EMAC_ISR_BFCS           (0x00080000)
 863 #define EMAC_ISR_PTLE           (0x00040000)
 864 #define EMAC_ISR_ORE            (0x00020000)
 865 #define EMAC_ISR_IRE            (0x00010000)
 866 #define EMAC_ISR_DBDM           (0x00000200)
 867 #define EMAC_ISR_DB0            (0x00000100)
 868 #define EMAC_ISR_SE0            (0x00000080)
 869 #define EMAC_ISR_TE0            (0x00000040)
 870 #define EMAC_ISR_DB1            (0x00000020)
 871 #define EMAC_ISR_SE1            (0x00000010)
 872 #define EMAC_ISR_TE1            (0x00000008)
 873 #define EMAC_ISR_MOS            (0x00000002)
 874 #define EMAC_ISR_MOF            (0x00000001)
 875
 876 /* STA CONTROL REG */
 877 #define EMAC_STACR_OC           (0x00008000)
 878 #define EMAC_STACR_PHYE         (0x00004000)
 879 #define EMAC_STACR_WRITE        (0x00002000)
 880 #define EMAC_STACR_READ         (0x00001000)
 881 #define EMAC_STACR_CLK_83MHZ    (0x00000800)  /* 0's for 50Mhz */
 882 #define EMAC_STACR_CLK_66MHZ    (0x00000400)
 883 #define EMAC_STACR_CLK_100MHZ   (0x00000C00)
 884
 885 #define EMAC_STACR_OC_MASK      (0x00000000)
 886
 887 /* Transmit Request Threshold Register */
 888 #define EMAC_TRTR_256           (0x18000000)   /* 0's for 64 Bytes */
 889 #define EMAC_TRTR_192           (0x10000000)
 890 #define EMAC_TRTR_128           (0x01000000)
 891
 892 /* the follwing defines are for the MadMAL status and control registers. */
 893 #define EMAC_TX_CTRL_GFCS       (0x0200)
 894 #define EMAC_TX_CTRL_GP         (0x0100)
 895 #define EMAC_TX_CTRL_ISA        (0x0080)
 896 #define EMAC_TX_CTRL_RSA        (0x0040)
 897 #define EMAC_TX_CTRL_IVT        (0x0020)
 898 #define EMAC_TX_CTRL_RVT        (0x0010)
 899
 900 #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
 901
 902 #define EMAC_TX_ST_BFCS         (0x0200)
 903 #define EMAC_TX_ST_BPP          (0x0100)
 904 #define EMAC_TX_ST_LCS          (0x0080)
 905 #define EMAC_TX_ST_ED           (0x0040)
 906 #define EMAC_TX_ST_EC           (0x0020)
 907 #define EMAC_TX_ST_LC           (0x0010)
 908 #define EMAC_TX_ST_MC           (0x0008)
 909 #define EMAC_TX_ST_SC           (0x0004)
 910 #define EMAC_TX_ST_UR           (0x0002)
 911 #define EMAC_TX_ST_SQE          (0x0001)
 912
 913 #define EMAC_TX_ST_DEFAULT      (0x03F3)
 914
 915 /* madmal receive status / Control bits */
 916
 917 #define EMAC_RX_ST_OE           (0x0200)
 918 #define EMAC_RX_ST_PP           (0x0100)
 919 #define EMAC_RX_ST_BP           (0x0080)
 920 #define EMAC_RX_ST_RP           (0x0040)
 921 #define EMAC_RX_ST_SE           (0x0020)
 922 #define EMAC_RX_ST_AE           (0x0010)
 923 #define EMAC_RX_ST_BFCS         (0x0008)
 924 #define EMAC_RX_ST_PTL          (0x0004)
 925 #define EMAC_RX_ST_ORE          (0x0002)
 926 #define EMAC_RX_ST_IRE          (0x0001)
 927 /* all the errors we care about */
 928 #define EMAC_RX_ERRORS          (0x03FF)
 929
 930 /* AMCC460 USB */
 931 #define OHCI0_HCREV             (0xef000000)    /* 0x4 bffd0000 */
 932 #define EHCI0_HCCAPBASE         (0xef000400)    /* 0x4 bffd0400 */
 933
 934 /* AMCC460 IDE/SATA */
 935 #define SATA0_CDR0              (0xef001000)    /* 0x4 bffd1000 */
 936 #define SATA0_SCR0              (0xef001024)    /* 0x4 bffd1024 */
 937 #define SATA0_SCR2              (0xef00102c)    /* 0x4 bffd102c */
 938
 939 #endif /*ASM_AMCC440_H*/