arch/ppc-chrp/exec/preparecontext.c

   1 /*
   2     Copyright © 1995-2014, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <exec/types.h>
   7 #include <exec/execbase.h>
   8 #include <exec/memory.h>
   9 #include <utility/tagitem.h>
  10 #include <asm/mpc5200b.h>
  11 #include <proto/kernel.h>
  12
  13 #include "exec_intern.h"
  14 #include "exec_util.h"
  15
  16 #define DEBUG 0
  17
  18 #include <aros/libcall.h>
  19 #include <aros/debug.h>
  20
  21 BOOL PrepareContext(struct Task *task, APTR entryPoint, APTR fallBack,
  22                     const struct TagItem *tagList, struct ExecBase *SysBase)
  23 {
  24     context_t   *ctx;
  25     int         i;
  26     IPTR        *sp=(IPTR *)((IPTR)task->tc_SPReg & 0xfffffff0);
  27     IPTR        args[8] = {0};
  28     WORD        numargs = 0;
  29
  30     while(tagList)
  31     {
  32         switch(tagList->ti_Tag)
  33         {
  34             case TAG_MORE:
  35                 tagList = (const struct TagItem *)tagList->ti_Data;
  36                 continue;
  37
  38             case TAG_SKIP:
  39                 tagList += tagList->ti_Data;
  40                 break;
  41
  42             case TAG_DONE:
  43                 tagList = NULL;
  44                 break;
  45
  46             #define HANDLEARG(x) \
  47             case TASKTAG_ARG ## x: \
  48                 args[x - 1] = (IPTR)tagList->ti_Data; \
  49                 if (x > numargs) numargs = x; \
  50                 break;
  51
  52             HANDLEARG(1)
  53             HANDLEARG(2)
  54             HANDLEARG(3)
  55             HANDLEARG(4)
  56             HANDLEARG(5)
  57             HANDLEARG(6)
  58             HANDLEARG(7)
  59             HANDLEARG(8)
  60
  61             #undef HANDLEARG
  62             }
  63
  64         if (tagList) tagList++;
  65     }
  66
  67     if (!(task->tc_Flags & TF_ETASK) )
  68         return FALSE;
  69
  70     /* Get the memory for CPU context. Alloc it with MEMF_CLEAR flag */
  71     task->tc_UnionETask.tc_ETask->et_RegFrame = KrnCreateContext();
  72
  73     D(bug("[exec] PrepareContext: et_RegFrame = %012p\n", task->tc_UnionETask.tc_ETask->et_RegFrame));
  74
  75     if (!(ctx = (context_t *)task->tc_UnionETask.tc_ETask->et_RegFrame))
  76         return FALSE;
  77
  78     SuperState();
  79     if (numargs)
  80     {
  81         switch (numargs)
  82         {
  83             case 8:
  84                 ctx->cpu.gpr[10] = args[7];
  85             case 7:
  86                 ctx->cpu.gpr[9] = args[6];
  87             case 6:
  88                 ctx->cpu.gpr[8] = args[5];
  89             case 5:
  90                 ctx->cpu.gpr[7] = args[4];
  91             case 4:
  92                 ctx->cpu.gpr[6] = args[3];
  93             case 3:
  94                 ctx->cpu.gpr[5] = args[2];
  95             case 2:
  96                 ctx->cpu.gpr[4] = args[1];
  97             case 1:
  98                 ctx->cpu.gpr[3] = args[0];
  99                 break;
 100         }
 101     }
 102
 103     /* Push fallBack address */
 104     ctx->cpu.lr = fallBack;
 105     /*
 106      * Task will be started upon interrupt resume. Push entrypoint into SRR0
 107      * and the MSR register into SRR1. Enable FPU at the beginning
 108      */
 109     ctx->cpu.srr0 = (IPTR)entryPoint;
 110     ctx->cpu.srr1 = MSR_PR | MSR_EE | MSR_ME | MSR_IS | MSR_DS;
 111     ctx->cpu.srr1 |= MSR_FP;
 112     ctx->cpu.gpr[1] = sp;
 113
 114     task->tc_SPReg = sp;
 115
 116     sp[0] = 0;
 117     sp[1] = 0;
 118
 119     D(bug("[exec] New context:\n[exec] SRR0=%08x, SRR1=%08x\n",ctx->cpu.srr0, ctx->cpu.srr1));
 120     D(bug("[exec] GPR00=%08x GPR01=%08x GPR02=%08x GPR03=%08x\n",
 121              ctx->cpu.gpr[0],ctx->cpu.gpr[1],ctx->cpu.gpr[2],ctx->cpu.gpr[3]));
 122     D(bug("[exec] GPR04=%08x GPR05=%08x GPR06=%08x GPR07=%08x\n",
 123              ctx->cpu.gpr[4],ctx->cpu.gpr[5],ctx->cpu.gpr[6],ctx->cpu.gpr[7]));
 124     D(bug("[exec] GPR08=%08x GPR09=%08x GPR10=%08x GPR11=%08x\n",
 125              ctx->cpu.gpr[8],ctx->cpu.gpr[9],ctx->cpu.gpr[10],ctx->cpu.gpr[11]));
 126     D(bug("[exec] GPR12=%08x GPR13=%08x GPR14=%08x GPR15=%08x\n",
 127              ctx->cpu.gpr[12],ctx->cpu.gpr[13],ctx->cpu.gpr[14],ctx->cpu.gpr[15]));
 128
 129     D(bug("[exec] GPR16=%08x GPR17=%08x GPR18=%08x GPR19=%08x\n",
 130              ctx->cpu.gpr[16],ctx->cpu.gpr[17],ctx->cpu.gpr[18],ctx->cpu.gpr[19]));
 131     D(bug("[exec] GPR20=%08x GPR21=%08x GPR22=%08x GPR23=%08x\n",
 132              ctx->cpu.gpr[20],ctx->cpu.gpr[21],ctx->cpu.gpr[22],ctx->cpu.gpr[23]));
 133     D(bug("[exec] GPR24=%08x GPR25=%08x GPR26=%08x GPR27=%08x\n",
 134              ctx->cpu.gpr[24],ctx->cpu.gpr[25],ctx->cpu.gpr[26],ctx->cpu.gpr[27]));
 135     D(bug("[exec] GPR28=%08x GPR29=%08x GPR30=%08x GPR31=%08x\n",
 136              ctx->cpu.gpr[28],ctx->cpu.gpr[29],ctx->cpu.gpr[30],ctx->cpu.gpr[31]));
 137
 138     UserState(NULL);
 139
 140     return TRUE;
 141 }