workbench/hidds/vmwaresvga/vmwaresvga_hardware.c

   1 /*
   2     Copyright © 1995-2019, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: vmware svga hardware functions
   6     Lang: English
   7 */
   8
   9 #ifdef DEBUG
  10 #undef DEBUG
  11 #endif
  12 #define DEBUG 0 /* no SysBase */
  13 #include <aros/debug.h>
  14
  15 #include <asm/io.h>
  16
  17 #include <limits.h>
  18 #include <exec/ports.h>
  19 #include <devices/timer.h>
  20 #include <proto/exec.h>
  21
  22 #include "vmwaresvga_intern.h"
  23
  24 #if (DEBUG0)
  25 #define DIRQ(x)                         x
  26 #define DDMG(x)
  27 #define DFIFO(x)
  28 #define DFIFOINF(x)                     x
  29 #define DFIFOBUF(x)                     x
  30 #define DFENCE(x)                       x
  31 #define DREFRESH(x)
  32 #define DCURSOR(x)
  33 #else
  34 #define DIRQ(x)
  35 #define DDMG(x)
  36 #define DFIFO(x)
  37 #define DFIFOINF(x)
  38 #define DFIFOBUF(x)
  39 #define DFENCE(x)
  40 #define DREFRESH(x)
  41 #define DCURSOR(x)
  42 #endif
  43
  44 ULONG vmwareReadReg(struct HWData *data, ULONG reg)
  45 {
  46     outl(reg, data->indexReg);
  47     return inl(data->valueReg);
  48 }
  49
  50 VOID vmwareWriteReg(struct HWData *data, ULONG reg, ULONG val)
  51 {
  52     outl(reg, data->indexReg);
  53     outl(val, data->valueReg);
  54 }
  55
  56 VOID vmwareHandlerIRQ(struct HWData *data, void *unused)
  57 {
  58     UWORD port = (UWORD)((IPTR)data->iobase + SVGA_IRQSTATUS_PORT);
  59     ULONG irqFlags = inl(port);
  60     outl(irqFlags, port);
  61
  62     DIRQ(bug("[VMWareSVGA] %s(%08x)\n", __func__, irqFlags);)
  63     if (!irqFlags)
  64     {
  65         D(bug("[VMWareSVGA] %s: Spurrious IRQ!\n", __func__);)
  66     }
  67     else
  68     {
  69     }
  70 }
  71
  72
  73 #undef SysBase
  74 extern struct ExecBase *SysBase;
  75
  76
  77
  78 APTR VMWareSVGA_MemAlloc(struct HWData *data, ULONG size)
  79 {
  80     D(bug("[VMWareSVGA:HW] %s(%d)\n", __func__, size);)
  81     return AllocMem(size, MEMF_CLEAR|MEMF_31BIT);
  82 }
  83
  84 VOID VMWareSVGA_MemFree(struct HWData *data, APTR addr, ULONG size)
  85 {
  86     D(bug("[VMWareSVGA:HW] %s(0x%p)\n", __func__, addr);)
  87     FreeMem(addr, size);
  88 }
  89
  90
  91 /**********/
  92
  93 ULONG getVMWareSVGAID(struct HWData *data)
  94 {
  95     ULONG id;
  96
  97     D(bug("[VMWareSVGA:HW] %s()\n", __func__);)
  98
  99     vmwareWriteReg(data, SVGA_REG_ID, SVGA_ID_2);
 100     id = vmwareReadReg(data, SVGA_REG_ID);
 101     if (id == SVGA_ID_2)
 102         return id;
 103     vmwareWriteReg(data, SVGA_REG_ID, SVGA_ID_1);
 104     id = vmwareReadReg(data, SVGA_REG_ID);
 105     if (id == SVGA_ID_1)
 106         return id;
 107     if (id == SVGA_ID_0)
 108         return id;
 109     return SVGA_ID_INVALID;
 110 }
 111
 112 BOOL hasCapVMWareSVGAFIFO(struct HWData *data, ULONG fifocap)
 113 {
 114     volatile ULONG *fifo = data->mmiobase;
 115     if ((data->capabilities & SVGA_CAP_EXTENDED_FIFO) &&
 116         (fifo[SVGA_FIFO_MIN] > (fifocap << 2)))
 117     {
 118         return TRUE;
 119     }
 120     return FALSE;
 121 }
 122
 123 VOID initVMWareSVGAFIFO(struct HWData *data)
 124 {
 125     volatile ULONG *fifo = data->mmiobase;
 126
 127     DFIFOINF(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 128
 129     if (!data->fifomin)
 130     {
 131         if (data->capabilities & SVGA_CAP_EXTENDED_FIFO)
 132         {
 133             DFIFOINF(bug("[VMWareSVGA:HW] %s: Extended FIFO Capabilities\n", __func__);)
 134             data->fifomin = vmwareReadReg(data, SVGA_REG_MEM_REGS);
 135             data->fifocapabilities = fifo[SVGA_FIFO_CAPABILITIES];
 136             DFIFOINF(
 137               if (data->fifocapabilities & SVGA_FIFO_CAP_FENCE)
 138                   bug("[VMWareSVGA] %s:   Fence\n", __func__);
 139               if (data->fifocapabilities & SVGA_FIFO_CAP_ACCELFRONT)
 140                   bug("[VMWareSVGA] %s:   Accelerate Front\n", __func__);
 141               if (data->fifocapabilities & SVGA_FIFO_CAP_PITCHLOCK)
 142                   bug("[VMWareSVGA] %s:   Pitchlock\n", __func__);
 143               if (data->fifocapabilities & SVGA_FIFO_CAP_VIDEO)
 144                   bug("[VMWareSVGA] %s:   Video\n", __func__);
 145               if (data->fifocapabilities & SVGA_FIFO_CAP_CURSOR_BYPASS_3)
 146                   bug("[VMWareSVGA] %s:   Cursor-Bypass3\n", __func__);
 147               if (data->fifocapabilities & SVGA_FIFO_CAP_ESCAPE)
 148                   bug("[VMWareSVGA] %s:   Escape\n", __func__);
 149               if (data->fifocapabilities & SVGA_FIFO_CAP_RESERVE)
 150                   bug("[VMWareSVGA] %s:   FIFO Reserve\n", __func__);
 151               if (data->fifocapabilities & SVGA_FIFO_CAP_SCREEN_OBJECT)
 152                   bug("[VMWareSVGA] %s:   Screen-Object\n", __func__);
 153               if (data->fifocapabilities & SVGA_FIFO_CAP_GMR2)
 154                   bug("[VMWareSVGA] %s:   GMR2\n", __func__);
 155               if (data->fifocapabilities & SVGA_FIFO_CAP_3D_HWVERSION_REVISED)
 156                   bug("[VMWareSVGA] %s:   3DHWVersion-Revised\n", __func__);
 157               if (data->fifocapabilities & SVGA_FIFO_CAP_SCREEN_OBJECT_2)
 158                   bug("[VMWareSVGA] %s:   Screen-Object2\n", __func__);
 159              )
 160         }
 161         else
 162             data->fifomin = SVGA_FIFO_CAPABILITIES;
 163     }
 164     DFIFOINF(bug("[VMWareSVGA:HW] %s: FIFO Min Regs = %d\n", __func__, data->fifomin));
 165
 166     data->mmiosize = vmwareReadReg(data, SVGA_REG_MEM_SIZE);
 167
 168     vmwareWriteReg(data, SVGA_REG_CONFIG_DONE, 0);              //Stop vmware from reading the fifo
 169
 170     fifo[SVGA_FIFO_MIN] = (data->fifomin << VMWFIFO_CMD_SIZESHIFT);
 171     fifo[SVGA_FIFO_MAX] = data->mmiosize;
 172     fifo[SVGA_FIFO_NEXT_CMD] = fifo[SVGA_FIFO_MIN];
 173     fifo[SVGA_FIFO_STOP] = fifo[SVGA_FIFO_MIN];
 174
 175     vmwareWriteReg(data, SVGA_REG_CONFIG_DONE, 1);
 176
 177     if (hasCapVMWareSVGAFIFO(data, SVGA_FIFO_GUEST_3D_HWVERSION))
 178     {
 179         DFIFOINF(bug("[VMWareSVGA:HW] %s: Setting GUEST_3D_HWVERSION = %d\n", __func__, SVGA3D_HWVERSION_CURRENT);)
 180         fifo[SVGA_FIFO_GUEST_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
 181     }
 182     data->fifocmdbuf.buffer = AllocMem(VMW_COMMAND_SIZE, MEMF_CLEAR|MEMF_ANY);
 183     bug("[VMWareSVGA:HW] %s: FIFO Cmd bounce-buffer @ 0x%p\n", __func__, data->fifocmdbuf.buffer);
 184     InitSemaphore((struct SignalSemaphore *)&data->fifocmdbuf.fifocmdsema);
 185 }
 186
 187 void waitVMWareSVGAFIFO(struct HWData *data)
 188 {
 189     bug("[VMWareSVGA:HW] %s()\n", __func__);
 190     if (hasCapVMWareSVGAFIFO(data, SVGA_FIFO_FENCE_GOAL) &&
 191        (data->capabilities & SVGA_CAP_IRQMASK)) {
 192 #if (0)
 193         /*
 194          * On hosts which support interrupts, we can sleep until the
 195          * FIFO_PROGRESS interrupt occurs. This is the most efficient
 196          * thing to do when the FIFO fills up.
 197          *
 198          * As with the IRQ-based SVGA_SyncToFence(), this will only work
 199          * on Workstation 6.5 virtual machines and later.
 200          */
 201
 202         vmwareWriteReg(data, SVGA_REG_IRQMASK, SVGA_IRQFLAG_FIFO_PROGRESS);
 203         // TODO: wait for the irq...
 204         vmwareWriteReg(data, SVGA_REG_IRQMASK, 0);
 205 #endif
 206     } else {
 207         /*
 208          * Fallback implementation: Perform one iteration of the
 209          * legacy-style sync. This synchronously processes FIFO commands
 210          * for an arbitrary amount of time, then returns control back to
 211          * the guest CPU.
 212          */
 213         syncVMWareSVGAFIFO(data);
 214         vmwareReadReg(data, SVGA_REG_BUSY);
 215    }
 216 }
 217
 218 APTR reserveVMWareSVGAFIFO(struct HWData *data, ULONG size)
 219 {
 220     volatile ULONG *fifo = data->mmiobase;
 221     ULONG max = fifo[SVGA_FIFO_MAX];
 222     ULONG min = fifo[SVGA_FIFO_MIN];
 223     ULONG cmdNext = fifo[SVGA_FIFO_NEXT_CMD];
 224     BOOL canreserve = FALSE;
 225
 226     DFIFOBUF(bug("[VMWareSVGA:HW] %s(%d)\n", __func__, size);)
 227
 228     if (data->fifocapabilities & SVGA_FIFO_CAP_RESERVE)
 229     {
 230         DFIFOBUF(bug("[VMWareSVGA:HW] %s: reserve supported\n", __func__);)
 231         canreserve = TRUE;
 232     }
 233
 234     if (size > VMW_COMMAND_SIZE || (size > (max - min))) {
 235         bug("[VMWareSVGA:HW] %s: FIFO command too large", __func__);
 236         return NULL;
 237     }
 238
 239     if (size % VMWFIFO_CMD_SIZE) {
 240         bug("[VMWareSVGA:HW] %s: size of %d not 32bit-aligned!!\n", __func__, size);
 241         return NULL;
 242     }
 243
 244     ObtainSemaphore((struct SignalSemaphore *)&data->fifocmdbuf.fifocmdsema);
 245     data->fifocmdbuf.reserved = size;
 246
 247     while (1) {
 248         ULONG stop = fifo[SVGA_FIFO_STOP];
 249         BOOL reserveInPlace = FALSE;
 250         BOOL needBounce = FALSE;
 251
 252         /*
 253          * Find a strategy for dealing with "size" of data:
 254          * - reserve in place, if there's room and the FIFO supports it
 255          * - reserve in bounce buffer, if there's room in FIFO but not
 256          *   contiguous or FIFO can't safely handle reservations
 257          * - otherwise, sync the FIFO and try again.
 258          */
 259
 260         if (cmdNext >= stop) {
 261             /* There is no valid FIFO data between cmdNext and max */
 262
 263             if (cmdNext + size < max ||
 264                 (cmdNext + size == max && stop > min)) {
 265                 /*
 266                  * Fastest path 1: There is already enough contiguous space
 267                  * between cmdNext and max (the end of the buffer).
 268                  *
 269                  * Note the edge case: If the "<" path succeeds, we can
 270                  * quickly return without performing any other tests. If
 271                  * we end up on the "==" path, we're writing exactly up to
 272                  * the top of the FIFO and we still need to make sure that
 273                  * there is at least one unused DWORD at the bottom, in
 274                  * order to be sure we don't fill the FIFO entirely.
 275                  *
 276                  * If the "==" test succeeds, but stop <= min (the FIFO
 277                  * would be completely full if we were to reserve this
 278                  * much space) we'll end up hitting the FIFOFull path below.
 279                  */
 280                 reserveInPlace = TRUE;
 281             } else if ((max - cmdNext) + (stop - min) <= size) {
 282                 /*
 283                  * We have to split the FIFO command into two pieces,
 284                  * but there still isn't enough total free space in
 285                  * the FIFO to store it.
 286                  *
 287                  * Note the "<=". We need to keep at least one DWORD
 288                  * of the FIFO free at all times, or we won't be able
 289                  * to tell the difference between full and empty.
 290                  */
 291                 waitVMWareSVGAFIFO(data);
 292             } else {
 293                 /*
 294                  * Data fits in FIFO but only if we split it.
 295                  * Need to bounce to guarantee contiguous buffer.
 296                  */
 297                 needBounce = TRUE;
 298             }
 299
 300         } else {
 301          /* There is FIFO data between cmdNext and max */
 302
 303             if (cmdNext + size < stop) {
 304                 /*
 305                  * Fastest path 2: There is already enough contiguous space
 306                  * between cmdNext and stop.
 307                  */
 308                 reserveInPlace = TRUE;
 309             } else {
 310                 /*
 311                  * There isn't enough room between cmdNext and stop.
 312                  * The FIFO is too full to accept this command.
 313                  */
 314                 waitVMWareSVGAFIFO(data);
 315             }
 316         }
 317
 318         /*
 319          * If we decided we can write directly to the FIFO, make sure
 320          * the VMX can safely support this.
 321          */
 322         if (reserveInPlace) {
 323             if (canreserve || size <= sizeof(ULONG)) {
 324                 data->bbused = FALSE;
 325                 if (canreserve) {
 326                     fifo[SVGA_FIFO_RESERVED] = size;
 327                 }
 328                 ReleaseSemaphore((struct SignalSemaphore *)&data->fifocmdbuf.fifocmdsema);
 329                 return cmdNext + (UBYTE *)fifo;
 330             } else {
 331                 /*
 332                  * Need to bounce because we can't trust the VMX to safely
 333                  * handle uncommitted data in FIFO.
 334                  */
 335                 needBounce = TRUE;
 336             }
 337         }
 338
 339         /*
 340          * If we reach here, either we found a full FIFO, called
 341          * waitVMWareSVGAFIFO to make more room, and want to try again, or we
 342          * decided to use a bounce buffer instead.
 343          */
 344         if (needBounce) {
 345             data->bbused = TRUE;
 346             ReleaseSemaphore((struct SignalSemaphore *)&data->fifocmdbuf.fifocmdsema);
 347             return data->fifocmdbuf.buffer;
 348         }
 349     } /* while (1) */
 350 }
 351
 352 VOID commitVMWareSVGAFIFO(struct HWData *data, ULONG size)
 353 {
 354     volatile ULONG *fifo = data->mmiobase;
 355     ULONG max = fifo[SVGA_FIFO_MAX];
 356     ULONG min = fifo[SVGA_FIFO_MIN];
 357     ULONG cmdNext = fifo[SVGA_FIFO_NEXT_CMD];
 358     BOOL canreserve = FALSE;
 359
 360     DFIFOBUF(bug("[VMWareSVGA:HW] %s(%d)\n", __func__, size);)
 361
 362     if (data->fifocapabilities & SVGA_FIFO_CAP_RESERVE)
 363     {
 364         DFIFOBUF(bug("[VMWareSVGA:HW] %s: reserve supported\n", __func__);)
 365         canreserve = TRUE;
 366     }
 367
 368     if (data->fifocmdbuf.reserved == 0) {
 369         bug("[VMWareSVGA:HW] %s: COMMIT called before RESERVE!!\n", __func__);
 370         return;
 371     }
 372
 373     ObtainSemaphore((struct SignalSemaphore *)&data->fifocmdbuf.fifocmdsema);
 374
 375     data->fifocmdbuf.used += data->fifocmdbuf.reserved;
 376     data->fifocmdbuf.reserved = 0;
 377
 378     if (data->bbused) {
 379         /*
 380         * Slow paths: copy out of a bounce buffer.
 381         */
 382         UBYTE *buffer = data->fifocmdbuf.buffer;
 383
 384         if (canreserve) {
 385             /*
 386              * Slow path: bulk copy out of a bounce buffer in two chunks.
 387              *
 388              * Note that the second chunk may be zero-length if the reserved
 389              * size was large enough to wrap around but the commit size was
 390              * small enough that everything fit contiguously into the FIFO.
 391              *
 392              * Note also that we didn't need to tell the FIFO about the
 393              * reservation in the bounce buffer, but we do need to tell it
 394              * about the data we're bouncing from there into the FIFO.
 395              */
 396             ULONG chunkSize;
 397             if (size > (max - cmdNext))
 398                 chunkSize = max - cmdNext;
 399             else
 400                 chunkSize = size;
 401             bug("[VMWareSVGA:HW] %s: chunk size %d, size %d\n", __func__, chunkSize, size);
 402             fifo[SVGA_FIFO_RESERVED] = size;
 403             memcpy(cmdNext + (UBYTE *) fifo, buffer, chunkSize);
 404             memcpy(min + (UBYTE *) fifo, buffer + chunkSize, size - chunkSize);
 405         } else {
 406             /*
 407              * Slowest path: copy one ULONG at a time, updating NEXT_CMD as
 408              * we go, so that we bound how much data the guest has written
 409              * and the host doesn't know to checkpoint.
 410              */
 411
 412             ULONG *dword = (ULONG *)buffer;
 413
 414             bug("[VMWareSVGA:HW] %s: copying %dbytes\n", __func__, size);
 415
 416             while (size > 0) {
 417                 fifo[cmdNext >> VMWFIFO_CMD_SIZESHIFT] = *dword++;
 418                 cmdNext += VMWFIFO_CMD_SIZE;
 419                 if (cmdNext == max) {
 420                     cmdNext = min;
 421                 }
 422                 fifo[SVGA_FIFO_NEXT_CMD] = cmdNext;
 423                 size -= VMWFIFO_CMD_SIZE;
 424             }
 425         }
 426     }
 427
 428     /*
 429      * Atomically update NEXT_CMD, if we didn't already
 430      */
 431     if (!data->bbused || canreserve) {
 432         cmdNext += size;
 433         if (cmdNext >= max) {
 434             cmdNext -= max - min;
 435         }
 436         fifo[SVGA_FIFO_NEXT_CMD] = cmdNext;
 437     }
 438
 439     /*
 440      * Clear the reservation in the FIFO.
 441      */
 442     if (canreserve) {
 443         fifo[SVGA_FIFO_RESERVED] = 0;
 444     }
 445     ReleaseSemaphore((struct SignalSemaphore *)&data->fifocmdbuf.fifocmdsema);
 446 }
 447
 448 VOID flushVMWareSVGAFIFO(struct HWData *data, ULONG *fence)
 449 {
 450     DFIFOBUF(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 451
 452     if (data->fifocmdbuf.reserved)
 453     {
 454         *fence = fenceVMWareSVGAFIFO(data);
 455         commitVMWareSVGAFIFO(data, data->fifocmdbuf.reserved);
 456     }
 457 }
 458
 459 ULONG fenceVMWareSVGAFIFO(struct HWData *data)
 460 {
 461     ULONG fence = 1;
 462
 463     if (hasCapVMWareSVGAFIFO(data, SVGA_FIFO_FENCE) && (data->fifocapabilities & SVGA_FIFO_CAP_FENCE))
 464     {
 465         fence = data->fence++;
 466         if (fence == 0) fence = 1;
 467
 468         DFENCE(bug("[VMWareSVGA:HW] %s: inserting fence #%d\n", __func__, fence);)
 469
 470         writeVMWareSVGAFIFO(data, SVGA_CMD_FENCE);
 471         writeVMWareSVGAFIFO(data, fence);
 472         syncVMWareSVGAFIFO(data);
 473     }
 474     return fence;
 475 }
 476
 477 VOID syncfenceVMWareSVGAFIFO(struct HWData *data, ULONG fence)
 478 {
 479     volatile ULONG *fifo;
 480
 481     if (hasCapVMWareSVGAFIFO(data, SVGA_FIFO_FENCE) && (data->fifocapabilities & SVGA_FIFO_CAP_FENCE))
 482     {
 483         fifo = data->mmiobase;
 484         if ((LONG)(fifo[SVGA_FIFO_FENCE] - fence) < 0)
 485         {
 486             DFENCE(bug("[VMWareSVGA:HW] %s: fence #%d hasnt been reached yet...\n", __func__, fence);)
 487
 488         }
 489     }
 490 }
 491
 492 VOID syncVMWareSVGAFIFO(struct HWData *data)
 493 {
 494     DFIFO(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 495
 496     vmwareWriteReg(data, SVGA_REG_SYNC, 1);
 497 }
 498
 499 VOID writeVMWareSVGAFIFO(struct HWData *data, ULONG val)
 500 {
 501     volatile ULONG *fifo;
 502
 503     DFIFO(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 504
 505     fifo = data->mmiobase;
 506     if (
 507             (fifo[SVGA_FIFO_NEXT_CMD] + VMWFIFO_CMD_SIZE == fifo[SVGA_FIFO_STOP]) ||
 508             (
 509                 (fifo[SVGA_FIFO_NEXT_CMD] == (fifo[SVGA_FIFO_MAX] - VMWFIFO_CMD_SIZE)) &&
 510                 (fifo[SVGA_FIFO_STOP] == fifo[SVGA_FIFO_MIN])
 511             )
 512         )
 513         syncVMWareSVGAFIFO(data);
 514
 515     fifo[fifo[SVGA_FIFO_NEXT_CMD] >> VMWFIFO_CMD_SIZESHIFT] = val;
 516     fifo[SVGA_FIFO_NEXT_CMD] += VMWFIFO_CMD_SIZE;
 517
 518     if (fifo[SVGA_FIFO_NEXT_CMD] == fifo[SVGA_FIFO_MAX])
 519         fifo[SVGA_FIFO_NEXT_CMD] = fifo[SVGA_FIFO_MIN];
 520 }
 521
 522 BOOL initVMWareSVGAHW(struct HWData *data, OOP_Object *device)
 523 {
 524     ULONG id;
 525
 526     D(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 527
 528     id = getVMWareSVGAID(data);
 529     if (id == SVGA_ID_INVALID)
 530         return FALSE;
 531
 532     data->maskPool = CreatePool(MEMF_ANY, (32 << 3), (32 << 2));
 533
 534     if (id >= SVGA_ID_1)
 535     {
 536         volatile ULONG *fifo = data->mmiobase;
 537         data->capabilities = vmwareReadReg(data, SVGA_REG_CAPABILITIES);
 538     }
 539
 540     if (data->capabilities & SVGA_CAP_8BIT_EMULATION)
 541     {
 542         data->bitsperpixel = vmwareReadReg(data, SVGA_REG_HOST_BITS_PER_PIXEL);
 543         vmwareWriteReg(data,SVGA_REG_BITS_PER_PIXEL, data->bitsperpixel);
 544     }
 545     data->bitsperpixel = vmwareReadReg(data, SVGA_REG_BITS_PER_PIXEL);
 546
 547     data->depth = vmwareReadReg(data, SVGA_REG_DEPTH);
 548     data->maxwidth = vmwareReadReg(data, SVGA_REG_MAX_WIDTH);
 549     data->maxheight = vmwareReadReg(data, SVGA_REG_MAX_HEIGHT);
 550     data->redmask = vmwareReadReg(data, SVGA_REG_RED_MASK);
 551     data->greenmask = vmwareReadReg(data, SVGA_REG_GREEN_MASK);
 552     data->bluemask = vmwareReadReg(data, SVGA_REG_BLUE_MASK);
 553     data->bytesperpixel = 1;
 554
 555     if (data->depth>16)
 556         data->bytesperpixel = 4;
 557     else if (data->depth>8)
 558         data->bytesperpixel = 2;
 559
 560     if (data->capabilities & SVGA_CAP_MULTIMON)
 561     {
 562         data->displaycount = vmwareReadReg(data, SVGA_REG_NUM_DISPLAYS);
 563     }
 564     else
 565     {
 566         data->displaycount = 1;
 567     }
 568
 569     data->vramsize = vmwareReadReg(data, SVGA_REG_VRAM_SIZE);
 570     data->vrambase = (APTR)(IPTR)vmwareReadReg(data, SVGA_REG_FB_START);
 571     data->pseudocolor = vmwareReadReg(data, SVGA_REG_PSEUDOCOLOR);
 572
 573     D(
 574       bug("[VMWareSVGA:HW] %s: VRAM at 0x%08x size %d\n", __func__, data->vrambase, data->vramsize);
 575       bug("[VMWareSVGA:HW] %s: no.displays: %d\n", __func__, data->displaycount);
 576       bug("[VMWareSVGA:HW] %s: depth: %d\n", __func__, data->depth);
 577       bug("[VMWareSVGA:HW] %s: bpp  : %d\n", __func__, data->bitsperpixel);
 578      )
 579
 580     VMWareSVGA_RestartRenderTask(data);
 581
 582     return TRUE;
 583 }
 584
 585 VOID getModeCfgVMWareSVGA(struct HWData *data)
 586 {
 587     D(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 588
 589     data->fboffset = vmwareReadReg(data, SVGA_REG_FB_OFFSET);
 590     data->bytesperline = vmwareReadReg(data, SVGA_REG_BYTES_PER_LINE);
 591     data->depth = vmwareReadReg(data, SVGA_REG_DEPTH);
 592     data->redmask = vmwareReadReg(data, SVGA_REG_RED_MASK);
 593     data->greenmask = vmwareReadReg(data, SVGA_REG_GREEN_MASK);
 594     data->bluemask = vmwareReadReg(data, SVGA_REG_BLUE_MASK);
 595     data->pseudocolor = vmwareReadReg(data, SVGA_REG_PSEUDOCOLOR);
 596
 597     data->display_width = vmwareReadReg(data, SVGA_REG_WIDTH);
 598     data->display_height = vmwareReadReg(data, SVGA_REG_HEIGHT);
 599     D(bug("[VMWareSVGA:HW] %s: %dx%d\n", __func__, data->display_width, data->display_height));
 600 }
 601
 602 VOID enableVMWareSVGA(struct HWData *data)
 603 {
 604     vmwareWriteReg(data, SVGA_REG_ENABLE, 1);
 605 }
 606
 607 VOID disableVMWareSVGA(struct HWData *data)
 608 {
 609     vmwareWriteReg(data, SVGA_REG_ENABLE, 0);
 610 }
 611
 612 VOID initDisplayVMWareSVGA(struct HWData *data)
 613 {
 614     enableVMWareSVGA(data);
 615     getModeCfgVMWareSVGA(data);
 616     initVMWareSVGAFIFO(data);
 617 }
 618
 619 VOID setModeVMWareSVGA(struct HWData *data, ULONG width, ULONG height)
 620 {
 621     D(bug("[VMWareSVGA:HW] %s(%dx%d)\n", __func__, width, height));
 622
 623     disableVMWareSVGA(data);
 624
 625     vmwareWriteReg(data, SVGA_REG_WIDTH, width);
 626     vmwareWriteReg(data, SVGA_REG_HEIGHT, height);
 627
 628     if (data->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 629     {
 630         D(bug("[VMWareSVGA:HW] %s: Adjusting Display Topology\n", __func__);)
 631
 632         vmwareWriteReg(data, SVGA_REG_DISPLAY_ID, 0);
 633         vmwareWriteReg(data, SVGA_REG_DISPLAY_IS_PRIMARY, TRUE);
 634
 635         vmwareWriteReg(data, SVGA_REG_DISPLAY_POSITION_X, 0);
 636         vmwareWriteReg(data, SVGA_REG_DISPLAY_POSITION_Y, 0);
 637         vmwareWriteReg(data, SVGA_REG_DISPLAY_WIDTH, width);
 638         vmwareWriteReg(data, SVGA_REG_DISPLAY_HEIGHT, height);
 639     }
 640
 641     if (data->capabilities & SVGA_CAP_8BIT_EMULATION)
 642         vmwareWriteReg(data, SVGA_REG_BITS_PER_PIXEL, data->bitsperpixel);
 643
 644     initDisplayVMWareSVGA(data);
 645 }
 646
 647 VOID refreshAreaVMWareSVGA(struct HWData *data, struct Box *box)
 648 {
 649     DREFRESH(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 650
 651     writeVMWareSVGAFIFO(data, SVGA_CMD_UPDATE);
 652     writeVMWareSVGAFIFO(data, box->x1);
 653     writeVMWareSVGAFIFO(data, box->y1);
 654     writeVMWareSVGAFIFO(data, box->x2-box->x1+1);
 655     writeVMWareSVGAFIFO(data, box->y2-box->y1+1);
 656 }
 657
 658 VOID rectFillVMWareSVGA(struct HWData *data, ULONG color, LONG x, LONG y, LONG width, LONG height)
 659 {
 660     D(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 661
 662     writeVMWareSVGAFIFO(data, SVGA_CMD_RECT_FILL);
 663     writeVMWareSVGAFIFO(data, color);
 664     writeVMWareSVGAFIFO(data, x);
 665     writeVMWareSVGAFIFO(data, y);
 666     writeVMWareSVGAFIFO(data, width);
 667     writeVMWareSVGAFIFO(data, height);
 668     syncVMWareSVGAFIFO(data);
 669 }
 670
 671 VOID ropFillVMWareSVGA(struct HWData *data, ULONG color, LONG x, LONG y, LONG width, LONG height, ULONG mode)
 672 {
 673     D(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 674
 675     writeVMWareSVGAFIFO(data, SVGA_CMD_RECT_ROP_FILL);
 676     writeVMWareSVGAFIFO(data, color);
 677     writeVMWareSVGAFIFO(data, x);
 678     writeVMWareSVGAFIFO(data, y);
 679     writeVMWareSVGAFIFO(data, width);
 680     writeVMWareSVGAFIFO(data, height);
 681     writeVMWareSVGAFIFO(data, mode);
 682     syncVMWareSVGAFIFO(data);
 683 }
 684
 685 VOID ropCopyVMWareSVGA(struct HWData *data, LONG sx, LONG sy, LONG dx, LONG dy, ULONG width, ULONG height, ULONG mode)
 686 {
 687     D(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 688
 689     writeVMWareSVGAFIFO(data, SVGA_CMD_RECT_ROP_COPY);
 690     writeVMWareSVGAFIFO(data, sx);
 691     writeVMWareSVGAFIFO(data, sy);
 692     writeVMWareSVGAFIFO(data, dx);
 693     writeVMWareSVGAFIFO(data, dy);
 694     writeVMWareSVGAFIFO(data, width);
 695     writeVMWareSVGAFIFO(data, height);
 696     writeVMWareSVGAFIFO(data, mode);
 697     syncVMWareSVGAFIFO(data);
 698 }
 699
 700 VOID defineCursorVMWareSVGA(struct HWData *data, struct MouseData *mouse)
 701 {
 702     ULONG size = mouse->width * mouse->height;
 703     ULONG *xorMask, *xorBuffer;
 704     ULONG *image = mouse->shape;
 705     int i;
 706
 707     DCURSOR(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 708
 709     xorMask = (ULONG *)AllocVecPooled(data->maskPool, size << 2);
 710     if (xorMask)
 711     {
 712         DCURSOR(bug("[VMWareSVGA:HW] %s: xormask @ 0x%p\n", __func__, xorMask);)
 713         xorBuffer = xorMask;
 714         for (i = 0; i < size; i++)
 715         {
 716             ULONG pixel = *image ++;
 717             *xorBuffer = pixel;
 718             xorBuffer++;
 719         }
 720
 721         if (data->capabilities & SVGA_CAP_ALPHA_CURSOR)
 722         {
 723             DCURSOR(bug("[VMWareSVGA:HW] %s: rendering Alpha Cursor\n", __func__);)
 724             writeVMWareSVGAFIFO(data, SVGA_CMD_DEFINE_ALPHA_CURSOR);
 725             writeVMWareSVGAFIFO(data, VMWCURSOR_ID); // id
 726             writeVMWareSVGAFIFO(data, 0); // hotspot x
 727             writeVMWareSVGAFIFO(data, 0); // hotspot y
 728             writeVMWareSVGAFIFO(data, mouse->width); // width
 729             writeVMWareSVGAFIFO(data, mouse->height); // height
 730
 731             xorBuffer = xorMask;
 732             for (i = 0; i < size; i++)
 733             {
 734                 writeVMWareSVGAFIFO(data, *xorBuffer++);
 735             }
 736
 737             syncVMWareSVGAFIFO(data);
 738         }
 739         else
 740         {
 741 #if (0)
 742             xandBuffer = (ULONG *)AllocVecPooled(data->maskPool, size << 2);
 743             if (xandBuffer)
 744             {
 745                 DCURSOR(bug("[VMWareSVGA:HW] %s: rendering masked Cursor\n", __func__);)
 746                 writeVMWareSVGAFIFO(data, SVGA_CMD_DEFINE_CURSOR);
 747                 writeVMWareSVGAFIFO(data, VMWCURSOR_ID); // id
 748                 writeVMWareSVGAFIFO(data, 0); // hotspot x
 749                 writeVMWareSVGAFIFO(data, 0); // hotspot y
 750                 writeVMWareSVGAFIFO(data, mouse->width); // width
 751                 writeVMWareSVGAFIFO(data, mouse->height); // height
 752
 753                 for (i = 0; i < size; i++)
 754                 {
 755                     writeVMWareSVGAFIFO(data, *xandBuffer++);
 756                 }
 757
 758                 xorBuffer = xorMask;
 759                 for (i = 0; i < size; i++)
 760                 {
 761                     writeVMWareSVGAFIFO(data, *xorBuffer++);
 762                 }
 763
 764                 syncVMWareSVGAFIFO(data);
 765                 FreeVecPooled(data->maskPool, xandBuffer);
 766             }
 767 #endif
 768         }
 769         FreeVecPooled(data->maskPool, xorMask);
 770     }
 771 }
 772
 773 VOID displayCursorVMWareSVGA(struct HWData *data, LONG mode)
 774 {
 775     volatile ULONG *fifo = data->mmiobase;
 776
 777     DCURSOR(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 778
 779     if (hasCapVMWareSVGAFIFO(data, SVGA_FIFO_CURSOR_COUNT) && (data->fifocapabilities & SVGA_FIFO_CAP_CURSOR_BYPASS_3))
 780     {
 781         ULONG count;
 782         fifo[SVGA_FIFO_CURSOR_ON] = mode;
 783         count = fifo[SVGA_FIFO_CURSOR_COUNT];
 784         fifo[SVGA_FIFO_CURSOR_COUNT] = ++count;
 785     }
 786     else
 787     {
 788         if (data->capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 789         {
 790             vmwareWriteReg(data, SVGA_REG_CURSOR_ID, VMWCURSOR_ID);
 791             vmwareWriteReg(data, SVGA_REG_CURSOR_ON, mode);
 792         }
 793         else
 794         {
 795             writeVMWareSVGAFIFO(data, SVGA_CMD_DISPLAY_CURSOR);
 796             writeVMWareSVGAFIFO(data, VMWCURSOR_ID);
 797             writeVMWareSVGAFIFO(data, mode);
 798             syncVMWareSVGAFIFO(data);
 799         }
 800     }
 801 }
 802
 803 VOID moveCursorVMWareSVGA(struct HWData *data, LONG x, LONG y)
 804 {
 805     volatile ULONG *fifo = data->mmiobase;
 806
 807     DCURSOR(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 808
 809     if (hasCapVMWareSVGAFIFO(data, SVGA_FIFO_CURSOR_COUNT) && (data->fifocapabilities & SVGA_FIFO_CAP_CURSOR_BYPASS_3))
 810     {
 811         ULONG count;
 812         fifo[SVGA_FIFO_CURSOR_ON] = SVGA_CURSOR_ON_SHOW;
 813         fifo[SVGA_FIFO_CURSOR_X] = x;
 814         fifo[SVGA_FIFO_CURSOR_Y] = y;
 815         count = fifo[SVGA_FIFO_CURSOR_COUNT];
 816         fifo[SVGA_FIFO_CURSOR_COUNT] = ++count;
 817     }
 818     else
 819     {
 820         if (data->capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 821         {
 822             vmwareWriteReg(data, SVGA_REG_CURSOR_ID, VMWCURSOR_ID);
 823             vmwareWriteReg(data, SVGA_REG_CURSOR_X, x);
 824             vmwareWriteReg(data, SVGA_REG_CURSOR_Y, y);
 825             vmwareWriteReg(data, SVGA_REG_CURSOR_ON, SVGA_CURSOR_ON_SHOW);
 826         }
 827         else
 828         {
 829             writeVMWareSVGAFIFO(data, SVGA_CMD_MOVE_CURSOR);
 830             writeVMWareSVGAFIFO(data, x);
 831             writeVMWareSVGAFIFO(data, y);
 832             syncVMWareSVGAFIFO(data);
 833         }
 834     }
 835 }
 836
 837 VOID VMWareSVGA_Damage_Reset(struct HWData *hwdata)
 838 {
 839     DDMG(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 840
 841     ObtainSemaphore(&hwdata->damage_control);
 842
 843     hwdata->delta_damage.x1 = INT_MAX;
 844     hwdata->delta_damage.y1 = INT_MAX;
 845     hwdata->delta_damage.x2 = INT_MIN;
 846     hwdata->delta_damage.y2 = INT_MIN;
 847
 848     ReleaseSemaphore(&hwdata->damage_control);
 849 }
 850
 851 VOID VMWareSVGA_Damage_DeltaAdd(struct HWData *hwdata, struct Box *box)
 852 {
 853     ULONG tmpval;
 854
 855     DDMG(bug("[VMWareSVGA:HW] %s()\n", __func__);)
 856
 857     if (box->x1 > box->x2)
 858     {
 859         tmpval = box->x2;
 860         box->x2 = box->x1;
 861         box->x1 = tmpval;
 862     }
 863     if (box->y1 > box->y2)
 864     {
 865         tmpval = box->y2;
 866         box->y2 = box->y1;
 867         box->y1 = tmpval;
 868     }
 869
 870     ObtainSemaphore(&hwdata->damage_control);
 871     if (box->x1 < hwdata->delta_damage.x1)
 872     {
 873         hwdata->delta_damage.x1 = box->x1;
 874     }
 875     if (box->y1 < hwdata->delta_damage.y1)
 876     {
 877         hwdata->delta_damage.y1 = box->y1;
 878     }
 879     if (box->x2 > hwdata->delta_damage.x2)
 880     {
 881         hwdata->delta_damage.x2 = box->x2;
 882     }
 883     if (box->y2 > hwdata->delta_damage.y2)
 884     {
 885         hwdata->delta_damage.y2 = box->y2;
 886     }
 887 #if defined(VMWAREGFX_IMMEDIATEDRAW)
 888     if (hwdata->shown)
 889     {
 890         refreshAreaVMWareSVGA(hwdata, &hwdata->delta_damage);
 891         VMWareSVGA_Damage_Reset(hwdata);
 892         syncVMWareSVGAFIFO(hwdata);
 893     }
 894 #endif
 895     ReleaseSemaphore(&hwdata->damage_control);
 896 }
 897
 898 #if !defined(VMWAREGFX_IMMEDIATEDRAW)
 899 VOID VMWareSVGA_RenderTask(struct HWData *hwdata)
 900 {
 901     struct MsgPort render_thread_message_port;
 902     struct timerequest *timer_request;
 903     struct IORequest *timer_request_as_io_request;
 904     ULONG request_size = sizeof(struct timerequest);
 905     BYTE running;
 906
 907     render_thread_message_port.mp_Flags = PA_SIGNAL;
 908     render_thread_message_port.mp_Node.ln_Type = NT_MSGPORT;
 909     render_thread_message_port.mp_MsgList.lh_TailPred = (struct Node *)&render_thread_message_port.mp_MsgList;
 910     render_thread_message_port.mp_MsgList.lh_Tail = 0;
 911     render_thread_message_port.mp_MsgList.lh_Head = (struct Node *)&render_thread_message_port.mp_MsgList.lh_Tail;
 912
 913     render_thread_message_port.mp_SigBit = AllocSignal(-1);
 914     render_thread_message_port.mp_SigTask = FindTask(0);
 915
 916     timer_request = AllocMem(request_size, MEMF_CLEAR | MEMF_PUBLIC);
 917     timer_request_as_io_request = (void *)timer_request;
 918
 919     timer_request_as_io_request->io_Message.mn_Node.ln_Type     = NT_MESSAGE;
 920     timer_request_as_io_request->io_Message.mn_ReplyPort                = &render_thread_message_port;
 921     timer_request_as_io_request->io_Message.mn_Length                   = request_size;
 922
 923     OpenDevice("timer.device", UNIT_MICROHZ, timer_request_as_io_request, 0);
 924
 925     timer_request->tr_node.io_Command = TR_ADDREQUEST;
 926     timer_request->tr_time.tv_secs = 0;
 927     timer_request->tr_time.tv_micro = 20000;
 928     SendIO(timer_request_as_io_request);
 929
 930     running = 1;
 931     while (running) // TODO: If you'll ever implement GFX Driver hot swap, you will want to unlock this condition and let the RenderTask terminate
 932     {
 933         if (!vmwareReadReg(hwdata, SVGA_REG_BUSY))
 934         {
 935             ObtainSemaphore(&hwdata->damage_control);
 936             struct Box *damage = &hwdata->delta_damage;
 937
 938             if ((damage->x2 > damage->x1) && (damage->y2 > damage->y1))
 939             {
 940                 refreshAreaVMWareSVGA(hwdata, &hwdata->delta_damage);
 941                 VMWareSVGA_Damage_Reset(hwdata);
 942                 syncVMWareSVGAFIFO(hwdata);
 943             }
 944             ReleaseSemaphore(&hwdata->damage_control);
 945         }
 946
 947         WaitIO(timer_request_as_io_request);
 948         GetMsg(&render_thread_message_port); // TODO: Did we have to reply to this? Oh memory ...
 949
 950         timer_request->tr_node.io_Command = TR_ADDREQUEST;
 951         timer_request->tr_time.tv_secs = 0;
 952         timer_request->tr_time.tv_micro = 20000; // TODO: This should be adaptive. We would need to know the CPU load and increase the delay to avoid burning all of the CPU time
 953         SendIO(timer_request_as_io_request);
 954     }
 955
 956     CloseDevice(timer_request_as_io_request);
 957 }
 958 #endif
 959
 960 VOID VMWareSVGA_RestartRenderTask(struct HWData *hwdata)
 961 {
 962     // TODO: CleanUp and add defenses here
 963
 964     InitSemaphore(&hwdata->damage_control);
 965 #if !defined(VMWAREGFX_IMMEDIATEDRAW)
 966     hwdata->render_task = NewCreateTask(TASKTAG_PC,
 967                                         VMWareSVGA_RenderTask,
 968                                         TASKTAG_NAME,   "VMWare Render Task",
 969                                         TASKTAG_PRI,    1,
 970                                         TASKTAG_ARG1,   hwdata,
 971                                         TAG_DONE);
 972 #endif
 973 }