rom/usb/classes/davicometh/dm9601eth.h

   1 #ifndef DM9601ETH_H
   2 #define DM9601ETH_H
   3
   4 #include <intuition/intuition.h>
   5 #include <intuition/intuitionbase.h>
   6 #include <libraries/mui.h>
   7 #include <libraries/gadtools.h>
   8 #include <devices/sana2.h>
   9 #include <devices/sana2specialstats.h>
  10 #include <exec/devices.h>
  11
  12 #if defined(__GNUC__)
  13 # pragma pack(2)
  14 #endif
  15
  16 #define DM_MAX_MCAST    64
  17 #define DM_MCAST_SIZE   8
  18 #define DM_EEPROM_LEN   256
  19 #define DM_TX_OVERHEAD  2       /* 2 byte header */
  20 #define DM_RX_OVERHEAD  7       /* 3 byte header + 4 byte crc tail */
  21
  22 #define DDF_CONFIGURED (1<<2)  /* station address is configured */
  23 #define DDF_ONLINE     (1<<3)  /* device is online */
  24 #define DDF_OFFLINE    (1<<4)  /* device was put offline */
  25
  26 #define DROPPED        (1<<0)  /* Did the packet get dropped? */
  27 #define PACKETFILTER   (1<<1)  /* Use the packet filter? */
  28
  29 /* Ethernet address bytesize
  30 */
  31 #define ETHER_ADDR_SIZE 6
  32
  33 #define ETHER_MIN_LEN  60           /* smallest amount that nic will accept */
  34 #define ETHER_MAX_LEN  1536         /* largest legal amount for Ethernet */
  35
  36 /* Ethernet packet data sizes (maximum)
  37 */
  38 #define ETHERPKT_SIZE  1500
  39 #define RAWPKT_SIZE    1514
  40
  41 #define PHY_BUSY                0x01
  42 #define PHY_WRITE               0x02
  43 #define PHY_READ                0x04
  44 #define PHY_PHYSEL              0x08
  45 #define PHY_WRITE_EEPROM        0x10
  46 #define PHY_RELOAD_EEPROM       0x20
  47
  48 #define RX_ENABLE               0x01
  49 #define RX_PROMISCUOUS          0x02
  50 #define RX_PASS_RUNT            0x04
  51 #define RX_ALL_MULTICAST        0x08
  52 #define RX_DISCARD_LONG         0x10
  53 #define RX_DISCARD_CRC          0x20
  54 #define RX_WATCHDOG_DISABLE     0x40
  55
  56 /* USB Control Pipe Commands */
  57 #define UDMR_GET_REGS           0x00
  58 #define UDMR_SET_REGS           0x01
  59 #define UDMR_READ_MEM           0x02
  60 #define UDMR_SET_REG            0x03
  61 #define UDMR_WRITE_MEM_MULTI    0x05
  62 #define UDMR_WRITE_MEM          0x07
  63
  64 /* registers */
  65 #define DMREG_NET_CTRL          0x00
  66 #define DMREG_NET_STATUS        0x01
  67 #define DMREG_TX_CTRL           0x02
  68 #define DMREG_TX_STATUS_1       0x03
  69 #define DMREG_TX_STATUS_2       0x04
  70 #define DMREG_RX_CTRL           0x05
  71 #define DMREG_RX_STATUS         0x06
  72 #define DMREG_RX_OVERFLOW       0x07
  73 #define DMREG_BACK_PRESSURE     0x08
  74 #define DMREG_FLOW_CTRL         0x09
  75 #define DMREG_RX_FLOW_CTRL      0x0a
  76 #define DMREG_PHY_CTRL          0x0b
  77 #define DMREG_PHY_ADDR          0x0c
  78 #define DMREG_PHY_DATA_LOW      0x0d
  79 #define DMREG_PHY_DATA_HIGH     0x0e
  80 #define DMREG_WAKEUP_CTRL       0x0f
  81 #define DMREG_ETH_ID            0x10    /* 6 bytes */
  82 #define DMREG_MCAST_ADDR        0x16    /* 8 bytes */
  83 #define DMREG_GPR_CTRL          0x1e
  84 #define DMREG_GPR_DATA          0x1f
  85
  86 /* PHY stuff */
  87
  88 /* Generic MII registers. */
  89
  90 #define MII_BMCR            0x00        /* Basic mode control register */
  91 #define MII_BMSR            0x01        /* Basic mode status register  */
  92 #define MII_PHYSID1         0x02        /* PHYS ID 1                   */
  93 #define MII_PHYSID2         0x03        /* PHYS ID 2                   */
  94 #define MII_ADVERTISE       0x04        /* Advertisement control reg   */
  95 #define MII_LPA             0x05        /* Link partner ability reg    */
  96 #define MII_EXPANSION       0x06        /* Expansion register          */
  97 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
  98 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
  99 #define MII_ESTATUS         0x0f        /* Extended Status */
 100 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 101 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 102 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
 103 #define MII_RERRCOUNTER     0x15        /* Receive error counter       */
 104 #define MII_SREVISION       0x16        /* Silicon revision            */
 105 #define MII_RESV1           0x17        /* Reserved...                 */
 106 #define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
 107 #define MII_PHYADDR         0x19        /* PHY address                 */
 108 #define MII_RESV2           0x1a        /* Reserved...                 */
 109 #define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
 110 #define MII_NCONFIG         0x1c        /* Network interface config    */
 111
 112 /* Basic mode control register. */
 113 #define BMCR_RESV               0x003f  /* Unused...                   */
 114 #define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
 115 #define BMCR_CTST               0x0080  /* Collision test              */
 116 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 117 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
 118 #define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
 119 #define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
 120 #define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
 121 #define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
 122 #define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
 123 #define BMCR_RESET              0x8000  /* Reset the DP83840           */
 124
 125 /* Basic mode status register. */
 126 #define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
 127 #define BMSR_JCD                0x0002  /* Jabber detected             */
 128 #define BMSR_LSTATUS            0x0004  /* Link status                 */
 129 #define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
 130 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 131 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 132 #define BMSR_RESV               0x00c0  /* Unused...                   */
 133 #define BMSR_ESTATEN            0x0100  /* Extended Status in R15 */
 134 #define BMSR_100FULL2           0x0200  /* Can do 100BASE-T2 HDX */
 135 #define BMSR_100HALF2           0x0400  /* Can do 100BASE-T2 FDX */
 136 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
 137 #define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
 138 #define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
 139 #define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
 140 #define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
 141
 142 #define BMSR_MEDIA (BMSR_10HALF|BMSR_10FULL|BMSR_100HALF|BMSR_100FULL|BMSR_ANEGCAPABLE)
 143
 144 /* Advertisement control register. */
 145 #define ADVERTISE_SLCT          0x001f  /* Selector bits               */
 146 #define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
 147 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
 148 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
 149 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
 150 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
 151 #define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
 152 #define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
 153 #define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
 154 #define ADVERTISE_RESV          0x1000  /* Unused...                   */
 155 #define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
 156 #define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
 157 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
 158
 159 #define ID_ABOUT        0x55555555
 160 #define ID_STORE_CONFIG 0xaaaaaaaa
 161 #define ID_DEF_CONFIG   0xaaaaaaab
 162
 163 #define MT_AUTO                 0x0000
 164 #define MT_10BASE_T_HALF_DUP    0x0001
 165 #define MT_10BASE_T_FULL_DUP    0x0002
 166 #define MT_100BASE_TX_HALF_DUP  0x0003
 167 #define MT_100BASE_TX_FULL_DUP  0x0004
 168
 169 struct ClsDevCfg
 170 {
 171     ULONG cdc_ChunkID;
 172     ULONG cdc_Length;
 173     ULONG cdc_DefaultUnit;
 174     ULONG cdc_MediaType;
 175 };
 176
 177 #if defined(__GNUC__)
 178 # pragma pack()
 179 #endif
 180
 181 /* Structure of an ethernet packet - internal
 182 */
 183
 184 struct EtherPacketHeader
 185 {
 186     UBYTE       eph_Dest[ETHER_ADDR_SIZE]; /* 0 destination address */
 187     UBYTE       eph_Src[ETHER_ADDR_SIZE]; /* 6 originator  address */
 188     UWORD       eph_Type;                 /* 12 packet type */
 189 };
 190
 191 /* Buffer management node - private
 192 */
 193 struct BufMan
 194 {
 195     struct Node bm_Node;
 196     APTR        bm_DMACopyFromBuf32;
 197     APTR        bm_CopyFromBuf;
 198     APTR        bm_DMACopyToBuf32;
 199     APTR        bm_CopyToBuf;
 200     APTR        bm_PacketFilter;
 201     struct List bm_RXQueue;               /* read requests */
 202 };
 203
 204 /* Multicast address range record - private
 205 */
 206 struct MulticastAddressRange
 207 {
 208     struct Node mar_Node;                 /* 0 list node */
 209     ULONG       mar_UseCount;             /* 8 number of times used */
 210     UBYTE       mar_LowerAddr[ETHER_ADDR_SIZE]; /* 12 multicast address lower bound */
 211     UBYTE       mar_UpperAddr[ETHER_ADDR_SIZE]; /* 18 multicast address upper bound */
 212 };
 213
 214 struct PacketTypeStats
 215 {
 216     struct Node pts_Node;
 217     ULONG       pts_PacketType;
 218     struct Sana2PacketTypeStats pts_Stats;
 219 };
 220
 221
 222 struct NepEthDevBase
 223 {
 224     struct Library      np_Library;       /* standard */
 225     UWORD               np_Flags;         /* various flags */
 226
 227     BPTR                np_SegList;       /* device seglist */
 228     struct NepEthBase  *np_ClsBase;       /* pointer to class base */
 229     struct Library     *np_UtilityBase;   /* cached utilitybase */
 230 };
 231
 232 struct NepClassEth
 233 {
 234     struct Unit         ncp_Unit;         /* Unit structure */
 235     ULONG               ncp_UnitNo;       /* Unit number */
 236     ULONG               ncp_OpenFlags;    /* Flags used to open the device */
 237     struct NepEthBase  *ncp_ClsBase;      /* Up linkage */
 238     struct NepEthDevBase *ncp_DevBase;    /* Device base */
 239     struct Library     *ncp_Base;         /* Poseidon base */
 240     struct PsdDevice   *ncp_Device;       /* Up linkage */
 241     struct PsdConfig   *ncp_Config;       /* Up linkage */
 242     struct PsdInterface *ncp_Interface;   /* Up linkage */
 243     struct Task        *ncp_ReadySigTask; /* Task to send ready signal to */
 244     LONG                ncp_ReadySignal;  /* Signal to send when ready */
 245     struct Task        *ncp_Task;         /* Subtask */
 246     struct MsgPort     *ncp_TaskMsgPort;  /* Message Port of Subtask */
 247
 248     struct PsdPipe     *ncp_EP0Pipe;      /* Endpoint 0 pipe */
 249     struct PsdEndpoint *ncp_EPOut;        /* Endpoint 1 */
 250     struct PsdPipe     *ncp_EPOutPipe[2]; /* Endpoint 1 pipes */
 251     IPTR                ncp_EPOutMaxPktSize; /* Endpoint 1 max pkt size */
 252     IPTR                ncp_EPOutNum;     /* Number of Out-Endpoint */
 253     struct PsdEndpoint *ncp_EPIn;         /* Endpoint 2 */
 254     struct PsdPipe     *ncp_EPInPipe;     /* Endpoint 2 pipe */
 255     IPTR                ncp_EPInNum;      /* Number of In-Endpoint */
 256     struct MsgPort     *ncp_DevMsgPort;   /* Message Port for IOParReq */
 257     UWORD               ncp_UnitProdID;   /* ProductID of unit */
 258     UWORD               ncp_UnitVendorID; /* VendorID of unit */
 259     //BOOL                ncp_DenyRequests; /* Do not accept further IO requests */
 260
 261     struct List         ncp_BufManList;   /* Buffer Managers */
 262     struct List         ncp_EventList;    /* List for DoEvent */
 263     struct List         ncp_TrackList;    /* List of trackables */
 264     struct List         ncp_Multicasts;   /* List of multicast addresses */
 265     UBYTE               ncp_MacAddress[ETHER_ADDR_SIZE]; /* Current Mac Address */
 266     UBYTE               ncp_ROMAddress[ETHER_ADDR_SIZE]; /* ROM Mac Address */
 267     UBYTE               ncp_MulticastArray[8]; /* array for the multicast hashes */
 268     ULONG               ncp_StateFlags;   /* State of the unit */
 269
 270     ULONG               ncp_Retries;      /* tx collision count */
 271     ULONG               ncp_BadMulticasts; /* bad multicast count */
 272
 273     UBYTE              *ncp_ReadBuffer[2]; /* Packet Double Buffered Read Buffer */
 274     UBYTE              *ncp_WriteBuffer[2]; /* Packet Write Buffer */
 275
 276     UWORD               ncp_ReadBufNum;   /* Next Read Buffer to use */
 277     UWORD               ncp_WriteBufNum;  /* Next Write Buffer to use */
 278
 279     struct Sana2DeviceStats ncp_DeviceStats; /* SANA Stats */
 280     struct Sana2PacketTypeStats *ncp_TypeStats2048; /* IP protocol stats ptr, or NULL */
 281     struct Sana2PacketTypeStats *ncp_TypeStats2054; /* ARP protocol stats ptr, or NULL */
 282
 283     UBYTE              *ncp_ReadPending;  /* read IORequest pending */
 284     struct IOSana2Req  *ncp_WritePending[2]; /* write IORequest pending */
 285     struct List         ncp_OrphanQueue;  /* List of orphan read requests */
 286     struct List         ncp_WriteQueue;   /* List of write requests */
 287
 288     UBYTE               ncp_DevIDString[128];  /* Device ID String */
 289
 290     BOOL                ncp_UsingDefaultCfg;
 291     struct ClsDevCfg   *ncp_CDC;
 292
 293     struct Library     *ncp_MUIBase;      /* MUI master base */
 294     struct Library     *ncp_PsdBase;      /* Poseidon base */
 295     struct Library     *ncp_IntBase;      /* Intuition base */
 296     struct Task        *ncp_GUITask;      /* GUI Task */
 297     struct NepClassHid *ncp_GUIBinding;   /* Window of binding that's open */
 298
 299     Object             *ncp_App;
 300     Object             *ncp_MainWindow;
 301
 302     Object             *ncp_UnitObj;
 303     Object             *ncp_MediaTypeObj;
 304
 305     Object             *ncp_UseObj;
 306     Object             *ncp_SetDefaultObj;
 307     Object             *ncp_CloseObj;
 308
 309     Object             *ncp_AboutMI;
 310     Object             *ncp_UseMI;
 311     Object             *ncp_SetDefaultMI;
 312     Object             *ncp_MUIPrefsMI;
 313
 314 };
 315
 316 struct NepEthBase
 317 {
 318     struct Library      nh_Library;       /* standard */
 319     UWORD               nh_Flags;         /* various flags */
 320
 321     struct Library     *nh_UtilityBase;   /* utility base */
 322
 323     struct NepEthDevBase *nh_DevBase;     /* base of device created */
 324     struct List         nh_Units;         /* List of units available */
 325
 326     struct NepClassEth  nh_DummyNCP;      /* Dummy ncp for default config */
 327 };
 328
 329
 330 #endif /* DM9601ETH_H */