rom/usb/pciusb/ohcichip.h

   1 #ifndef OHCICHIP_H
   2 #define OHCICHIP_H
   3
   4 /*
   5  *----------------------------------------------------------------------------
   6  *             Includes for OHCI USB Controller
   7  *----------------------------------------------------------------------------
   8  *                   By Chris Hodges <chrisly@platon42.de>
   9  */
  10
  11 #include <exec/types.h>
  12 #include "hccommon.h"
  13
  14 /* PCI Class: PCI_CLASS_SERIAL_USB */
  15
  16 /* Framelist stuff
  17
  18   - Framelist contains all the same entries pointing to ISO-TD
  19   - ISO-TD: is inactive by default. Links to Control-QH
  20   - Control-QH: - Head links to Int-Queue
  21                 - Element: Links to dummy-TD if empty (inactive)
  22                 - Element: otherwise links to QH for control transfer
  23   - Int-Queue : - Head links to Bulk-Queue
  24
  25
  26 */
  27
  28 /*
  29  * --------------------- OHCI registers ------------------------
  30  * Warning: These are BYTE offsets!
  31  */
  32
  33 /* operational registers */
  34 #define OHCI_REVISION       0x000 /* Host Controller Revision (r) */
  35 #define OHCI_CONTROL        0x004 /* Control register (r/w) */
  36 #define OHCI_CMDSTATUS      0x008 /* Command and Status */
  37 #define OHCI_INTSTATUS      0x00c /* Interrupt Status (r/wc) */
  38 #define OHCI_INTEN          0x010 /* Interrupt Enable (r/ws) */
  39 #define OHCI_INTDIS         0x014 /* Interrupt Disable (r/wc) */
  40 #define OHCI_HCCA           0x018 /* Pointer to HCCA */
  41 #define OHCI_PERIODIC_ED    0x01c /* Current periodic ED */
  42 #define OHCI_CTRL_HEAD_ED   0x020 /* Control Head ED */
  43 #define OHCI_CTRL_ED        0x024 /* Current control ED */
  44 #define OHCI_BULK_HEAD_ED   0x028 /* Bulk Head ED */
  45 #define OHCI_BULK_ED        0x02c /* Current bulk ED */
  46 #define OHCI_DONEHEAD       0x030 /* Done head pointer */
  47 #define OHCI_FRAMEINTERVAL  0x034 /* Frame interval */
  48 #define OHCI_FRAMEREMAINING 0x038 /* Frame remaining time */
  49 #define OHCI_FRAMECOUNT     0x03c /* Frame number */
  50 #define OHCI_PERIODICSTART  0x040 /* Periodic start (usually 10% of 12000 == 0x3e67) */
  51 #define OHCI_LSTHRESHOLD    0x044 /* Lowspeed threshold (usually 0x0628) */
  52 #define OHCI_HUBDESCA       0x048 /* Root Hub Descriptor A */
  53 #define OHCI_HUBDESCB       0x04c /* Root Hub Descriptor B */
  54 #define OHCI_HUBSTATUS      0x050 /* Root Hub Status */
  55 #define OHCI_PORTSTATUS     0x054 /* Port Status */
  56
  57 /* OHCI_CONTROL defines */
  58 #define OCLS_CBSR            0    /* Control Bulk Service Ratio */
  59 #define OCLB_PERIODICENABLE  2    /* Periodic Enable */
  60 #define OCLB_ISOENABLE       3    /* Isochronous Enable */
  61 #define OCLB_CTRLENABLE      4    /* Control List enable */
  62 #define OCLB_BULKENABLE      5    /* Bulk List enable */
  63 #define OCLS_USBSTATE        6    /* Host controller functional state */
  64 #define OCLB_SMIINT          8    /* SMI Interrupt routing */
  65 #define OCLB_REMOTEWAKEUP   10    /* Remote wakeup enabled */
  66
  67 #define OCLF_PERIODICENABLE (1UL<<OCLB_PERIODICENABLE)
  68 #define OCLF_ISOENABLE      (1UL<<OCLB_ISOENABLE)
  69 #define OCLF_CTRLENABLE     (1UL<<OCLB_CTRLENABLE)
  70 #define OCLF_BULKENABLE     (1UL<<OCLB_BULKENABLE)
  71 #define OCLF_SMIINT         (1UL<<OCLB_SMIINT)
  72 #define OCLF_REMOTEWAKEUP   (1UL<<OCLB_REMOTEWAKEUP)
  73
  74 #define OCLM_CBSR           (((1UL<<2)-1)<<OCLS_CBSR)
  75 #define OCLM_USBSTATE       (((1UL<<2)-1)<<OCLS_USBSTATE)
  76 #define OCLF_USBRESET       (0UL<<OCLS_USBSTATE)
  77 #define OCLF_USBRESUME      (1UL<<OCLS_USBSTATE)
  78 #define OCLF_USBOPER        (2UL<<OCLS_USBSTATE)
  79 #define OCLF_USBSUSPEND     (3UL<<OCLS_USBSTATE)
  80
  81 /* OHCI_CMDSTATUS defines */
  82 #define OCSB_HCRESET         0    /* Host controller reset */
  83 #define OCSB_CTRLENABLE      1    /* Enable Control List processing */
  84 #define OCSB_BULKENABLE      2    /* Enable Bulk List processing */
  85 #define OCSB_OWNERCHANGEREQ  3    /* Request change of ownership for BIOS handover */
  86
  87 #define OCSF_HCRESET        (1UL<<OCSB_HCRESET)
  88 #define OCSF_CTRLENABLE     (1UL<<OCSB_CTRLENABLE)
  89 #define OCSF_BULKENABLE     (1UL<<OCSB_BULKENABLE)
  90 #define OCSF_OWNERCHANGEREQ (1UL<<OCSB_OWNERCHANGEREQ)
  91
  92 /* OHCI_INTSTATUS, OHCI_INTEN and OHCI_INTDIS defines */
  93 #define OISB_SCHEDOVERRUN    0    /* Schedule overrun */
  94 #define OISB_DONEHEAD        1    /* Writeback done head */
  95 #define OISB_SOF             2    /* Start of Frame */
  96 #define OISB_RESUMEDTX       3    /* Resume detected */
  97 #define OISB_HOSTERROR       4    /* Unrecoverable error */
  98 #define OISB_FRAMECOUNTOVER  5    /* Frame counter overrun (15 bit) */
  99 #define OISB_HUBCHANGE       6    /* Root Hub status change */
 100 #define OISB_OWNERCHANGE    30    /* Ownership changed */
 101 #define OISB_MASTERENABLE   31    /* Master Interrupt enable (INTEN only) */
 102
 103 #define OISF_SCHEDOVERRUN   (1UL<<OISB_SCHEDOVERRUN)
 104 #define OISF_DONEHEAD       (1UL<<OISB_DONEHEAD)
 105 #define OISF_SOF            (1UL<<OISB_SOF)
 106 #define OISF_RESUMEDTX      (1UL<<OISB_RESUMEDTX)
 107 #define OISF_HOSTERROR      (1UL<<OISB_HOSTERROR)
 108 #define OISF_FRAMECOUNTOVER (1UL<<OISB_FRAMECOUNTOVER)
 109 #define OISF_HUBCHANGE      (1UL<<OISB_HUBCHANGE)
 110 #define OISF_OWNERCHANGE    (1UL<<OISB_OWNERCHANGE)
 111 #define OISF_MASTERENABLE   (1UL<<OISB_MASTERENABLE)
 112
 113 #define OISF_ALL_INTS       (OISF_SCHEDOVERRUN|OISF_DONEHEAD|OISF_SOF|OISF_RESUMEDTX|OISF_HOSTERROR|OISF_FRAMECOUNTOVER|OISF_HUBCHANGE|OISF_MASTERENABLE)
 114
 115 /* OHCI_INTERVAL defines */
 116 #define OIVS_INTERVAL        0    /* Interval, usually 11999 == 0x2edf */
 117 #define OIVS_BITSPERFRAME   16    /* Size of the frames in bits, usually ((12000 - 210) * 6) / 7 == 10105 */
 118 #define OIVB_TOGGLE         31    /* Toggle on change of interval */
 119
 120 #define OIVM_INTERVAL       (((1UL<<14)-1)<<OIVS_INTERVAL)
 121 #define OIVM_BITSPERFRAME   (((1UL<<15)-1)<<OIVS_BITSPERFRAME)
 122 #define OIVF_TOGGLE         (1UL<<OIVB_TOGGLE)
 123
 124 #define OHCI_DEF_BITSPERFRAME 10105
 125
 126 /* OHCI_HUBDESCA defines */
 127 #define OHAS_NUMPORTS        0    /* Number of downstream ports */
 128 #define OHAB_INDIVIDUALPS    8    /* Power switching per port */
 129 #define OHAB_NOPOWERSWITCH   9    /* Ports always powered */
 130 #define OHAB_INDIVIDUALOC   11    /* Overcurrent Detection per port */
 131 #define OHAB_NOOVERCURRENT  12    /* No over-current detection */
 132 #define OHAS_POWERGOOD      24    /* Power-good delay */
 133
 134 #define OHAM_NUMPORTS       (((1UL<<8)-1)<<OHAS_NUMPORTS)
 135 #define OHAF_INDIVIDUALPS   (1UL<<OHAB_INDIVIDUALPS)
 136 #define OHAF_NOPOWERSWITCH  (1UL<<OHAB_NOPOWERSWITCH)
 137 #define OHAF_INDIVIDUALOC   (1UL<<OHAB_INDIVIDUALOC)
 138 #define OHAF_NOOVERCURRENT  (1UL<<OHAB_NOOVERCURRENT)
 139 #define OHAM_POWERGOOD      (((1UL<<8)-1)<<OHAS_POWERGOOD)
 140
 141 /* OHCI_HUBDESCB defines */
 142 #define OHBS_DEVREMOVABLE    0    /* Bitmask of removable devices at roothub (port 1 == bit 1) */
 143 #define OHBS_PORTPOWERCTRL  16    /* Bitmask of global power controlled ports */
 144
 145 #define OHBM_DEVREMOVABLE   (((1UL<<16)-1)<<OHBS_DEVREMOVABLE)
 146 #define OHBM_PORTPOWERCTRL  (((1UL<<16)-1)<<OHBS_PORTPOWERCTRL)
 147
 148 /* OHCI_HUBSTATUS defines */
 149 #define OHSB_UNPOWERHUB      0    /* Clear global Hub power */
 150 #define OHSB_OVERCURRENT     1    /* Global over-current reported */
 151 #define OHSB_POWERHUB       16    /* Set global Hub power */
 152 #define OHSB_OVERCURRENTCHG 17    /* Reports change in over-current situation */
 153
 154 #define OHSF_UNPOWERHUB     (1UL<<OHSB_UNPOWERHUB)
 155 #define OHSF_OVERCURRENT    (1UL<<OHSB_OVERCURRENT)
 156 #define OHSF_POWERHUB       (1UL<<OHSB_POWERHUB)
 157 #define OHSF_OVERCURRENTCHG (1UL<<OHSB_OVERCURRENTCHG)
 158
 159 /* OHCI_PORTSTATUS defines */
 160 #define OHPB_PORTCONNECTED   0    /* Port Connection status (r) */
 161 #define OHPB_PORTDISABLE     0    /* Clear Port enable (w) */
 162 #define OHPB_PORTENABLE      1    /* Port Enabled (r), Enable Port (w) */
 163 #define OHPB_PORTSUSPEND     2    /* Port Suspended (r), Suspend Port (w) */
 164 #define OHPB_OVERCURRENT     3    /* Port Overcurrent detected (r) */
 165 #define OHPB_RESUME          3    /* Resume from suspend (w) */
 166 #define OHPB_PORTRESET       4    /* Port in reset (r), Reset port (w) */
 167 #define OHPB_PORTPOWER       8    /* Power powered (r), Power port (w) */
 168 #define OHPB_LOWSPEED        9    /* Low speed device connected (r) */
 169 #define OHPB_PORTUNPOWER     9    /* Clear Port power (w) */
 170 #define OHPB_CONNECTCHANGE  16    /* Port Connection change */
 171 #define OHPB_ENABLECHANGE   17    /* Port Enable/Disable change */
 172 #define OHPB_RESUMEDTX      18    /* Resume detected */
 173 #define OHPB_OVERCURRENTCHG 19    /* Over-current change */
 174 #define OHPB_RESETCHANGE    20    /* Reset complete */
 175
 176 #define OHPF_PORTCONNECTED  (1UL<<OHPB_PORTCONNECTED)
 177 #define OHPF_PORTDISABLE    (1UL<<OHPB_PORTDISABLE)
 178 #define OHPF_PORTENABLE     (1UL<<OHPB_PORTENABLE)
 179 #define OHPF_PORTSUSPEND    (1UL<<OHPB_PORTSUSPEND)
 180 #define OHPF_OVERCURRENT    (1UL<<OHPB_OVERCURRENT)
 181 #define OHPF_RESUME         (1UL<<OHPB_RESUME)
 182 #define OHPF_PORTRESET      (1UL<<OHPB_PORTRESET)
 183 #define OHPF_PORTPOWER      (1UL<<OHPB_PORTPOWER)
 184 #define OHPF_LOWSPEED       (1UL<<OHPB_LOWSPEED)
 185 #define OHPF_PORTUNPOWER    (1UL<<OHPB_PORTUNPOWER)
 186 #define OHPF_CONNECTCHANGE  (1UL<<OHPB_CONNECTCHANGE)
 187 #define OHPF_ENABLECHANGE   (1UL<<OHPB_ENABLECHANGE)
 188 #define OHPF_RESUMEDTX      (1UL<<OHPB_RESUMEDTX)
 189 #define OHPF_OVERCURRENTCHG (1UL<<OHPB_OVERCURRENTCHG)
 190 #define OHPF_RESETCHANGE    (1UL<<OHPB_RESETCHANGE)
 191
 192 /* data structures */
 193
 194 /* HCCA registers */
 195
 196 #define OHCI_HCCA_SIZE        256 /* size of HCCA section */
 197 #define OHCI_HCCA_ALIGNMENT 0x0ff /* alignment of HCCA section */
 198
 199 struct OhciHCCA
 200 {
 201     ULONG           oha_IntEDs[32]; /* LE PHYSICAL pointer to Interrupt EDs */
 202     UWORD           oha_FrameCount; /* LE Framecounter */
 203     UWORD           oha_FrmCntChg;  /* Set 0 when framecounter was updated */
 204     ULONG           oha_DoneHead;   /* LE PHYSICAL pointer to Head of ED finished + unmasked Int */
 205 };
 206
 207
 208 #define OHCI_PAGE_SIZE           4096
 209
 210 #define OHCI_TDQH_ALIGNMENT      0x001f
 211
 212 #define OHCI_ED_POOLSIZE         128
 213 #define OHCI_TD_POOLSIZE         512
 214
 215 #define OHCI_TD_BULK_LIMIT       (128<<10) // limit for one batch of BULK data TDs
 216
 217
 218 struct OhciED
 219 {
 220     struct OhciED  *oed_Succ;
 221     struct OhciED  *oed_Pred;
 222     ULONG           oed_Self;       /* LE PHYSICAL pointer to self */
 223     /* On 64 bits a padding will be inserted here */
 224     struct IOUsbHWReq *oed_IOReq;   /* IO Request this belongs to */
 225
 226     struct OhciTD  *oed_FirstTD;    /* First TD */
 227     IPTR            oed_Continue;   /* Flag for fragmented bulk transfer */
 228     APTR            oed_Buffer;     /* Mirror buffer for data outside of DMA-accessible area */
 229     struct UsbSetupData *oed_SetupData; /* Mirror buffer for setup packet */
 230
 231     /* HC data, aligned to 16 bytes */
 232     ULONG           oed_EPCaps;     /* LE MaxPacketSize and other stuff */
 233     ULONG           oed_TailPtr;    /* LE PHYSICAL TD Queue Tail Pointer */
 234     ULONG           oed_HeadPtr;    /* LE PHYSICAL TD Queue Head Pointer */
 235     ULONG           oed_NextED;     /* LE PHYSICAL Next Endpoint Descriptor */
 236 };
 237
 238 struct OhciTD
 239 {
 240     struct OhciTD  *otd_Succ;
 241     IPTR            otd_Length;     /* Length of transfer */
 242     ULONG           otd_Self;       /* LE PHYSICAL pointer to self */
 243     /* On 64 bits a padding will be inserted here */
 244     struct OhciED  *otd_ED;         /* Pointer to parent ED this TD belongs to */
 245
 246     /* HC data, aligned to 16 bytes */
 247     ULONG           otd_Ctrl;       /* LE Ctrl stuff */
 248     ULONG           otd_BufferPtr;  /* LE PHYSICAL Current Buffer Pointer */
 249     ULONG           otd_NextTD;     /* LE PHYSICAL Next TD */
 250     ULONG           otd_BufferEnd;  /* LE PHYSICAL End of buffer */
 251 };
 252
 253 /* pointer defines */
 254
 255 #define OHCI_PTRMASK        0xfffffff0 /* frame list pointer mask */
 256
 257 /* ED EPCaps defines */
 258
 259 #define OECB_LOWSPEED       13    /* Lowspeed */
 260 #define OECB_SKIP           14    /* Skip ED */
 261 #define OECB_ISO            15    /* Isochronous endpoint */
 262
 263 #define OECS_DEVADDR         0    /* Device Address */
 264 #define OECS_ENDPOINT        7    /* Endpoint number */
 265 #define OECS_DIRECTION      11    /* Direction */
 266 #define OECS_MAXPKTLEN      16    /* MaxPacketLength */
 267
 268 #define OECF_LOWSPEED       (1UL<<OECB_LOWSPEED)
 269 #define OECF_SKIP           (1UL<<OECB_SKIP)
 270 #define OECF_ISO            (1UL<<OECB_ISO)
 271
 272 #define OECM_DEVADDR        (((1UL<<7)-1)<<OECS_DEVADDR)
 273 #define OECM_ENDPOINT       (((1UL<<4)-1)<<OECS_ENDPOINT)
 274 #define OECM_MAXPKTLEN      (((1UL<<11)-1)<<OECS_MAXPKTLEN)
 275
 276 #define OECM_DIRECTION      (((1UL<<2)-1)<<OECS_DIRECTION)
 277 #define OECF_DIRECTION_TD   (0UL<<OECS_DIRECTION)
 278 #define OECF_DIRECTION_OUT  (1UL<<OECS_DIRECTION)
 279 #define OECF_DIRECTION_IN   (2UL<<OECS_DIRECTION)
 280
 281 /* ED HeadPtr defines */
 282
 283 #define OEHB_HALTED          0    /* TD Queue is halted */
 284 #define OEHB_DATA1           1    /* Data 1 Toggle bit */
 285
 286 #define OEHF_HALTED         (1UL<<OEHB_HALTED)
 287 #define OEHF_DATA1          (1UL<<OEHB_DATA1)
 288
 289 /* TD Ctrl defines */
 290
 291 #define OTCB_ALLOWSHORTPKT  18    /* Allow short packets */
 292 #define OTCB_DATA1          24    /* Data 1 toggle bit */
 293 #define OTCB_TOGGLEFROMTD   25    /* Data toggle comes from TD */
 294
 295 #define OTCS_PIDCODE        19    /* PID code */
 296 #define OTCS_DELAYINT       21    /* Delay interrupt by given amount of frames */
 297 #define OTCS_ERRORCOUNT     26    /* Number of errors occurred so far */
 298 #define OTCS_COMPLETIONCODE 28    /* Error codes */
 299
 300 #define OTCF_ALLOWSHORTPKT  (1UL<<OTCB_ALLOWSHORTPKT)
 301 #define OTCF_DATA0          (0UL<<OTCB_DATA1)
 302 #define OTCF_DATA1          (1UL<<OTCB_DATA1)
 303 #define OTCF_TOGGLEFROMTD   (1UL<<OTCB_TOGGLEFROMTD)
 304
 305 #define OTCM_PIDCODE        (((1UL<<2)-1)<<OTCS_PIDCODE)
 306 #define OTCF_PIDCODE_SETUP  (0UL<<OTCS_PIDCODE)
 307 #define OTCF_PIDCODE_OUT    (1UL<<OTCS_PIDCODE)
 308 #define OTCF_PIDCODE_IN     (2UL<<OTCS_PIDCODE)
 309
 310 #define OTCM_DELAYINT       (((1UL<<3)-1)<<OTCS_DELAYINT)
 311 #define OTCF_NOINT          (7UL<<OTCS_DELAYINT)
 312
 313 #define OTCM_ERRORCOUNT     (((1UL<<2)-1)<<OTCS_ERRORCOUNT)
 314 #define OTCM_COMPLETIONCODE (((1UL<<4)-1)<<OTCS_COMPLETIONCODE)
 315 #define OTCF_CC_NOERROR     (0UL<<OTCS_COMPLETIONCODE)
 316 #define OTCF_CC_CRCERROR    (1UL<<OTCS_COMPLETIONCODE)
 317 #define OTCF_CC_BABBLE      (2UL<<OTCS_COMPLETIONCODE)
 318 #define OTCF_CC_WRONGTOGGLE (3UL<<OTCS_COMPLETIONCODE)
 319 #define OTCF_CC_STALL       (4UL<<OTCS_COMPLETIONCODE)
 320 #define OTCF_CC_TIMEOUT     (5UL<<OTCS_COMPLETIONCODE)
 321 #define OTCF_CC_PIDCORRUPT  (6UL<<OTCS_COMPLETIONCODE)
 322 #define OTCF_CC_WRONGPID    (7UL<<OTCS_COMPLETIONCODE)
 323 #define OTCF_CC_OVERFLOW    (8UL<<OTCS_COMPLETIONCODE)
 324 #define OTCF_CC_SHORTPKT    (9UL<<OTCS_COMPLETIONCODE)
 325 #define OTCF_CC_OVERRUN     (12UL<<OTCS_COMPLETIONCODE)
 326 #define OTCF_CC_UNDERRUN    (13UL<<OTCS_COMPLETIONCODE)
 327 #define OTCF_CC_INVALID     (15UL<<OTCS_COMPLETIONCODE)
 328
 329 #endif /* OHCICHIP_H */