arch/all-native/hidd/vgagfx/vgagfx_support.h

   1 #ifndef VGAGFX_SUPPORT_H
   2 #define VGAGFX_SUPPORT_H
   3
   4 /*
   5     Copyright © 1995-2017, The AROS Development Team. All rights reserved.
   6     $Id$
   7
   8     Desc: VGAGfx hardware support.
   9     Lang: English.
  10 */
  11
  12 #if (1)
  13 /* I have to move away this defines - should be in separate file */
  14
  15 #define inb(port) \
  16     ({  char __value;   \
  17         __asm__ __volatile__ ("inb %%dx,%%al":"=a"(__value):"d"(port)); \
  18         __value;        })
  19
  20 #define outb(port,val) \
  21     ({  char __value=(val);     \
  22         __asm__ __volatile__ ("outb %%al,%%dx"::"a"(__value),"d"(port)); })
  23
  24 #define inw(port) \
  25     ({  short __value;  \
  26         __asm__ __volatile__ ("inw %%dx,%%ax":"=a"(__value):"d"(port)); \
  27         __value;        })
  28
  29 #define outw(port,val) \
  30     ({  short __value=(val);    \
  31         __asm__ __volatile__ ("outw %%ax,%%dx"::"a"(__value),"d"(port)); })
  32
  33 #define inl(port) \
  34     ({  LONG __value;   \
  35         __asm__ __volatile__ ("inl %%dx,%%eax":"=a"(__value):"d"(port));        \
  36         __value;        })
  37
  38 #define outl(port,val) \
  39     ({  LONG __value=(val);     \
  40         __asm__ __volatile__ ("outl %%eax,%%dx"::"a"(__value),"d"(port)); })
  41
  42 #endif
  43
  44 #define DACDelay \
  45         { \
  46                 unsigned char temp = inb(vgaIOBase + 0x0A); \
  47                 temp = inb(vgaIOBase + 0x0A); \
  48         }
  49
  50 /* This structure keeps contents of mode registers including palette */
  51
  52 struct vgaHWRec
  53 {
  54   unsigned char MiscOutReg;     /* */
  55   unsigned char CRTC[25];       /* Crtc Controller */
  56   unsigned char Sequencer[5];   /* Video Sequencer */
  57   unsigned char Graphics[9];    /* Video Graphics */
  58   unsigned char Attribute[21];  /* Video Atribute */
  59   unsigned char DAC[768];       /* Internal Colorlookuptable */
  60   char NoClock;                 /* number of selected clock */
  61 };
  62
  63 /* CRT controller register indices */
  64
  65 #define CRTC_H_TOTAL        0
  66 #define CRTC_H_DISPLAY      1
  67 #define CRTC_H_BLANK_START  2
  68 #define CRTC_H_BLANK_END    3
  69 #define CRTC_H_SYNC_START   4
  70 #define CRTC_H_SYNC_END     5
  71 #define CRTC_V_TOTAL        6
  72 #define CRTC_OVERFLOW       7
  73 #define CRTC_PRESET_ROW     8
  74 #define CRTC_MAX_SCAN       9
  75 #define CRTC_CURSOR_START   10
  76 #define CRTC_CURSOR_END     11
  77 #define CRTC_START_HI       12
  78 #define CRTC_START_LO       13
  79 #define CRTC_CURSOR_HI      14
  80 #define CRTC_CURSOR_LO      15
  81 #define CRTC_V_SYNC_START   16
  82 #define CRTC_V_SYNC_END     17
  83 #define CRTC_V_DISP_END     18
  84 #define CRTC_OFFSET         19
  85 #define CRTC_UNDERLINE      20
  86 #define CRTC_V_BLANK_START  21
  87 #define CRTC_V_BLANK_END    22
  88 #define CRTC_MODE           23
  89 #define CRTC_LINE_COMPARE   24
  90
  91 #endif /* VGAGFX_SUPPORT_H */