2 Copyright © 1995-2001, The AROS Development Team. All rights reserved.
6 /*****************************************************************************
10 AROS_LH0(void, CacheClearU,
13 struct ExecBase *, SysBase, 106, Exec)
16 Flushes the contents of all CPU caches in a simple way.
32 68020/30: clear instruction cache and (030) data cache
33 68040/60: push dirty lines to memory and invalidate both caches
37 ******************************************************************************/
41 XDEF AROS_SLIB_ENTRY(CacheClearU_00,Exec,106) ; for 68000/68010
42 XDEF AROS_SLIB_ENTRY(CacheClearU_20,Exec,106) ; for 68020/68030
43 XDEF AROS_SLIB_ENTRY(CacheClearU_40,Exec,106) ; for 68040/68060
44 XDEF AROS_SLIB_ENTRY(CacheClearU_60,Exec,106) ; for 68060 (clears not only
45 ; the i and d caches, but also
49 #include "aros/m68k/asm.h"
54 .globl AROS_SLIB_ENTRY(CacheClearU_00,Exec,106)
55 .type AROS_SLIB_ENTRY(CacheClearU_00,Exec,106),@function
56 AROS_SLIB_ENTRY(CacheClearU_00,Exec,106):
57 /* Simple 68000s have no chaches */
67 .globl AROS_SLIB_ENTRY(CacheClearU_20,Exec,106)
68 .type AROS_SLIB_ENTRY(CacheClearU_20,Exec,106),@function
69 AROS_SLIB_ENTRY(CacheClearU_20,Exec,106):
75 move.l %a5,%a1 /* Save a5 */
76 lea.l cacheclearusup_20,%a5
77 jmp Supervisor(%a6) /* No jsr: this saves an rts */
80 or.w #0x0700,%sr /* Disable interrupts so cacr can not be influenced
81 while we clear the caches */
83 or.w #0x0808,%d0 /* Set CD and CI bit in cacr */
85 move.l %a1,%a5 /* Restore a5 */
86 rte /* This rte will restore the SR from the stack */
90 .globl AROS_SLIB_ENTRY(CacheClearU_40,Exec,106)
91 .type AROS_SLIB_ENTRY(CacheClearU_40,Exec,106),@function
92 AROS_SLIB_ENTRY(CacheClearU_40,Exec,106):
99 lea.l cacheclearusup_40,%a5
104 .globl AROS_SLIB_ENTRY(CacheClearU_60,Exec,106)
105 .type AROS_SLIB_ENTRY(CacheClearU_60,Exec,106),@function
106 AROS_SLIB_ENTRY(CacheClearU_60,Exec,106):
113 lea.l cacheclearusup_60,%a5
117 nop /* old 68040 revision bug workaround */
119 cpusha %bc /* Push dirty cache lines to memory and invalidate both caches */
125 movem.l %d0-%d1/%a0-%a1,-(%sp)
129 movem.l (%sp)+,%d0-%d1/%a0-%a1