revert 213 commits (to 56092) from the last month. 10 still need work to resolve...
[AROS.git] / developer / debug / test / misc / getcpuinfo.c
blob81ae42dd951fba395711f5c936a4c58da5a7bb7a
1 /*
2 Copyright © 1995-2017, The AROS Development Team. All rights reserved.
3 $Id$
4 */
6 #include <proto/exec.h>
7 #include <resources/processor.h>
8 #include <stdio.h>
9 #if !defined(STATICBUILD)
10 #include <proto/processor.h>
12 APTR ProcessorBase = NULL;
13 #else
14 #include "processor_intern.h"
15 struct ProcessorBase ProcBase;
16 void Processor_GetCPUInfo(struct TagItem * tagList, struct ProcessorBase * ProcessorBase);
17 LONG Processor_Init(struct ProcessorBase * ProcessorBase);
18 #define GetCPUInfo(x) Processor_GetCPUInfo(x, &ProcBase)
19 #endif
21 static ULONG getcpucount()
23 ULONG cpucount = 0;
24 struct TagItem tags [] =
26 {GCIT_NumberOfProcessors, (IPTR)&cpucount},
27 {TAG_DONE, TAG_DONE}
30 GetCPUInfo(tags);
32 printf("CPU Count: %d\n", (int)cpucount);
34 return cpucount;
37 struct TagDescription
39 ULONG Value;
40 CONST_STRPTR Description;
43 struct TagDescription VectorUnit [] =
45 { VECTORTYPE_NONE, "None"},
46 { VECTORTYPE_ALTIVEC, "AltiVec"},
47 { VECTORTYPE_VMX, "VMX"},
48 { VECTORTYPE_MMX, "MMX"},
49 { VECTORTYPE_SSE, "SSE"},
50 { VECTORTYPE_SSE2, "SSE2"},
51 { VECTORTYPE_SSE3, "SSE3"},
52 { VECTORTYPE_SSSE3, "SSSE3"},
53 { VECTORTYPE_SSE41, "SSE41"},
54 { VECTORTYPE_SSE42, "SSE42"},
55 { VECTORTYPE_MMXEXT, "MMX Ext"},
56 { VECTORTYPE_3DNOW, "3DNow"},
57 { VECTORTYPE_3DNOWEXT, "3DNow Ext"},
58 { VECTORTYPE_SSE4A, "SSE4A"},
59 { 0, NULL }
62 struct TagDescription ProcessorFamily [] =
64 { CPUFAMILY_UNKNOWN, "Unknown" },
65 { CPUFAMILY_MOTOROLA_68000, "Motorola MC680x0" },
66 { CPUFAMILY_60X, "IBM PowerPC 60x" },
67 { CPUFAMILY_7X0, "IBM PowerPC 7x0" },
68 { CPUFAMILY_74XX, "IBM PowerPC 74xx" },
69 { CPUFAMILY_4XX, "IBM PowerPC 4xx" },
70 { CPUFAMILY_AMD_K5, "AMD K5" },
71 { CPUFAMILY_AMD_K6, "AMD K6" },
72 { CPUFAMILY_AMD_K7, "AMD K7" },
73 { CPUFAMILY_AMD_K8, "AMD K8" },
74 { CPUFAMILY_AMD_K9, "AMD K9" },
75 { CPUFAMILY_AMD_K10, "AMD K10" },
76 { CPUFAMILY_INTEL_486, "Intel 486" },
77 { CPUFAMILY_INTEL_PENTIUM, "Intel Pentium" },
78 { CPUFAMILY_INTEL_PENTIUM_PRO, "Intel Pentium Pro" },
79 { CPUFAMILY_INTEL_PENTIUM4, "Intel Pentium 4"},
80 { 0, NULL },
83 struct TagDescription ProcessorArchitecture [] =
85 { PROCESSORARCH_UNKNOWN, "Unknown" },
86 { PROCESSORARCH_M68K, "M68K" },
87 { PROCESSORARCH_PPC, "PowerPC" },
88 { PROCESSORARCH_X86, "X86" },
89 { PROCESSORARCH_ARM, "ARM" },
90 { 0, NULL }
93 struct TagDescription CurrentEndianness [] =
95 { ENDIANNESS_UNKNOWN, "Unknown" },
96 { ENDIANNESS_LE, "LE" },
97 { ENDIANNESS_BE, "BE" },
98 { 0, NULL}
101 struct TagDescription ProcessorFeatures [] =
103 { GCIT_SupportsFPU, "FPU" },
104 { GCIT_SupportsAltiVec, "AltiVec" },
105 { GCIT_SupportsVMX, "VMX" },
106 { GCIT_SupportsMMX, "MMX" },
107 { GCIT_SupportsMMXEXT, "AMD MMX Entensions" },
108 { GCIT_Supports3DNOW, "3DNow!" },
109 { GCIT_Supports3DNOWEXT, "AMD 3DNow! Extensions" },
110 { GCIT_SupportsSSE, "SSE" },
111 { GCIT_SupportsSSE2, "SSE2" },
112 { GCIT_SupportsSSE3, "SSE3" },
113 { GCIT_SupportsSSSE3, "SSSE3" },
114 { GCIT_SupportsSSE41, "SSE4.1" },
115 { GCIT_SupportsSSE42, "SSE4.2" },
116 { GCIT_SupportsSSE4A, "SSE4a" },
117 { GCIT_SupportsVME, "Virtual Mode Extension" },
118 { GCIT_SupportsPSE, "Page Size Extension" },
119 { GCIT_SupportsPAE, "Physical Address Extension" },
120 { GCIT_SupportsCX8, "CMPXCHG8 Instruction" },
121 { GCIT_SupportsAPIC, "APIC" },
122 { GCIT_SupportsCMOV, "Conditional Move Instruction" },
123 { GCIT_SupportsPSE36, "36-bit Page Size Extension" },
124 { GCIT_SupportsCLFSH, "CLFLUSH Instruction" },
125 { GCIT_SupportsACPI, "ACPI" },
126 { GCIT_SupportsFXSR, "FXSAVE and FXSTOR Instructions" },
127 { GCIT_SupportsHTT, "Hyper-Threading Technology" },
128 { GCIT_SupportsCX16, "CMPXCHG16B Instruction" },
129 { GCIT_SupportsVirtualization, "Virtualization Technology" },
130 { GCIT_SupportsNoExecutionBit, "No-Execution Page Bit" },
131 { GCIT_Supports64BitMode, "64-bit Capable (x86-64)" },
132 { GCIT_SupportsMSR, "MSR (Model Specific Registers)" },
133 { 0, NULL }
136 CONST_STRPTR GetDescription(struct TagDescription * table, ULONG value)
138 static CONST_STRPTR undefined = "Undefined";
140 LONG i = 0;
141 while (table[i].Description != NULL)
143 if (table[i].Value == value)
144 return table[i].Description;
145 i++;
148 return undefined;
151 static void printcpuinformation(ULONG index)
153 CONST_STRPTR modelstring;
154 ULONG family, vectorunit;
155 ULONG i = 0;
156 ULONG l1size, l1datasize, l1instrsize, l2size, l3size, cachelinesize;
157 ULONG architecture, endianness;
158 UQUAD currentspeed, fsbspeed;
160 struct TagItem tags [] =
162 {GCIT_SelectedProcessor, index},
163 {GCIT_ModelString, (IPTR)&modelstring},
164 {GCIT_Family, (IPTR)&family},
165 {GCIT_VectorUnit, (IPTR)&vectorunit},
166 {GCIT_L1CacheSize, (IPTR)&l1size},
167 {GCIT_L1DataCacheSize, (IPTR)&l1datasize},
168 {GCIT_L1InstructionCacheSize, (IPTR)&l1instrsize},
169 {GCIT_L2CacheSize, (IPTR)&l2size},
170 {GCIT_L3CacheSize, (IPTR)&l3size},
171 {GCIT_CacheLineSize, (IPTR)&cachelinesize},
172 {GCIT_Architecture, (IPTR)&architecture},
173 {GCIT_Endianness, (IPTR)&endianness},
174 {GCIT_ProcessorSpeed, (IPTR)&currentspeed},
175 {GCIT_FrontsideSpeed, (IPTR)&fsbspeed},
176 {TAG_DONE, TAG_DONE}
179 GetCPUInfo(tags);
181 printf("CPU: %d\n", (int)index);
182 printf("Family: %d\n", (int)family);
183 printf("FamilyString: %s\n", GetDescription(ProcessorFamily, family));
184 printf("ModelString: %s\n", modelstring);
185 printf("Vector Unit: %s\n", GetDescription(VectorUnit, vectorunit));
186 printf("Architecture: %s\n", GetDescription(ProcessorArchitecture, architecture));
187 printf("Endianness: %s\n", GetDescription(CurrentEndianness, endianness));
189 printf("Current Speed: %u Mhz\n", (unsigned)(currentspeed / 1000000));
190 printf("Frontside Bus Speed: %u Mhz\n", (unsigned)(fsbspeed / 1000000));
192 printf("L1CacheSize: %d kB\n", (int)l1size);
193 printf("L1DataCacheSize: %d kB\n", (int)l1datasize);
194 printf("L1InstructionCacheSize: %d kB\n", (int)l1instrsize);
195 printf("L2CacheSize: %d kB\n", (int)l2size);
196 printf("L3CacheSize: %d kB\n", (int)l3size);
197 printf("CacheLineSize: %d B\n", (int)cachelinesize);
199 printf("Features:\n");
200 i = 0;
201 while(ProcessorFeatures[i].Description != NULL)
203 BOOL check = FALSE;
204 struct TagItem ftags [] =
206 { GCIT_SelectedProcessor, index },
207 { ProcessorFeatures[i].Value, (IPTR)&check },
208 { TAG_DONE, TAG_DONE }
211 GetCPUInfo(ftags);
213 if (check)
214 printf(" [%s]\n", ProcessorFeatures[i].Description);
215 i++;
219 int main(void)
221 ULONG cpus = 0;
222 ULONG index = 0;
224 #if !defined(STATICBUILD)
225 if ((ProcessorBase = OpenResource(PROCESSORNAME)) == NULL)
227 printf("Not able to open %s\n", PROCESSORNAME);
228 return 1;
230 #else
231 Processor_Init(&ProcBase);
232 #endif
234 cpus = getcpucount();
236 for(index = 0; index < cpus; index++)
237 printcpuinformation(index);
239 return 0;