workbench/libs/mesa/src/gallium/drivers/nvc0/nvc0_program.h

   1
   2 #ifndef __NVC0_PROGRAM_H__
   3 #define __NVC0_PROGRAM_H__
   4
   5 #include "pipe/p_state.h"
   6 #include "tgsi/tgsi_scan.h"
   7
   8 #define NVC0_CAP_MAX_PROGRAM_TEMPS 64
   9
  10 #define NVC0_SHADER_HEADER_SIZE (20 * 4)
  11
  12 struct nvc0_program {
  13    struct pipe_shader_state pipe;
  14
  15    ubyte type;
  16    boolean translated;
  17    ubyte max_gpr;
  18
  19    uint32_t *code;
  20    unsigned code_base;
  21    unsigned code_size;
  22    unsigned parm_size;
  23
  24    uint32_t hdr[20]; /* TODO: move this into code to save space */
  25
  26    uint32_t flags[2];
  27
  28    struct {
  29       uint8_t edgeflag;
  30       uint8_t num_ucps;
  31       uint8_t out_pos[PIPE_MAX_SHADER_OUTPUTS];
  32    } vp;
  33    struct {
  34       uint8_t early_z;
  35       uint8_t in_pos[PIPE_MAX_SHADER_INPUTS];
  36    } fp;
  37
  38    void *relocs;
  39    unsigned num_relocs;
  40
  41    struct nouveau_resource *res;
  42 };
  43
  44 /* first 2 bits are written into the program header, for each input */
  45 #define NVC0_INTERP_FLAT          (1 << 0)
  46 #define NVC0_INTERP_PERSPECTIVE   (2 << 0)
  47 #define NVC0_INTERP_LINEAR        (3 << 0)
  48 #define NVC0_INTERP_CENTROID      (1 << 2)
  49
  50 /* analyze TGSI and see which TEMP[] are used as subroutine inputs/outputs */
  51 struct nvc0_subroutine {
  52    unsigned id;
  53    unsigned first_insn;
  54    uint32_t argv[NVC0_CAP_MAX_PROGRAM_TEMPS][4];
  55    uint32_t retv[NVC0_CAP_MAX_PROGRAM_TEMPS][4];
  56 };
  57
  58 struct nvc0_translation_info {
  59    struct nvc0_program *prog;
  60    struct tgsi_full_instruction *insns;
  61    unsigned num_insns;
  62    ubyte input_file;
  63    ubyte output_file;
  64    ubyte fp_depth_output;
  65    uint16_t input_loc[PIPE_MAX_SHADER_INPUTS][4];
  66    uint16_t output_loc[PIPE_MAX_SHADER_OUTPUTS][4];
  67    uint16_t sysval_loc[TGSI_SEMANTIC_COUNT];
  68    boolean sysval_in[TGSI_SEMANTIC_COUNT];
  69    int input_access[PIPE_MAX_SHADER_INPUTS][4];
  70    int output_access[PIPE_MAX_SHADER_OUTPUTS][4];
  71    ubyte interp_mode[PIPE_MAX_SHADER_INPUTS];
  72    boolean indirect_inputs;
  73    boolean indirect_outputs;
  74    boolean require_stores;
  75    boolean global_stores;
  76    uint32_t *immd32;
  77    ubyte *immd32_ty;
  78    unsigned immd32_nr;
  79    unsigned temp128_nr;
  80    ubyte edgeflag_out;
  81    struct nvc0_subroutine *subr;
  82    unsigned num_subrs;
  83    boolean append_ucp;
  84    struct tgsi_shader_info scan;
  85 };
  86
  87 int nvc0_generate_code(struct nvc0_translation_info *);
  88
  89 void nvc0_relocate_program(struct nvc0_program *,
  90                            uint32_t code_base, uint32_t data_base);
  91
  92 #endif