rom/usb/classes/asixeth/asixeth.h

   1 #ifndef ASIXETH_H
   2 #define ASIXETH_H
   3
   4 #include <intuition/intuition.h>
   5 #include <intuition/intuitionbase.h>
   6 #include <libraries/mui.h>
   7 #include <libraries/gadtools.h>
   8 #include <devices/sana2.h>
   9 #include <devices/sana2specialstats.h>
  10 #include <exec/devices.h>
  11
  12 #if defined(__GNUC__)
  13 # pragma pack(2)
  14 #endif
  15
  16 #define PF_AX88178      0x0001
  17 #define PF_AX88772      0x0002
  18 #define PF_DLINKGPIO    0x0010 // 0x9f9d9f
  19 #define PF_HAWKINGGPIO  0x0020 // 0x1f1d1f
  20
  21 #define DDF_CONFIGURED (1<<2)  /* station address is configured */
  22 #define DDF_ONLINE     (1<<3)  /* device is online */
  23 #define DDF_OFFLINE    (1<<4)  /* device was put offline */
  24
  25 #define DROPPED        (1<<0)  /* Did the packet get dropped? */
  26 #define PACKETFILTER   (1<<1)  /* Use the packet filter? */
  27
  28 /* Ethernet address bytesize
  29 */
  30 #define ETHER_ADDR_SIZE 6
  31
  32 #define ETHER_MIN_LEN  60           /* smallest amount that nic will accept */
  33 #define ETHER_MAX_LEN  2048         /* largest legal amount for Ethernet */
  34
  35 /* Ethernet packet data sizes (maximum)
  36 */
  37 #define ETHERPKT_SIZE  1500
  38 #define RAWPKT_SIZE    1514
  39
  40 /* ASIX AX8817X based USB 2.0 Ethernet Devices */
  41
  42 #define UAXR_SET_SW_MII               0x06
  43 #define UAXR_READ_MII_REG             0x07
  44 #define UAXR_WRITE_MII_REG            0x08
  45 #define UAXR_SET_HW_MII               0x0a
  46 #define UAXR_READ_EEPROM              0x0b
  47 #define UAXR_WRITE_EEPROM             0x0c
  48 #define UAXR_WRITE_ENABLE             0x0d
  49 #define UAXR_WRITE_DISABLE            0x0e
  50 #define UAXR_READ_RX_CTL              0x0f
  51 #define UAXR_WRITE_RX_CTL             0x10
  52 #define UAXR_READ_IPG012              0x11
  53 #define UAXR_WRITE_IPG0               0x12
  54 #define UAXR_WRITE_IPG1               0x13
  55 #define UAXR_READ_NODE_ID             0x13
  56 #define UAXR_WRITE_IPG2               0x14
  57 #define UAXR_WRITE_MULTI_FILTER       0x16
  58 #define UAXR_READ_NODE_ID_2           0x17
  59 #define UAXR_READ_PHY_ID              0x19
  60 #define UAXR_READ_MEDIUM_STATUS       0x1a
  61 #define UAXR_WRITE_MEDIUM_MODE        0x1b
  62 #define UAXR_READ_MONITOR_MODE        0x1c
  63 #define UAXR_WRITE_MONITOR_MODE       0x1d
  64 #define UAXR_READ_GPIOS               0x1e
  65 #define UAXR_WRITE_GPIOS              0x1f
  66 #define UAXR_SW_RESET                 0x20
  67 #define UAXR_SW_PHY_STATUS            0x21
  68 #define UAXR_SW_PHY_SELECT            0x22
  69
  70 #define AX_MONITOR_MODE                 0x01
  71 #define AX_MONITOR_LINK                 0x02
  72 #define AX_MONITOR_MAGIC                0x04
  73 #define AX_MONITOR_HSFS                 0x10
  74
  75 /* AX88172 Medium Status Register values */
  76 #define AX88172_MEDIUM_FD               0x02
  77 #define AX88172_MEDIUM_TX               0x04
  78 #define AX88172_MEDIUM_FC               0x10
  79 #define AX88172_MEDIUM_DEFAULT  (AX88172_MEDIUM_FD|AX88172_MEDIUM_TX|AX88172_MEDIUM_FC)
  80
  81 #define AX_MCAST_FILTER_SIZE            8
  82 #define AX_MAX_MCAST                    64
  83
  84 #define AX_SWRESET_CLEAR                0x00
  85 #define AX_SWRESET_RR                   0x01
  86 #define AX_SWRESET_RT                   0x02
  87 #define AX_SWRESET_PRTE                 0x04
  88 #define AX_SWRESET_PRL                  0x08
  89 #define AX_SWRESET_BZ                   0x10
  90 #define AX_SWRESET_IPRL                 0x20
  91 #define AX_SWRESET_IPPD                 0x40
  92
  93 #define AX88772_IPG0_DEFAULT            0x15
  94 #define AX88772_IPG1_DEFAULT            0x0c
  95 #define AX88772_IPG2_DEFAULT            0x12
  96
  97 /* AX88772 & AX88178 Medium Mode Register */
  98 #define AX_MEDIUM_PF            0x0080
  99 #define AX_MEDIUM_JFE           0x0040
 100 #define AX_MEDIUM_TFC           0x0020
 101 #define AX_MEDIUM_RFC           0x0010
 102 #define AX_MEDIUM_ENCK          0x0008
 103 #define AX_MEDIUM_AC            0x0004
 104 #define AX_MEDIUM_FD            0x0002
 105 #define AX_MEDIUM_GM            0x0001
 106 #define AX_MEDIUM_SM            0x1000
 107 #define AX_MEDIUM_SBP           0x0800
 108 #define AX_MEDIUM_PS            0x0200
 109 #define AX_MEDIUM_RE            0x0100
 110
 111 #define AX88178_MEDIUM_DEFAULT  (AX_MEDIUM_PS|AX_MEDIUM_FD|AX_MEDIUM_AC|AX_MEDIUM_RFC|AX_MEDIUM_TFC|AX_MEDIUM_RE|AX_MEDIUM_JFE)
 112
 113 #define AX88772_MEDIUM_DEFAULT  (AX_MEDIUM_PS|AX_MEDIUM_FD|AX_MEDIUM_AC|AX_MEDIUM_RFC|AX_MEDIUM_TFC|AX_MEDIUM_RE)
 114
 115 /* AX88772 & AX88178 RX_CTL values */
 116 #define AX_RX_CTL_SO                    0x0080
 117 #define AX_RX_CTL_AP                    0x0020
 118 #define AX_RX_CTL_AM                    0x0010
 119 #define AX_RX_CTL_AB                    0x0008
 120 #define AX_RX_CTL_SEP                   0x0004
 121 #define AX_RX_CTL_AMALL                 0x0002
 122 #define AX_RX_CTL_PRO                   0x0001
 123 #define AX_RX_CTL_MFB_2048              0x0000
 124 #define AX_RX_CTL_MFB_4096              0x0100
 125 #define AX_RX_CTL_MFB_8192              0x0200
 126 #define AX_RX_CTL_MFB_16384             0x0300
 127
 128 #define AX_DEFAULT_RX_CTL       (AX_RX_CTL_SO|AX_RX_CTL_AB)
 129
 130 /* GPIO 0 .. 2 toggles */
 131 #define AX_GPIO_GPO0EN          0x01    /* GPIO0 Output enable */
 132 #define AX_GPIO_GPO_0           0x02    /* GPIO0 Output value */
 133 #define AX_GPIO_GPO1EN          0x04    /* GPIO1 Output enable */
 134 #define AX_GPIO_GPO_1           0x08    /* GPIO1 Output value */
 135 #define AX_GPIO_GPO2EN          0x10    /* GPIO2 Output enable */
 136 #define AX_GPIO_GPO_2           0x20    /* GPIO2 Output value */
 137 #define AX_GPIO_RESERVED        0x40    /* Reserved */
 138 #define AX_GPIO_RSE             0x80    /* Reload serial EEPROM */
 139
 140 #define AX_EEPROM_MAGIC         0xdeadbeef
 141 #define AX88172_EEPROM_LEN      0x40
 142 #define AX88772_EEPROM_LEN      0xff
 143
 144 #define PHY_MODE_MARVELL        0x0000
 145 #define MII_MARVELL_LED_CTRL    0x0018
 146 #define MII_MARVELL_STATUS      0x001b
 147 #define MII_MARVELL_CTRL        0x0014
 148
 149 #define MARVELL_LED_MANUAL      0x0019
 150
 151 #define MARVELL_STATUS_HWCFG    0x0004
 152
 153 #define MARVELL_CTRL_TXDELAY    0x0002
 154 #define MARVELL_CTRL_RXDELAY    0x0080
 155
 156 /* PHY stuff */
 157
 158 /* Generic MII registers. */
 159
 160 #define MII_BMCR            0x00        /* Basic mode control register */
 161 #define MII_BMSR            0x01        /* Basic mode status register  */
 162 #define MII_PHYSID1         0x02        /* PHYS ID 1                   */
 163 #define MII_PHYSID2         0x03        /* PHYS ID 2                   */
 164 #define MII_ADVERTISE       0x04        /* Advertisement control reg   */
 165 #define MII_LPA             0x05        /* Link partner ability reg    */
 166 #define MII_EXPANSION       0x06        /* Expansion register          */
 167 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
 168 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
 169 #define MII_ESTATUS         0x0f        /* Extended Status */
 170 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 171 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 172 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
 173 #define MII_RERRCOUNTER     0x15        /* Receive error counter       */
 174 #define MII_SREVISION       0x16        /* Silicon revision            */
 175 #define MII_RESV1           0x17        /* Reserved...                 */
 176 #define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
 177 #define MII_PHYADDR         0x19        /* PHY address                 */
 178 #define MII_RESV2           0x1a        /* Reserved...                 */
 179 #define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
 180 #define MII_NCONFIG         0x1c        /* Network interface config    */
 181
 182 /* Basic mode control register. */
 183 #define BMCR_RESV               0x003f  /* Unused...                   */
 184 #define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
 185 #define BMCR_CTST               0x0080  /* Collision test              */
 186 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 187 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
 188 #define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
 189 #define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
 190 #define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
 191 #define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
 192 #define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
 193 #define BMCR_RESET              0x8000  /* Reset the DP83840           */
 194
 195 /* Basic mode status register. */
 196 #define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
 197 #define BMSR_JCD                0x0002  /* Jabber detected             */
 198 #define BMSR_LSTATUS            0x0004  /* Link status                 */
 199 #define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
 200 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 201 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 202 #define BMSR_RESV               0x00c0  /* Unused...                   */
 203 #define BMSR_ESTATEN            0x0100  /* Extended Status in R15 */
 204 #define BMSR_100FULL2           0x0200  /* Can do 100BASE-T2 HDX */
 205 #define BMSR_100HALF2           0x0400  /* Can do 100BASE-T2 FDX */
 206 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
 207 #define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
 208 #define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
 209 #define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
 210 #define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
 211
 212 #define BMSR_MEDIA (BMSR_10HALF|BMSR_10FULL|BMSR_100HALF|BMSR_100FULL|BMSR_ANEGCAPABLE)
 213
 214 /* Advertisement control register. */
 215 #define ADVERTISE_SLCT          0x001f  /* Selector bits               */
 216 #define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
 217 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
 218 #define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
 219 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
 220 #define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
 221 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
 222 #define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
 223 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
 224 #define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
 225 #define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
 226 #define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
 227 #define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
 228 #define ADVERTISE_RESV          0x1000  /* Unused...                   */
 229 #define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
 230 #define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
 231 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
 232
 233 /* 1000BASE-T Control register */
 234 #define ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex */
 235 #define ADVERTISE_1000HALF      0x0100  /* Advertise 1000BASE-T half duplex */
 236
 237 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
 238                         ADVERTISE_CSMA)
 239 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
 240                        ADVERTISE_100HALF | ADVERTISE_100FULL)
 241
 242 #define ID_ABOUT        0x55555555
 243 #define ID_STORE_CONFIG 0xaaaaaaaa
 244 #define ID_DEF_CONFIG   0xaaaaaaab
 245
 246 #define MT_AUTO                 0x0000
 247 #define MT_10BASE_T_HALF_DUP    0x0001
 248 #define MT_10BASE_T_FULL_DUP    0x0002
 249 #define MT_100BASE_TX_HALF_DUP  0x0003
 250 #define MT_100BASE_TX_FULL_DUP  0x0004
 251 #define MT_1000BASE_TX_HALF_DUP 0x0005
 252 #define MT_1000BASE_TX_FULL_DUP 0x0006
 253
 254 struct ClsDevCfg
 255 {
 256     ULONG cdc_ChunkID;
 257     ULONG cdc_Length;
 258     ULONG cdc_DefaultUnit;
 259     ULONG cdc_MediaType;
 260 };
 261
 262 #if defined(__GNUC__)
 263 # pragma pack()
 264 #endif
 265
 266 /* Structure of an ethernet packet - internal
 267 */
 268
 269 struct EtherPacketHeader
 270 {
 271     UBYTE       eph_Dest[ETHER_ADDR_SIZE]; /* 0 destination address */
 272     UBYTE       eph_Src[ETHER_ADDR_SIZE]; /* 6 originator  address */
 273     UWORD       eph_Type;                 /* 12 packet type */
 274 };
 275
 276 /* Buffer management node - private
 277 */
 278 struct BufMan
 279 {
 280     struct Node bm_Node;
 281     APTR        bm_DMACopyFromBuf32;
 282     APTR        bm_CopyFromBuf;
 283     APTR        bm_DMACopyToBuf32;
 284     APTR        bm_CopyToBuf;
 285     APTR        bm_PacketFilter;
 286     struct List bm_RXQueue;               /* read requests */
 287 };
 288
 289 /* Multicast address range record - private
 290 */
 291 struct MulticastAddressRange
 292 {
 293     struct Node mar_Node;                 /* 0 list node */
 294     ULONG       mar_UseCount;             /* 8 number of times used */
 295     UBYTE       mar_LowerAddr[ETHER_ADDR_SIZE]; /* 12 multicast address lower bound */
 296     UBYTE       mar_UpperAddr[ETHER_ADDR_SIZE]; /* 18 multicast address upper bound */
 297 };
 298
 299 struct PacketTypeStats
 300 {
 301     struct Node pts_Node;
 302     ULONG       pts_PacketType;
 303     struct Sana2PacketTypeStats pts_Stats;
 304 };
 305
 306
 307 struct NepEthDevBase
 308 {
 309     struct Library      np_Library;       /* standard */
 310     UWORD               np_Flags;         /* various flags */
 311
 312     struct Library     *np_SysBase;       /* cached execbase */
 313     BPTR                np_SegList;       /* device seglist */
 314     struct NepEthBase  *np_ClsBase;       /* pointer to class base */
 315     struct Library     *np_UtilityBase;   /* cached utilitybase */
 316 };
 317
 318 struct NepClassEth
 319 {
 320     struct Unit         ncp_Unit;         /* Unit structure */
 321     ULONG               ncp_UnitNo;       /* Unit number */
 322     ULONG               ncp_OpenFlags;    /* Flags used to open the device */
 323     struct NepEthBase  *ncp_ClsBase;      /* Up linkage */
 324     struct NepEthDevBase *ncp_DevBase;    /* Device base */
 325     struct Library     *ncp_Base;         /* Poseidon base */
 326     struct PsdDevice   *ncp_Device;       /* Up linkage */
 327     struct PsdConfig   *ncp_Config;       /* Up linkage */
 328     struct PsdInterface *ncp_Interface;   /* Up linkage */
 329     struct Task        *ncp_ReadySigTask; /* Task to send ready signal to */
 330     LONG                ncp_ReadySignal;  /* Signal to send when ready */
 331     struct Task        *ncp_Task;         /* Subtask */
 332     struct MsgPort     *ncp_TaskMsgPort;  /* Message Port of Subtask */
 333
 334     struct PsdPipe     *ncp_EP0Pipe;      /* Endpoint 0 pipe */
 335     struct PsdEndpoint *ncp_EPOut;        /* Endpoint 1 */
 336     struct PsdPipe     *ncp_EPOutPipe[2]; /* Endpoint 1 pipes */
 337     IPTR                ncp_EPOutMaxPktSize; /* Endpoint 1 max pkt size */
 338     struct PsdEndpoint *ncp_EPIn;         /* Endpoint 2 */
 339     struct PsdPipe     *ncp_EPInPipe;     /* Endpoint 2 pipe */
 340     struct MsgPort     *ncp_DevMsgPort;   /* Message Port for IOParReq */
 341     UWORD               ncp_UnitProdID;   /* ProductID of unit */
 342     UWORD               ncp_UnitVendorID; /* VendorID of unit */
 343     //BOOL                ncp_DenyRequests; /* Do not accept further IO requests */
 344
 345     struct List         ncp_BufManList;   /* Buffer Managers */
 346     struct List         ncp_EventList;    /* List for DoEvent */
 347     struct List         ncp_TrackList;    /* List of trackables */
 348     struct List         ncp_Multicasts;   /* List of multicast addresses */
 349     ULONG               ncp_PatchFlags;   /* Patchflags */
 350     UBYTE               ncp_MacAddress[ETHER_ADDR_SIZE]; /* Current Mac Address */
 351     UBYTE               ncp_ROMAddress[ETHER_ADDR_SIZE]; /* ROM Mac Address */
 352     UBYTE               ncp_EthCtrl[4];   /* shadow of the control registers (one byte padding) */
 353     ULONG               ncp_PhyID;        /* ID of the PHY */
 354     UWORD               ncp_PhyMode;
 355     UWORD               ncp_LedMode;
 356
 357
 358     UBYTE               ncp_MulticastArray[8]; /* array for the multicast hashes */
 359     ULONG               ncp_StateFlags;   /* State of the unit */
 360
 361     ULONG               ncp_Retries;      /* tx collision count */
 362     ULONG               ncp_BadMulticasts; /* bad multicast count */
 363
 364     UBYTE              *ncp_ReadBuffer[2]; /* Packet Double Buffered Read Buffer */
 365     UBYTE              *ncp_WriteBuffer[2]; /* Packet Write Buffer */
 366
 367     UWORD               ncp_ReadBufNum;   /* Next Read Buffer to use */
 368     UWORD               ncp_WriteBufNum;  /* Next Write Buffer to use */
 369
 370     struct Sana2DeviceStats ncp_DeviceStats; /* SANA Stats */
 371     struct Sana2PacketTypeStats *ncp_TypeStats2048; /* IP protocol stats ptr, or NULL */
 372     struct Sana2PacketTypeStats *ncp_TypeStats2054; /* ARP protocol stats ptr, or NULL */
 373
 374     UBYTE              *ncp_ReadPending;  /* read IORequest pending */
 375     struct IOSana2Req  *ncp_WritePending[2]; /* write IORequest pending */
 376     struct List         ncp_OrphanQueue;  /* List of orphan read requests */
 377     struct List         ncp_WriteQueue;   /* List of write requests */
 378
 379     UBYTE               ncp_DevIDString[128];  /* Device ID String */
 380
 381     BOOL                ncp_UsingDefaultCfg;
 382     struct ClsDevCfg   *ncp_CDC;
 383
 384     struct Library     *ncp_MUIBase;      /* MUI master base */
 385     struct Library     *ncp_PsdBase;      /* Poseidon base */
 386     struct Library     *ncp_IntBase;      /* Intuition base */
 387     struct Task        *ncp_GUITask;      /* GUI Task */
 388     struct NepClassHid *ncp_GUIBinding;   /* Window of binding that's open */
 389
 390     Object             *ncp_App;
 391     Object             *ncp_MainWindow;
 392
 393     Object             *ncp_UnitObj;
 394     Object             *ncp_MediaTypeObj;
 395
 396     Object             *ncp_UseObj;
 397     Object             *ncp_SetDefaultObj;
 398     Object             *ncp_CloseObj;
 399
 400     Object             *ncp_AboutMI;
 401     Object             *ncp_UseMI;
 402     Object             *ncp_SetDefaultMI;
 403     Object             *ncp_MUIPrefsMI;
 404
 405 };
 406
 407 struct NepEthBase
 408 {
 409     struct Library      nh_Library;       /* standard */
 410     UWORD               nh_Flags;         /* various flags */
 411
 412     struct Library     *nh_UtilityBase;   /* utility base */
 413
 414     struct NepEthDevBase *nh_DevBase;     /* base of device created */
 415     struct List         nh_Units;         /* List of units available */
 416
 417     struct NepClassEth  nh_DummyNCP;      /* Dummy ncp for default config */
 418 };
 419
 420
 421 #endif /* ASIXETH_H */