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grub2: bring back build of aros-side grub2 tools
[AROS.git] / rom / usb / pciusb / uhwcmd.c
blobfa22b4e0ec57e4054e9a6ebaa35c13dae232cb20
1 /* uhwcmd.c - pciusb.device by Chris Hodges
2 */
3
4 #include <devices/usb_hub.h>
5 #include <proto/utility.h>
6 #include <proto/exec.h>
7 #include <proto/timer.h>
8
9 #include <strings.h>
10
11 #include "uhwcmd.h"
12 #include "ohciproto.h"
13
14 #define NewList NEWLIST
15
16 /* we cannot use AROS_WORD2LE in struct initializer */
17 #if AROS_BIG_ENDIAN
18 #define WORD2LE(w) (UWORD)(((w) >> 8) & 0x00FF) | (((w) << 8) & 0xFF00)
19 #else
20 #define WORD2LE(w) (w)
21 #endif
22
23 /* Root hub data */
24 const struct UsbStdDevDesc RHDevDesc = { sizeof(struct UsbStdDevDesc), UDT_DEVICE, WORD2LE(0x0110), HUB_CLASSCODE, 0, 0, 8, WORD2LE(0x0000), WORD2LE(0x0000), WORD2LE(0x0100), 1, 2, 0, 1 };
25
26 const struct UsbStdCfgDesc RHCfgDesc = { 9, UDT_CONFIGURATION, WORD2LE(9+9+7), 1, 1, 3, USCAF_ONE|USCAF_SELF_POWERED, 0 };
27 const struct UsbStdIfDesc RHIfDesc = { 9, UDT_INTERFACE, 0, 0, 1, HUB_CLASSCODE, 0, 0, 4 };
28 const struct UsbStdEPDesc RHEPDesc = { 7, UDT_ENDPOINT, URTF_IN|1, USEAF_INTERRUPT, WORD2LE(8), 255 };
29 const struct UsbHubDesc RHHubDesc = { 9, // 0 Number of bytes in this descriptor, including this byte
30 UDT_HUB, // 1 Descriptor Type, value: 29H for hub descriptor
31 0, // 2 Number of downstream facing ports that this hub supports
32 WORD2LE(UHCF_INDIVID_POWER|UHCF_INDIVID_OVP), // 3 wHubCharacteristics
33 0, // 5 bPwrOn2PwrGood
34 1, // 6 bHubContrCurrent
35 1, // 7 DeviceRemovable (size is variable)
36 0 // x PortPwrCtrlMask (size is variable)
37 };
38
39 const CONST_STRPTR RHStrings[] = { "Chris Hodges", "PCI Root Hub Unit x", "Standard Config", "Hub interface" };
40
41 /* /// "SureCause()" */
42 void SureCause(struct PCIDevice *base, struct Interrupt *interrupt)
43 {
44 /* this is a workaround for the original Cause() function missing tailed calls */
45 Disable();
46
47 if((interrupt->is_Node.ln_Type == NT_SOFTINT) || (interrupt->is_Node.ln_Type == NT_USER))
48 {
49 // signal tailed call
50 interrupt->is_Node.ln_Type = NT_USER;
51 } else {
52 do
53 {
54 interrupt->is_Node.ln_Type = NT_SOFTINT;
55 Forbid(); // make sure code is not interrupted by other tasks
56 Enable();
57 AROS_INTC1(interrupt->is_Code, interrupt->is_Data);
58 Disable();
59 Permit();
60 } while(interrupt->is_Node.ln_Type != NT_SOFTINT);
61 interrupt->is_Node.ln_Type = NT_INTERRUPT;
62 }
63 Enable();
64 }
65 /* \\\ */
66
67 /* /// "uhwOpenTimer()" */
68 BOOL uhwOpenTimer(struct PCIUnit *unit, struct PCIDevice *base)
69 {
70 if((unit->hu_MsgPort = CreateMsgPort()))
71 {
72 if((unit->hu_TimerReq = (struct timerequest *) CreateIORequest(unit->hu_MsgPort, sizeof(struct timerequest))))
73 {
74 if(!OpenDevice("timer.device", UNIT_MICROHZ, (struct IORequest *) unit->hu_TimerReq, 0))
75 {
76 unit->hu_TimerReq->tr_node.io_Message.mn_Node.ln_Name = "PCI hardware";
77 unit->hu_TimerReq->tr_node.io_Command = TR_ADDREQUEST;
78 KPRINTF(1, ("opened timer device\n"));
79 return(TRUE);
80 }
81 DeleteIORequest((struct IORequest *) unit->hu_TimerReq);
82 unit->hu_TimerReq = NULL;
83 }
84 DeleteMsgPort(unit->hu_MsgPort);
85 unit->hu_MsgPort = NULL;
86 }
87 KPRINTF(5, ("failed to open timer.device\n"));
88 return(FALSE);
89 }
90 /* \\\ */
91
92 /* /// "uhwDelayMS()" */
93 void uhwDelayMS(ULONG milli, struct PCIUnit *unit)
94 {
95 unit->hu_TimerReq->tr_time.tv_secs = 0;
96 unit->hu_TimerReq->tr_time.tv_micro = milli * 1000;
97 DoIO((struct IORequest *) unit->hu_TimerReq);
98 }
99 /* \\\ */
100
101 /* /// "uhwDelayMicro()" */
102 void uhwDelayMicro(ULONG micro, struct PCIUnit *unit)
103 {
104 unit->hu_TimerReq->tr_time.tv_secs = 0;
105 unit->hu_TimerReq->tr_time.tv_micro = micro;
106 DoIO((struct IORequest *) unit->hu_TimerReq);
107 }
108 /* \\\ */
109
110 /* /// "uhwCloseTimer()" */
111 void uhwCloseTimer(struct PCIUnit *unit, struct PCIDevice *base)
112 {
113 if(unit->hu_MsgPort)
114 {
115 if(unit->hu_TimerReq)
116 {
117 KPRINTF(1, ("closing timer.device\n"));
118 CloseDevice((APTR) unit->hu_TimerReq);
119 DeleteIORequest((struct IORequest *) unit->hu_TimerReq);
120 unit->hu_TimerReq = NULL;
121 }
122 DeleteMsgPort(unit->hu_MsgPort);
123 unit->hu_MsgPort = NULL;
124 }
125 }
126 /* \\\ */
127
128 /* /// "Open_Unit()" */
129 struct Unit * Open_Unit(struct IOUsbHWReq *ioreq,
130 LONG unitnr,
131 struct PCIDevice *base)
132 {
133 struct PCIUnit *unit = NULL;
134
135 if(!base->hd_ScanDone)
136 {
137 base->hd_ScanDone = TRUE;
138 if(!pciInit(base))
139 {
140 return NULL;
141 }
142 }
143 unit = (struct PCIUnit *) base->hd_Units.lh_Head;
144 while(((struct Node *) unit)->ln_Succ)
145 {
146 if(unit->hu_UnitNo == unitnr)
147 {
148 break;
149 }
150 unit = (struct PCIUnit *) ((struct Node *) unit)->ln_Succ;
151 }
152 if(!((struct Node *) unit)->ln_Succ)
153 {
154 KPRINTF(20, ("Unit %ld does not exist!\n", unitnr));
155 return NULL;
156 }
157 if(unit->hu_UnitAllocated)
158 {
159 ioreq->iouh_Req.io_Error = IOERR_UNITBUSY;
160 KPRINTF(5, ("Unit %ld already open!\n", unitnr));
161 return NULL;
162 }
163
164 if(uhwOpenTimer(unit, base))
165 {
166
167 if(pciAllocUnit(unit)) // hardware self test
168 {
169 unit->hu_UnitAllocated = TRUE;
170 unit->hu_NakTimeoutInt.is_Node.ln_Type = NT_INTERRUPT;
171 unit->hu_NakTimeoutInt.is_Node.ln_Name = "PCI NakTimeout";
172 unit->hu_NakTimeoutInt.is_Node.ln_Pri = -16;
173 unit->hu_NakTimeoutInt.is_Data = unit;
174 unit->hu_NakTimeoutInt.is_Code = (VOID_FUNC)uhwNakTimeoutInt;
175
176 CopyMem(unit->hu_TimerReq, &unit->hu_NakTimeoutReq, sizeof(struct timerequest));
177 unit->hu_NakTimeoutReq.tr_node.io_Message.mn_ReplyPort = &unit->hu_NakTimeoutMsgPort;
178 unit->hu_NakTimeoutMsgPort.mp_Node.ln_Type = NT_MSGPORT;
179 unit->hu_NakTimeoutMsgPort.mp_Flags = PA_SOFTINT;
180 unit->hu_NakTimeoutMsgPort.mp_SigTask = &unit->hu_NakTimeoutInt;
181 NewList(&unit->hu_NakTimeoutMsgPort.mp_MsgList);
182 Cause(&unit->hu_NakTimeoutInt);
183 return(&unit->hu_Unit);
184 } else {
185 ioreq->iouh_Req.io_Error = IOERR_SELFTEST;
186 KPRINTF(20, ("Hardware allocation failure!\n"));
187 }
188 uhwCloseTimer(unit, base);
189 }
190 return(NULL);
191 }
192 /* \\\ */
193
194 /* /// "Close_Unit()" */
195 void Close_Unit(struct PCIDevice *base,
196 struct PCIUnit *unit,
197 struct IOUsbHWReq *ioreq)
198 {
199 /* Disable all interrupts */
200 unit->hu_NakTimeoutMsgPort.mp_Flags = PA_IGNORE;
201 unit->hu_NakTimeoutInt.is_Node.ln_Type = NT_SOFTINT;
202 AbortIO((APTR) &unit->hu_NakTimeoutReq);
203
204 pciFreeUnit(unit);
205
206 uhwCloseTimer(unit, base);
207 unit->hu_UnitAllocated = FALSE;
208 }
209 /* \\\ */
210
211 /* /// "uhwGetUsbState()" */
212 UWORD uhwGetUsbState(struct IOUsbHWReq *ioreq,
213 struct PCIUnit *unit,
214 struct PCIDevice *base)
215 {
216 return(ioreq->iouh_State = UHSF_OPERATIONAL);
217 }
218 /* \\\ */
219
220 /* /// "cmdReset()" */
221 /*
222 *======================================================================
223 * cmdReset(ioreq, unit, base)
224 *======================================================================
225 *
226 * This is the device CMD_RESET routine.
227 *
228 * Resets the whole USB hardware. Goes into USBOperational mode right
229 * after. Must NOT be called from an interrupt.
230 *
231 */
232
233 WORD cmdReset(struct IOUsbHWReq *ioreq,
234 struct PCIUnit *unit,
235 struct PCIDevice *base)
236 {
237 KPRINTF(10, ("CMD_RESET ioreq: 0x%p\n", ioreq));
238
239 uhwDelayMS(1, unit);
240 uhwGetUsbState(ioreq, unit, base);
241
242 if(ioreq->iouh_State & UHSF_OPERATIONAL)
243 {
244 return RC_OK;
245 }
246 return UHIOERR_USBOFFLINE;
247 }
248 /* \\\ */
249
250 /* /// "cmdUsbReset()" */
251 /*
252 *======================================================================
253 * cmdUsbReset(ioreq, unit, base)
254 *======================================================================
255 *
256 * This is the device UHCMD_USBRESET routine.
257 *
258 * Resets the USB bus. Goes into USBOperational mode right after. Must
259 * NOT be called from an interrupt.
260 *
261 */
262
263 WORD cmdUsbReset(struct IOUsbHWReq *ioreq,
264 struct PCIUnit *unit,
265 struct PCIDevice *base)
266 {
267 KPRINTF(10, ("UHCMD_USBRESET ioreq: 0x%p\n", ioreq));
268
269 /* FIXME */
270 uhwGetUsbState(ioreq, unit, base);
271
272 unit->hu_FrameCounter = 1;
273 unit->hu_RootHubAddr = 0;
274
275 if(ioreq->iouh_State & UHSF_OPERATIONAL)
276 {
277 return RC_OK;
278 }
279 return UHIOERR_USBOFFLINE;
280 }
281 /* \\\ */
282
283 /* /// "cmdUsbResume()" */
284 /*
285 *======================================================================
286 * cmdUsbResume(ioreq, unit, base)
287 *======================================================================
288 *
289 * This is the device UHCMD_USBRESUME routine.
290 *
291 * Tries to resume from USBSuspend mode into USBOperational.
292 * Must NOT be called from an interrupt.
293 *
294 */
295
296 WORD cmdUsbResume(struct IOUsbHWReq *ioreq,
297 struct PCIUnit *unit,
298 struct PCIDevice *base)
299 {
300 KPRINTF(10, ("UHCMD_USBRESUME ioreq: 0x%p\n", ioreq));
301
302 /* FIXME */
303 uhwGetUsbState(ioreq, unit, base);
304 if(ioreq->iouh_State & UHSF_OPERATIONAL)
305 {
306 return RC_OK;
307 }
308 return UHIOERR_USBOFFLINE;
309 }
310 /* \\\ */
311
312 /* /// "cmdUsbSuspend()" */
313 /*
314 *======================================================================
315 * cmdUsbSuspend(ioreq, unit, base)
316 *======================================================================
317 *
318 * This is the device UHCMD_USBSUSPEND routine.
319 *
320 * Sets the USB into USBSuspend mode.
321 * Must NOT be called from an interrupt.
322 *
323 */
324
325 WORD cmdUsbSuspend(struct IOUsbHWReq *ioreq,
326 struct PCIUnit *unit,
327 struct PCIDevice *base)
328 {
329 KPRINTF(10, ("UHCMD_USBSUSPEND ioreq: 0x%p\n", ioreq));
330
331 /* FIXME */
332 uhwGetUsbState(ioreq, unit, base);
333 if(ioreq->iouh_State & UHSF_SUSPENDED)
334 {
335 return RC_OK;
336 }
337 return UHIOERR_USBOFFLINE;
338 }
339 /* \\\ */
340
341 /* /// "cmdUsbOper()" */
342 /*
343 *======================================================================
344 * cmdUsbOper(ioreq, unit, base)
345 *======================================================================
346 *
347 * This is the device UHCMD_USBOPER routine.
348 *
349 * Sets the USB into USBOperational mode.
350 * Must NOT be called from an interrupt.
351 *
352 */
353
354 WORD cmdUsbOper(struct IOUsbHWReq *ioreq,
355 struct PCIUnit *unit,
356 struct PCIDevice *base)
357 {
358 KPRINTF(10, ("UHCMD_USBOPER ioreq: 0x%p\n", ioreq));
359
360 /* FIXME */
361 uhwGetUsbState(ioreq, unit, base);
362 if(ioreq->iouh_State & UHSF_OPERATIONAL)
363 {
364 return RC_OK;
365 }
366 return UHIOERR_USBOFFLINE;
367 }
368 /* \\\ */
369
370 /* /// "cmdQueryDevice()" */
371 /*
372 *======================================================================
373 * cmdQueryDevice(ioreq, unit, base)
374 *======================================================================
375 *
376 * This is the device UHCMD_QUERYDEVICE routine.
377 *
378 * Returns information about the hardware.
379 *
380 */
381
382 WORD cmdQueryDevice(struct IOUsbHWReq *ioreq,
383 struct PCIUnit *unit,
384 struct PCIDevice *base)
385 {
386 struct TagItem *taglist = (struct TagItem *) ioreq->iouh_Data;
387 struct TagItem *tag;
388 ULONG count = 0;
389
390 KPRINTF(10, ("UHCMD_QUERYDEVICE ioreq: 0x%p, taglist: 0x%p\n", ioreq, taglist));
391
392 if((tag = FindTagItem(UHA_State, taglist)))
393 {
394 *((ULONG *) tag->ti_Data) = (ULONG) uhwGetUsbState(ioreq, unit, base);
395 count++;
396 }
397 if((tag = FindTagItem(UHA_Manufacturer, taglist)))
398 {
399 *((STRPTR *) tag->ti_Data) = "Chris Hodges";
400 count++;
401 }
402 if((tag = FindTagItem(UHA_ProductName, taglist)))
403 {
404 *((STRPTR *) tag->ti_Data) = unit->hu_ProductName;
405 count++;
406 }
407 if((tag = FindTagItem(UHA_Description, taglist)))
408 {
409 *((STRPTR *) tag->ti_Data) = "Generic adaptive host controller driver for PCI cards";
410 count++;
411 }
412 if((tag = FindTagItem(UHA_Copyright, taglist)))
413 {
414 *((STRPTR *) tag->ti_Data) ="©2007-2009 Chris Hodges";
415 count++;
416 }
417 if((tag = FindTagItem(UHA_Version, taglist)))
418 {
419 *((ULONG *) tag->ti_Data) = VERSION_NUMBER;
420 count++;
421 }
422 if((tag = FindTagItem(UHA_Revision, taglist)))
423 {
424 *((ULONG *) tag->ti_Data) = REVISION_NUMBER;
425 count++;
426 }
427 if((tag = FindTagItem(UHA_DriverVersion, taglist)))
428 {
429 *((ULONG *) tag->ti_Data) = 0x220;
430 count++;
431 }
432 if((tag = FindTagItem(UHA_Capabilities, taglist)))
433 {
434 *((ULONG *) tag->ti_Data) = UHCF_USB20;
435 count++;
436 }
437 ioreq->iouh_Actual = count;
438 return RC_OK;
439 }
440 /* \\\ */
441
442 /* /// "cmdControlXFerRootHub()" */
443 WORD cmdControlXFerRootHub(struct IOUsbHWReq *ioreq,
444 struct PCIUnit *unit,
445 struct PCIDevice *base)
446 {
447 struct PCIController *hc;
448 struct PCIController *chc;
449 UWORD rt = ioreq->iouh_SetupData.bmRequestType;
450 UWORD req = ioreq->iouh_SetupData.bRequest;
451 UWORD idx = AROS_WORD2LE(ioreq->iouh_SetupData.wIndex);
452 UWORD val = AROS_WORD2LE(ioreq->iouh_SetupData.wValue);
453 UWORD len = AROS_WORD2LE(ioreq->iouh_SetupData.wLength);
454 UWORD hciport;
455 ULONG numports = unit->hu_RootHubPorts;
456 BOOL cmdgood;
457 ULONG cnt;
458
459 if(ioreq->iouh_Endpoint)
460 {
461 return(UHIOERR_STALL);
462 }
463
464 if(len != ioreq->iouh_Length)
465 {
466 KPRINTF(20, ("RH: Len (%ld != %ld) mismatch!\n", len != ioreq->iouh_Length));
467 return(UHIOERR_STALL);
468 }
469 switch(rt)
470 {
471 case (URTF_STANDARD|URTF_DEVICE):
472 switch(req)
473 {
474 case USR_SET_ADDRESS:
475 KPRINTF(1, ("RH: SetAddress = %ld\n", val));
476 unit->hu_RootHubAddr = val;
477 ioreq->iouh_Actual = len;
478 return(0);
479
480 case USR_SET_CONFIGURATION:
481 KPRINTF(1, ("RH: SetConfiguration=%ld\n", val));
482 ioreq->iouh_Actual = len;
483 return(0);
484 }
485 break;
486
487 case (URTF_IN|URTF_STANDARD|URTF_DEVICE):
488 switch(req)
489 {
490 case USR_GET_DESCRIPTOR:
491 switch(val>>8)
492 {
493 case UDT_DEVICE:
494 KPRINTF(1, ("RH: GetDeviceDescriptor (%ld)\n", len));
495 ioreq->iouh_Actual = (len > sizeof(struct UsbStdDevDesc)) ? sizeof(struct UsbStdDevDesc) : len;
496 CopyMem((APTR) &RHDevDesc, ioreq->iouh_Data, ioreq->iouh_Actual);
497 if(ioreq->iouh_Length >= sizeof(struct UsbStdDevDesc))
498 {
499 if(unit->hu_RootHub20Ports)
500 {
501 struct UsbStdDevDesc *usdd = (struct UsbStdDevDesc *) ioreq->iouh_Data;
502 usdd->bcdUSB = AROS_WORD2LE(0x0200); // signal a highspeed root hub
503 usdd->bDeviceProtocol = 1; // single TT
504 }
505
506 }
507 return(0);
508
509 case UDT_CONFIGURATION:
510 {
511 UBYTE tmpbuf[9+9+7];
512 KPRINTF(1, ("RH: GetConfigDescriptor (%ld)\n", len));
513 CopyMem((APTR) &RHCfgDesc, tmpbuf, 9);
514 CopyMem((APTR) &RHIfDesc, &tmpbuf[9], 9);
515 CopyMem((APTR) &RHEPDesc, &tmpbuf[9+9], 7);
516 if(unit->hu_RootHub20Ports)
517 {
518 struct UsbStdEPDesc *usepd = (struct UsbStdEPDesc *) &tmpbuf[9+9];
519 usepd->bInterval = 12; // 2048 µFrames
520 }
521 ioreq->iouh_Actual = (len > 9+9+7) ? 9+9+7 : len;
522 CopyMem(tmpbuf, ioreq->iouh_Data, ioreq->iouh_Actual);
523 return(0);
524 }
525
526 case UDT_STRING:
527 if(val & 0xff) /* get lang array */
528 {
529 CONST_STRPTR source = NULL;
530 UWORD *mptr = ioreq->iouh_Data;
531 UWORD slen = 1;
532 KPRINTF(1, ("RH: GetString %04lx (%ld)\n", val, len));
533 if((val & 0xff) > 4) /* index too high? */
534 {
535 return(UHIOERR_STALL);
536 }
537 source = RHStrings[(val & 0xff)-1];
538 if(len > 1)
539 {
540 ioreq->iouh_Actual = 2;
541 while(*source++)
542 {
543 slen++;
544 }
545 source = RHStrings[(val & 0xff)-1];
546 *mptr++ = AROS_WORD2BE((slen<<9)|UDT_STRING);
547 while(ioreq->iouh_Actual+1 < len)
548 {
549 // special hack for unit number in root hub string
550 if(((val & 0xff) == 2) && (source[1] == 0))
551 {
552 *mptr++ = AROS_WORD2LE('0' + unit->hu_UnitNo);
553 } else {
554 *mptr++ = AROS_WORD2LE(*source);
555 }
556 source++;
557 ioreq->iouh_Actual += 2;
558 if(!(*source))
559 {
560 break;
561 }
562 }
563 }
564 } else {
565 UWORD *mptr = ioreq->iouh_Data;
566 KPRINTF(1, ("RH: GetLangArray %04lx (%ld)\n", val, len));
567 if(len > 1)
568 {
569 ioreq->iouh_Actual = 2;
570 mptr[0] = AROS_WORD2BE((4<<8)|UDT_STRING);
571 if(len > 3)
572 {
573 ioreq->iouh_Actual += 2;
574 mptr[1] = AROS_WORD2LE(0x0409);
575 }
576 }
577 }
578 return(0);
579
580 default:
581 KPRINTF(1, ("RH: Unsupported Descriptor %04lx\n", idx));
582 }
583 break;
584
585 case USR_GET_CONFIGURATION:
586 if(len == 1)
587 {
588 KPRINTF(1, ("RH: GetConfiguration\n"));
589 ((UBYTE *) ioreq->iouh_Data)[0] = 1;
590 ioreq->iouh_Actual = len;
591 return(0);
592 }
593 break;
594 }
595 break;
596
597 case (URTF_CLASS|URTF_OTHER):
598 switch(req)
599 {
600 case USR_SET_FEATURE:
601 if((!idx) || (idx > numports))
602 {
603 KPRINTF(20, ("Port %ld out of range\n", idx));
604 return(UHIOERR_STALL);
605 }
606 chc = unit->hu_PortMap11[idx - 1];
607 if(unit->hu_EhciOwned[idx - 1])
608 {
609 hc = unit->hu_PortMap20[idx - 1];
610 hciport = idx - 1;
611 } else {
612 hc = chc;
613 hciport = unit->hu_PortNum11[idx - 1];
614 }
615 KPRINTF(10, ("Set Feature %ld maps from glob. Port %ld to local Port %ld (%s)\n", val, idx, hciport, unit->hu_EhciOwned[idx - 1] ? "EHCI" : "U/OHCI"));
616 cmdgood = FALSE;
617 switch(hc->hc_HCIType)
618 {
619 case HCITYPE_UHCI:
620 {
621 UWORD portreg = hciport ? UHCI_PORT2STSCTRL : UHCI_PORT1STSCTRL;
622 ULONG oldval = READIO16_LE(hc->hc_RegBase, portreg) & ~(UHPF_ENABLECHANGE|UHPF_CONNECTCHANGE); // these are clear-on-write!
623 ULONG newval = oldval;
624 switch(val)
625 {
626 /* case UFS_PORT_CONNECTION: not possible */
627 case UFS_PORT_ENABLE:
628 KPRINTF(10, ("UHCI: Enabling Port (%s)\n", newval & UHPF_PORTENABLE ? "already" : "ok"));
629 newval |= UHPF_PORTENABLE;
630 cmdgood = TRUE;
631 break;
632
633 case UFS_PORT_SUSPEND:
634 newval |= UHPF_PORTSUSPEND;
635 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_SUSPEND; // manually fake suspend change
636 cmdgood = TRUE;
637 break;
638
639 /* case UFS_PORT_OVER_CURRENT: not possible */
640 case UFS_PORT_RESET:
641 KPRINTF(10, ("UHCI: Resetting Port (%s)\n", newval & UHPF_PORTRESET ? "already" : "ok"));
642
643 // this is an ugly blocking workaround to the inability of UHCI to clear reset automatically
644 newval &= ~(UHPF_PORTSUSPEND|UHPF_PORTENABLE);
645 newval |= UHPF_PORTRESET;
646 WRITEIO16_LE(hc->hc_RegBase, portreg, newval);
647 uhwDelayMS(25, unit);
648 newval = READIO16_LE(hc->hc_RegBase, portreg) & ~(UHPF_ENABLECHANGE|UHPF_CONNECTCHANGE|UHPF_PORTSUSPEND|UHPF_PORTENABLE);
649 KPRINTF(10, ("UHCI: Reset=%s\n", newval & UHPF_PORTRESET ? "GOOD" : "BAD!"));
650 // like windows does it
651 newval &= ~UHPF_PORTRESET;
652 WRITEIO16_LE(hc->hc_RegBase, portreg, newval);
653 uhwDelayMicro(50, unit);
654 newval = READIO16_LE(hc->hc_RegBase, portreg) & ~(UHPF_ENABLECHANGE|UHPF_CONNECTCHANGE|UHPF_PORTSUSPEND);
655 KPRINTF(10, ("UHCI: Reset=%s\n", newval & UHPF_PORTRESET ? "BAD!" : "GOOD"));
656 newval &= ~(UHPF_PORTSUSPEND|UHPF_PORTRESET);
657 newval |= UHPF_PORTENABLE;
658 WRITEIO16_LE(hc->hc_RegBase, portreg, newval);
659 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_RESET|UPSF_PORT_ENABLE; // manually fake reset change
660
661 cnt = 100;
662 do
663 {
664 uhwDelayMS(1, unit);
665 newval = READIO16_LE(hc->hc_RegBase, portreg);
666 } while(--cnt && (!(newval & UHPF_PORTENABLE)));
667 if(cnt)
668 {
669 KPRINTF(10, ("UHCI: Enabled after %ld ticks\n", 100-cnt));
670 } else {
671 KPRINTF(20, ("UHCI: Port refuses to be enabled!\n"));
672 return(UHIOERR_HOSTERROR);
673 }
674 // make enumeration possible
675 unit->hu_DevControllers[0] = hc;
676 cmdgood = TRUE;
677 break;
678
679 case UFS_PORT_POWER:
680 KPRINTF(10, ("UHCI: Powering Port\n"));
681 // ignore for UHCI, is always powered
682 cmdgood = TRUE;
683 break;
684
685 /* case UFS_PORT_LOW_SPEED: not possible */
686 /* case UFS_C_PORT_CONNECTION:
687 case UFS_C_PORT_ENABLE:
688 case UFS_C_PORT_SUSPEND:
689 case UFS_C_PORT_OVER_CURRENT:
690 case UFS_C_PORT_RESET: */
691 }
692 if(cmdgood)
693 {
694 KPRINTF(5, ("UHCI: Port %ld SET_FEATURE %04lx->%04lx\n", idx, oldval, newval));
695 WRITEIO16_LE(hc->hc_RegBase, portreg, newval);
696 return(0);
697 }
698 break;
699 }
700
701 case HCITYPE_OHCI:
702 {
703 UWORD portreg = OHCI_PORTSTATUS + (hciport<<2);
704 ULONG oldval = READREG32_LE(hc->hc_RegBase, portreg);
705
706 switch(val)
707 {
708 /* case UFS_PORT_CONNECTION: not possible */
709 case UFS_PORT_ENABLE:
710 KPRINTF(10, ("OHCI: Enabling Port (%s)\n", oldval & OHPF_PORTENABLE ? "already" : "ok"));
711 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTENABLE);
712 cmdgood = TRUE;
713 break;
714
715 case UFS_PORT_SUSPEND:
716 KPRINTF(10, ("OHCI: Suspending Port (%s)\n", oldval & OHPF_PORTSUSPEND ? "already" : "ok"));
717 //hc->hc_PortChangeMap[hciport] |= UPSF_PORT_SUSPEND; // manually fake suspend change
718 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTSUSPEND);
719 cmdgood = TRUE;
720 break;
721
722 /* case UFS_PORT_OVER_CURRENT: not possible */
723 case UFS_PORT_RESET:
724 KPRINTF(10, ("OHCI: Resetting Port (%s)\n", oldval & OHPF_PORTRESET ? "already" : "ok"));
725 // make sure we have at least 50ms of reset time here, as required for a root hub port
726 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTRESET);
727 uhwDelayMS(10, unit);
728 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTRESET);
729 uhwDelayMS(10, unit);
730 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTRESET);
731 uhwDelayMS(10, unit);
732 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTRESET);
733 uhwDelayMS(10, unit);
734 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTRESET);
735 uhwDelayMS(15, unit);
736 oldval = READREG32_LE(hc->hc_RegBase, portreg);
737 KPRINTF(10, ("OHCI: Reset release (%s %s)\n", oldval & OHPF_PORTRESET ? "didn't turn off" : "okay",
738 oldval & OHPF_PORTENABLE ? "enabled" : "not enabled"));
739 if(oldval & OHPF_PORTRESET)
740 {
741 uhwDelayMS(40, unit);
742 oldval = READREG32_LE(hc->hc_RegBase, portreg);
743 KPRINTF(10, ("OHCI: Reset 2nd release (%s %s)\n", oldval & OHPF_PORTRESET ? "didn't turn off" : "okay",
744 oldval & OHPF_PORTENABLE ? "enabled" : "still not enabled"));
745 }
746 // make enumeration possible
747 unit->hu_DevControllers[0] = hc;
748 cmdgood = TRUE;
749 break;
750
751 case UFS_PORT_POWER:
752 KPRINTF(10, ("OHCI: Powering Port (%s)\n", oldval & OHPF_PORTPOWER ? "already" : "ok"));
753 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTPOWER);
754 cmdgood = TRUE;
755 break;
756
757 /* case UFS_PORT_LOW_SPEED: not possible */
758 /* case UFS_C_PORT_CONNECTION:
759 case UFS_C_PORT_ENABLE:
760 case UFS_C_PORT_SUSPEND:
761 case UFS_C_PORT_OVER_CURRENT:
762 case UFS_C_PORT_RESET: */
763 }
764 if(cmdgood)
765 {
766 return(0);
767 }
768 break;
769 }
770
771 case HCITYPE_EHCI:
772 {
773 UWORD portreg = EHCI_PORTSC1 + (hciport<<2);
774 ULONG oldval = READREG32_LE(hc->hc_RegBase, portreg) & ~(EHPF_OVERCURRENTCHG|EHPF_ENABLECHANGE|EHPF_CONNECTCHANGE); // these are clear-on-write!
775 ULONG newval = oldval;
776 switch(val)
777 {
778 /* case UFS_PORT_CONNECTION: not possible */
779 case UFS_PORT_ENABLE:
780 KPRINTF(10, ("EHCI: Enabling Port (%s)\n", newval & EHPF_PORTENABLE ? "already" : "ok"));
781 newval |= EHPF_PORTENABLE;
782 cmdgood = TRUE;
783 break;
784
785 case UFS_PORT_SUSPEND:
786 newval |= EHPF_PORTSUSPEND;
787 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_SUSPEND; // manually fake suspend change
788 cmdgood = TRUE;
789 break;
790
791 /* case UFS_PORT_OVER_CURRENT: not possible */
792 case UFS_PORT_RESET:
793 KPRINTF(10, ("EHCI: Resetting Port (%s)\n", newval & EHPF_PORTRESET ? "already" : "ok"));
794
795 // this is an ugly blocking workaround to the inability of EHCI to clear reset automatically
796 newval &= ~(EHPF_PORTSUSPEND|EHPF_PORTENABLE);
797 newval |= EHPF_PORTRESET;
798 WRITEREG32_LE(hc->hc_RegBase, portreg, newval);
799 uhwDelayMS(50, unit);
800 newval = READREG32_LE(hc->hc_RegBase, portreg) & ~(EHPF_OVERCURRENTCHG|EHPF_ENABLECHANGE|EHPF_CONNECTCHANGE|EHPF_PORTSUSPEND|EHPF_PORTENABLE);
801 KPRINTF(10, ("EHCI: Reset=%s\n", newval & EHPF_PORTRESET ? "GOOD" : "BAD!"));
802 newval &= ~EHPF_PORTRESET;
803 WRITEREG32_LE(hc->hc_RegBase, portreg, newval);
804 uhwDelayMS(10, unit);
805 newval = READREG32_LE(hc->hc_RegBase, portreg) & ~(EHPF_OVERCURRENTCHG|EHPF_ENABLECHANGE|EHPF_CONNECTCHANGE|EHPF_PORTSUSPEND);
806 KPRINTF(10, ("EHCI: Reset=%s\n", newval & EHPF_PORTRESET ? "BAD!" : "GOOD"));
807 KPRINTF(10, ("EHCI: Highspeed=%s\n", newval & EHPF_PORTENABLE ? "YES!" : "NO"));
808 KPRINTF(10, ("EHCI: Port status=%08lx\n", newval));
809 if(!(newval & EHPF_PORTENABLE) && unit->hu_PortMap11[idx - 1] != NULL)
810 {
811 // if not highspeed, release ownership
812 KPRINTF(20, ("EHCI: Transferring ownership to UHCI/OHCI port %ld\n", unit->hu_PortNum11[idx - 1]));
813 KPRINTF(10, ("EHCI: Device is %s\n", newval & EHPF_LINESTATUS_DM ? "LOWSPEED" : "FULLSPEED"));
814 newval |= EHPF_NOTPORTOWNER;
815 if(!chc)
816 {
817 KPRINTF(20, ("EHCI has no companion controller, can't transfer ownership!\n"));
818 WRITEREG32_LE(hc->hc_RegBase, portreg, newval);
819 return(UHIOERR_HOSTERROR);
820 }
821 switch(chc->hc_HCIType)
822 {
823 case HCITYPE_UHCI:
824 {
825 UWORD uhcihciport = unit->hu_PortNum11[idx - 1];
826 UWORD uhciportreg = uhcihciport ? UHCI_PORT2STSCTRL : UHCI_PORT1STSCTRL;
827 ULONG __unused uhcinewval = READREG16_LE(chc->hc_RegBase, uhciportreg);
828
829 KPRINTF(10, ("UHCI Port status before handover=%04lx\n", uhcinewval));
830 break;
831 }
832
833 case HCITYPE_OHCI:
834 {
835 UWORD ohcihciport = unit->hu_PortNum11[idx - 1];
836 UWORD ohciportreg = OHCI_PORTSTATUS + (ohcihciport<<2);
837 ULONG __unused ohcioldval = READREG32_LE(chc->hc_RegBase, ohciportreg);
838
839 KPRINTF(10, ("OHCI: Port status before handover=%08lx\n", ohcioldval));
840 KPRINTF(10, ("OHCI: Powering Port (%s)\n", ohcioldval & OHPF_PORTPOWER ? "already" : "ok"));
841 WRITEREG32_LE(chc->hc_RegBase, ohciportreg, OHPF_PORTPOWER);
842 uhwDelayMS(10, unit);
843 KPRINTF(10, ("OHCI: Port status after handover=%08lx\n", READREG32_LE(chc->hc_RegBase, ohciportreg)));
844 break;
845 }
846 }
847 newval = READREG32_LE(hc->hc_RegBase, portreg) & ~(EHPF_OVERCURRENTCHG|EHPF_ENABLECHANGE|EHPF_CONNECTCHANGE|EHPF_PORTSUSPEND);
848 KPRINTF(10, ("EHCI: Port status (reread)=%08lx\n", newval));
849 newval |= EHPF_NOTPORTOWNER;
850 unit->hu_EhciOwned[idx - 1] = FALSE;
851 WRITEREG32_LE(hc->hc_RegBase, portreg, newval);
852 uhwDelayMS(90, unit);
853 KPRINTF(10, ("EHCI: Port status (after handover)=%08lx\n", READREG32_LE(hc->hc_RegBase, portreg) & ~(EHPF_OVERCURRENTCHG|EHPF_ENABLECHANGE|EHPF_CONNECTCHANGE|EHPF_PORTSUSPEND)));
854 // enable companion controller port
855 switch(chc->hc_HCIType)
856 {
857 case HCITYPE_UHCI:
858 {
859 UWORD uhcihciport = unit->hu_PortNum11[idx - 1];
860 UWORD uhciportreg = uhcihciport ? UHCI_PORT2STSCTRL : UHCI_PORT1STSCTRL;
861 ULONG uhcinewval;
862
863 uhcinewval = READIO16_LE(chc->hc_RegBase, uhciportreg) & ~(UHPF_ENABLECHANGE|UHPF_CONNECTCHANGE|UHPF_PORTSUSPEND);
864 KPRINTF(10, ("UHCI: Reset=%s\n", uhcinewval & UHPF_PORTRESET ? "BAD!" : "GOOD"));
865 if((uhcinewval & UHPF_PORTRESET))//|| (newval & EHPF_LINESTATUS_DM))
866 {
867 // this is an ugly blocking workaround to the inability of UHCI to clear reset automatically
868 KPRINTF(20, ("UHCI: Uhm, reset was bad!\n"));
869 uhcinewval &= ~(UHPF_PORTSUSPEND|UHPF_PORTENABLE);
870 uhcinewval |= UHPF_PORTRESET;
871 WRITEIO16_LE(chc->hc_RegBase, uhciportreg, uhcinewval);
872 uhwDelayMS(50, unit);
873 uhcinewval = READIO16_LE(chc->hc_RegBase, uhciportreg) & ~(UHPF_ENABLECHANGE|UHPF_CONNECTCHANGE|UHPF_PORTSUSPEND|UHPF_PORTENABLE);
874 KPRINTF(10, ("UHCI: ReReset=%s\n", uhcinewval & UHPF_PORTRESET ? "GOOD" : "BAD!"));
875 uhcinewval &= ~UHPF_PORTRESET;
876 WRITEIO16_LE(chc->hc_RegBase, uhciportreg, uhcinewval);
877 uhwDelayMicro(50, unit);
878 uhcinewval = READIO16_LE(chc->hc_RegBase, uhciportreg) & ~(UHPF_ENABLECHANGE|UHPF_CONNECTCHANGE|UHPF_PORTSUSPEND);
879 KPRINTF(10, ("UHCI: ReReset=%s\n", uhcinewval & UHPF_PORTRESET ? "STILL BAD!" : "GOOD"));
880 }
881 uhcinewval &= ~UHPF_PORTRESET;
882 uhcinewval |= UHPF_PORTENABLE;
883 WRITEIO16_LE(chc->hc_RegBase, uhciportreg, uhcinewval);
884 chc->hc_PortChangeMap[uhcihciport] |= UPSF_PORT_RESET|UPSF_PORT_ENABLE; // manually fake reset change
885 uhwDelayMS(5, unit);
886 cnt = 100;
887 do
888 {
889 uhwDelayMS(1, unit);
890 uhcinewval = READIO16_LE(chc->hc_RegBase, uhciportreg);
891 } while(--cnt && (!(uhcinewval & UHPF_PORTENABLE)));
892 if(cnt)
893 {
894 KPRINTF(10, ("UHCI: Enabled after %ld ticks\n", 100-cnt));
895 } else {
896 KPRINTF(20, ("UHCI: Port refuses to be enabled!\n"));
897 return(UHIOERR_HOSTERROR);
898 }
899 break;
900 }
901
902 case HCITYPE_OHCI:
903 {
904 UWORD ohcihciport = unit->hu_PortNum11[idx - 1];
905 UWORD ohciportreg = OHCI_PORTSTATUS + (ohcihciport<<2);
906 ULONG ohcioldval = READREG32_LE(chc->hc_RegBase, ohciportreg);
907 KPRINTF(10, ("OHCI: Resetting Port (%s)\n", ohcioldval & OHPF_PORTRESET ? "already" : "ok"));
908 // make sure we have at least 50ms of reset time here, as required for a root hub port
909 WRITEREG32_LE(chc->hc_RegBase, ohciportreg, OHPF_PORTRESET);
910 uhwDelayMS(10, unit);
911 WRITEREG32_LE(chc->hc_RegBase, ohciportreg, OHPF_PORTRESET);
912 uhwDelayMS(10, unit);
913 WRITEREG32_LE(chc->hc_RegBase, ohciportreg, OHPF_PORTRESET);
914 uhwDelayMS(10, unit);
915 WRITEREG32_LE(chc->hc_RegBase, ohciportreg, OHPF_PORTRESET);
916 uhwDelayMS(10, unit);
917 WRITEREG32_LE(chc->hc_RegBase, ohciportreg, OHPF_PORTRESET);
918 uhwDelayMS(15, unit);
919 ohcioldval = READREG32_LE(chc->hc_RegBase, ohciportreg);
920 KPRINTF(10, ("OHCI: Reset release (%s %s)\n", ohcioldval & OHPF_PORTRESET ? "didn't turn off" : "okay",
921 ohcioldval & OHPF_PORTENABLE ? "enabled" : "not enabled"));
922 if(ohcioldval & OHPF_PORTRESET)
923 {
924 uhwDelayMS(40, unit);
925 ohcioldval = READREG32_LE(chc->hc_RegBase, ohciportreg);
926 KPRINTF(10, ("OHCI: Reset 2nd release (%s %s)\n", ohcioldval & OHPF_PORTRESET ? "didn't turn off" : "okay",
927 ohcioldval & OHPF_PORTENABLE ? "enabled" : "still not enabled"));
928 }
929 break;
930 }
931
932 }
933 // make enumeration possible
934 unit->hu_DevControllers[0] = chc;
935 return(0);
936 } else {
937 newval &= ~EHPF_PORTRESET;
938 WRITEREG32_LE(hc->hc_RegBase, portreg, newval);
939 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_RESET; // manually fake reset change
940 uhwDelayMS(10, unit);
941 cnt = 100;
942 do
943 {
944 uhwDelayMS(1, unit);
945 newval = READREG32_LE(hc->hc_RegBase, portreg);
946 } while(--cnt && (!(newval & EHPF_PORTENABLE)));
947 if(cnt)
948 {
949 KPRINTF(10, ("EHCI: Enabled after %ld ticks\n", 100-cnt));
950 } else {
951 KPRINTF(20, ("EHCI: Port refuses to be enabled!\n"));
952 return(UHIOERR_HOSTERROR);
953 }
954 // make enumeration possible
955 unit->hu_DevControllers[0] = hc;
956 }
957 cmdgood = TRUE;
958 break;
959
960 case UFS_PORT_POWER:
961 KPRINTF(10, ("EHCI: Powering Port\n"));
962 newval |= EHPF_PORTPOWER;
963 cmdgood = TRUE;
964 break;
965
966 /* case UFS_PORT_LOW_SPEED: not possible */
967 /* case UFS_C_PORT_CONNECTION:
968 case UFS_C_PORT_ENABLE:
969 case UFS_C_PORT_SUSPEND:
970 case UFS_C_PORT_OVER_CURRENT:
971 case UFS_C_PORT_RESET: */
972 }
973 if(cmdgood)
974 {
975 KPRINTF(5, ("EHCI: Port %ld SET_FEATURE %04lx->%04lx\n", idx, oldval, newval));
976 WRITEREG32_LE(hc->hc_RegBase, portreg, newval);
977 return(0);
978 }
979 break;
980 }
981
982 }
983 break;
984
985 case USR_CLEAR_FEATURE:
986 if((!idx) || (idx > numports))
987 {
988 KPRINTF(20, ("Port %ld out of range\n", idx));
989 return(UHIOERR_STALL);
990 }
991 if(unit->hu_EhciOwned[idx - 1])
992 {
993 hc = unit->hu_PortMap20[idx - 1];
994 hciport = idx - 1;
995 } else {
996 hc = unit->hu_PortMap11[idx - 1];
997 hciport = unit->hu_PortNum11[idx - 1];
998 }
999 KPRINTF(10, ("Clear Feature %ld maps from glob. Port %ld to local Port %ld (%s)\n", val, idx, hciport, unit->hu_EhciOwned[idx - 1] ? "EHCI" : "U/OHCI"));
1000 cmdgood = FALSE;
1001 switch(hc->hc_HCIType)
1002 {
1003 case HCITYPE_UHCI:
1004 {
1005 UWORD portreg = hciport ? UHCI_PORT2STSCTRL : UHCI_PORT1STSCTRL;
1006 ULONG oldval = READIO16_LE(hc->hc_RegBase, portreg) & ~(UHPF_ENABLECHANGE|UHPF_CONNECTCHANGE); // these are clear-on-write!
1007 ULONG newval = oldval;
1008 switch(val)
1009 {
1010 case UFS_PORT_ENABLE:
1011 KPRINTF(10, ("Disabling Port (%s)\n", newval & UHPF_PORTENABLE ? "ok" : "already"));
1012 newval &= ~UHPF_PORTENABLE;
1013 cmdgood = TRUE;
1014 // disable enumeration
1015 unit->hu_DevControllers[0] = NULL;
1016 break;
1017
1018 case UFS_PORT_SUSPEND:
1019 newval &= ~UHPF_PORTSUSPEND;
1020 cmdgood = TRUE;
1021 break;
1022
1023 case UFS_PORT_POWER: // ignore for UHCI, there's no power control here
1024 KPRINTF(10, ("Disabling Power\n"));
1025 KPRINTF(10, ("Disabling Port (%s)\n", newval & UHPF_PORTENABLE ? "ok" : "already"));
1026 newval &= ~UHPF_PORTENABLE;
1027 cmdgood = TRUE;
1028 break;
1029
1030 case UFS_C_PORT_CONNECTION:
1031 newval |= UHPF_CONNECTCHANGE; // clear-on-write!
1032 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_CONNECTION;
1033 cmdgood = TRUE;
1034 break;
1035
1036 case UFS_C_PORT_ENABLE:
1037 newval |= UHPF_ENABLECHANGE; // clear-on-write!
1038 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_ENABLE;
1039 cmdgood = TRUE;
1040 break;
1041
1042 case UFS_C_PORT_SUSPEND: // ignore for UHCI, there's no bit indicating this
1043 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_SUSPEND; // manually fake suspend change clearing
1044 cmdgood = TRUE;
1045 break;
1046
1047 case UFS_C_PORT_OVER_CURRENT: // ignore for UHCI, there's no bit indicating this
1048 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_OVER_CURRENT; // manually fake over current clearing
1049 cmdgood = TRUE;
1050 break;
1051
1052 case UFS_C_PORT_RESET: // ignore for UHCI, there's no bit indicating this
1053 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_RESET; // manually fake reset change clearing
1054 cmdgood = TRUE;
1055 break;
1056 }
1057 if(cmdgood)
1058 {
1059 KPRINTF(5, ("Port %ld CLEAR_FEATURE %04lx->%04lx\n", idx, oldval, newval));
1060 WRITEIO16_LE(hc->hc_RegBase, portreg, newval);
1061 if(hc->hc_PortChangeMap[hciport])
1062 {
1063 unit->hu_RootPortChanges |= 1UL<<idx;
1064 } else {
1065 unit->hu_RootPortChanges &= ~(1UL<<idx);
1066 }
1067 return(0);
1068 }
1069 break;
1070 }
1071
1072 case HCITYPE_OHCI:
1073 {
1074 UWORD portreg = OHCI_PORTSTATUS + (hciport<<2);
1075 ULONG __unused oldval = READREG32_LE(hc->hc_RegBase, portreg);
1076
1077 switch(val)
1078 {
1079 case UFS_PORT_ENABLE:
1080 KPRINTF(10, ("Disabling Port (%s)\n", oldval & OHPF_PORTENABLE ? "ok" : "already"));
1081 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTDISABLE);
1082 cmdgood = TRUE;
1083 break;
1084
1085 case UFS_PORT_SUSPEND:
1086 KPRINTF(10, ("Resuming Port (%s)\n", oldval & OHPF_PORTSUSPEND ? "ok" : "already"));
1087 //hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_SUSPEND; // manually fake suspend change
1088 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_RESUME);
1089 cmdgood = TRUE;
1090 break;
1091
1092 case UFS_PORT_POWER:
1093 KPRINTF(10, ("Unpowering Port (%s)\n", oldval & OHPF_PORTPOWER ? "ok" : "already"));
1094 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_PORTUNPOWER);
1095 cmdgood = TRUE;
1096 break;
1097
1098 case UFS_C_PORT_CONNECTION:
1099 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_CONNECTCHANGE);
1100 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_CONNECTION;
1101 cmdgood = TRUE;
1102 break;
1103
1104 case UFS_C_PORT_ENABLE:
1105 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_ENABLECHANGE);
1106 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_ENABLE;
1107 cmdgood = TRUE;
1108 break;
1109
1110 case UFS_C_PORT_SUSPEND:
1111 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_RESUMEDTX);
1112 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_SUSPEND;
1113 cmdgood = TRUE;
1114 break;
1115
1116 case UFS_C_PORT_OVER_CURRENT:
1117 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_OVERCURRENTCHG);
1118 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_OVER_CURRENT;
1119 cmdgood = TRUE;
1120 break;
1121
1122 case UFS_C_PORT_RESET:
1123 WRITEREG32_LE(hc->hc_RegBase, portreg, OHPF_RESETCHANGE);
1124 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_RESET;
1125 cmdgood = TRUE;
1126 break;
1127 }
1128 if(cmdgood)
1129 {
1130 return(0);
1131 }
1132 break;
1133 }
1134
1135 case HCITYPE_EHCI:
1136 {
1137 UWORD portreg = EHCI_PORTSC1 + (hciport<<2);
1138 ULONG oldval = READREG32_LE(hc->hc_RegBase, portreg) & ~(EHPF_OVERCURRENTCHG|EHPF_ENABLECHANGE|EHPF_CONNECTCHANGE); // these are clear-on-write!
1139 ULONG newval = oldval;
1140 switch(val)
1141 {
1142 case UFS_PORT_ENABLE:
1143 KPRINTF(10, ("Disabling Port (%s)\n", newval & EHPF_PORTENABLE ? "ok" : "already"));
1144 newval &= ~EHPF_PORTENABLE;
1145 cmdgood = TRUE;
1146 // disable enumeration
1147 unit->hu_DevControllers[0] = NULL;
1148 break;
1149
1150 case UFS_PORT_SUSPEND:
1151 newval &= ~EHPF_PORTSUSPEND;
1152 cmdgood = TRUE;
1153 break;
1154
1155 case UFS_PORT_POWER: // ignore for UHCI, there's no power control here
1156 KPRINTF(10, ("Disabling Power (%s)\n", newval & EHPF_PORTPOWER ? "ok" : "already"));
1157 KPRINTF(10, ("Disabling Port (%s)\n", newval & EHPF_PORTENABLE ? "ok" : "already"));
1158 newval &= ~(EHPF_PORTENABLE|EHPF_PORTPOWER);
1159 cmdgood = TRUE;
1160 break;
1161
1162 case UFS_C_PORT_CONNECTION:
1163 newval |= EHPF_CONNECTCHANGE; // clear-on-write!
1164 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_CONNECTION;
1165 cmdgood = TRUE;
1166 break;
1167
1168 case UFS_C_PORT_ENABLE:
1169 newval |= EHPF_ENABLECHANGE; // clear-on-write!
1170 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_ENABLE;
1171 cmdgood = TRUE;
1172 break;
1173
1174 case UFS_C_PORT_SUSPEND: // ignore for EHCI, there's no bit indicating this
1175 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_SUSPEND; // manually fake suspend change clearing
1176 cmdgood = TRUE;
1177 break;
1178
1179 case UFS_C_PORT_OVER_CURRENT:
1180 newval |= EHPF_OVERCURRENTCHG; // clear-on-write!
1181 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_OVER_CURRENT; // manually fake over current clearing
1182 cmdgood = TRUE;
1183 break;
1184
1185 case UFS_C_PORT_RESET: // ignore for EHCI, there's no bit indicating this
1186 hc->hc_PortChangeMap[hciport] &= ~UPSF_PORT_RESET; // manually fake reset change clearing
1187 cmdgood = TRUE;
1188 break;
1189 }
1190 if(cmdgood)
1191 {
1192 KPRINTF(5, ("Port %ld CLEAR_FEATURE %08lx->%08lx\n", idx, oldval, newval));
1193 WRITEREG32_LE(hc->hc_RegBase, portreg, newval);
1194 if(hc->hc_PortChangeMap[hciport])
1195 {
1196 unit->hu_RootPortChanges |= 1UL<<idx;
1197 } else {
1198 unit->hu_RootPortChanges &= ~(1UL<<idx);
1199 }
1200 return(0);
1201 }
1202 break;
1203 }
1204
1205 }
1206 break;
1207 }
1208 break;
1209
1210 case (URTF_IN|URTF_CLASS|URTF_OTHER):
1211 switch(req)
1212 {
1213 case USR_GET_STATUS:
1214 {
1215 UWORD *mptr = ioreq->iouh_Data;
1216 if(len != sizeof(struct UsbPortStatus))
1217 {
1218 return(UHIOERR_STALL);
1219 }
1220 if((!idx) || (idx > numports))
1221 {
1222 KPRINTF(20, ("Port %ld out of range\n", idx));
1223 return(UHIOERR_STALL);
1224 }
1225 if(unit->hu_EhciOwned[idx - 1])
1226 {
1227 hc = unit->hu_PortMap20[idx - 1];
1228 hciport = idx - 1;
1229 } else {
1230 hc = unit->hu_PortMap11[idx - 1];
1231 hciport = unit->hu_PortNum11[idx - 1];
1232 }
1233 switch(hc->hc_HCIType)
1234 {
1235 case HCITYPE_UHCI:
1236 {
1237 UWORD portreg = hciport ? UHCI_PORT2STSCTRL : UHCI_PORT1STSCTRL;
1238 UWORD oldval = READIO16_LE(hc->hc_RegBase, portreg);
1239 *mptr = AROS_WORD2LE(UPSF_PORT_POWER);
1240 if(oldval & UHPF_PORTCONNECTED) *mptr |= AROS_WORD2LE(UPSF_PORT_CONNECTION);
1241 if(oldval & UHPF_PORTENABLE) *mptr |= AROS_WORD2LE(UPSF_PORT_ENABLE);
1242 if(oldval & UHPF_LOWSPEED) *mptr |= AROS_WORD2LE(UPSF_PORT_LOW_SPEED);
1243 if(oldval & UHPF_PORTRESET) *mptr |= AROS_WORD2LE(UPSF_PORT_RESET);
1244 if(oldval & UHPF_PORTSUSPEND) *mptr |= AROS_WORD2LE(UPSF_PORT_SUSPEND);
1245
1246 KPRINTF(5, ("UHCI Port %ld is %s\n", idx, oldval & UHPF_LOWSPEED ? "LOWSPEED" : "FULLSPEED"));
1247 KPRINTF(5, ("UHCI Port %ld Status %08lx\n", idx, *mptr));
1248
1249 mptr++;
1250 if(oldval & UHPF_ENABLECHANGE)
1251 {
1252 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_ENABLE;
1253 }
1254 if(oldval & UHPF_CONNECTCHANGE)
1255 {
1256 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_CONNECTION;
1257 }
1258 if(oldval & UHPF_RESUMEDTX)
1259 {
1260 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_SUSPEND|UPSF_PORT_ENABLE;
1261 }
1262 *mptr = AROS_WORD2LE(hc->hc_PortChangeMap[hciport]);
1263 WRITEIO16_LE(hc->hc_RegBase, portreg, oldval);
1264 KPRINTF(5, ("UHCI Port %ld Change %08lx\n", idx, *mptr));
1265 return(0);
1266 }
1267
1268 case HCITYPE_OHCI:
1269 {
1270 UWORD portreg = OHCI_PORTSTATUS + (hciport<<2);
1271 ULONG oldval = READREG32_LE(hc->hc_RegBase, portreg);
1272
1273 *mptr = 0;
1274 if(oldval & OHPF_PORTPOWER) *mptr |= AROS_WORD2LE(UPSF_PORT_POWER);
1275 if(oldval & OHPF_OVERCURRENT) *mptr |= AROS_WORD2LE(UPSF_PORT_OVER_CURRENT);
1276 if(oldval & OHPF_PORTCONNECTED) *mptr |= AROS_WORD2LE(UPSF_PORT_CONNECTION);
1277 if(oldval & OHPF_PORTENABLE) *mptr |= AROS_WORD2LE(UPSF_PORT_ENABLE);
1278 if(oldval & OHPF_LOWSPEED) *mptr |= AROS_WORD2LE(UPSF_PORT_LOW_SPEED);
1279 if(oldval & OHPF_PORTRESET) *mptr |= AROS_WORD2LE(UPSF_PORT_RESET);
1280 if(oldval & OHPF_PORTSUSPEND) *mptr |= AROS_WORD2LE(UPSF_PORT_SUSPEND);
1281
1282 KPRINTF(5, ("OHCI Port %ld (glob. %ld) is %s\n", hciport, idx, oldval & OHPF_LOWSPEED ? "LOWSPEED" : "FULLSPEED"));
1283 KPRINTF(5, ("OHCI Port %ld Status %08lx (%08lx)\n", idx, *mptr, oldval));
1284
1285 mptr++;
1286 if(oldval & OHPF_OVERCURRENTCHG)
1287 {
1288 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_OVER_CURRENT;
1289 }
1290 if(oldval & OHPF_RESETCHANGE)
1291 {
1292 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_RESET;
1293 }
1294 if(oldval & OHPF_ENABLECHANGE)
1295 {
1296 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_ENABLE;
1297 }
1298 if(oldval & OHPF_CONNECTCHANGE)
1299 {
1300 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_CONNECTION;
1301 }
1302 if(oldval & OHPF_RESUMEDTX)
1303 {
1304 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_SUSPEND;
1305 }
1306 *mptr = AROS_WORD2LE(hc->hc_PortChangeMap[hciport]);
1307 KPRINTF(5, ("OHCI Port %ld Change %08lx\n", idx, *mptr));
1308 return(0);
1309 }
1310
1311 case HCITYPE_EHCI:
1312 {
1313 UWORD portreg = EHCI_PORTSC1 + (hciport<<2);
1314 ULONG oldval = READREG32_LE(hc->hc_RegBase, portreg);
1315
1316 *mptr = 0;
1317 if(oldval & EHPF_PORTCONNECTED) *mptr |= AROS_WORD2LE(UPSF_PORT_CONNECTION);
1318 if(oldval & EHPF_PORTENABLE) *mptr |= AROS_WORD2LE(UPSF_PORT_ENABLE|UPSF_PORT_HIGH_SPEED);
1319 if((oldval & (EHPF_LINESTATUS_DM|EHPF_PORTCONNECTED|EHPF_PORTENABLE)) ==
1320 (EHPF_LINESTATUS_DM|EHPF_PORTCONNECTED))
1321 {
1322 KPRINTF(10, ("EHCI Port %ld is LOWSPEED\n", idx));
1323 // we need to detect low speed devices prior to reset
1324 *mptr |= AROS_WORD2LE(UPSF_PORT_LOW_SPEED);
1325 }
1326
1327 if(oldval & EHPF_PORTRESET) *mptr |= AROS_WORD2LE(UPSF_PORT_RESET);
1328 if(oldval & EHPF_PORTSUSPEND) *mptr |= AROS_WORD2LE(UPSF_PORT_SUSPEND);
1329 if(oldval & EHPF_PORTPOWER) *mptr |= AROS_WORD2LE(UPSF_PORT_POWER);
1330 if(oldval & EHPM_PORTINDICATOR) *mptr |= AROS_WORD2LE(UPSF_PORT_INDICATOR);
1331
1332 KPRINTF(5, ("EHCI Port %ld Status %08lx\n", idx, *mptr));
1333
1334 mptr++;
1335 if(oldval & EHPF_ENABLECHANGE)
1336 {
1337 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_ENABLE;
1338 }
1339 if(oldval & EHPF_CONNECTCHANGE)
1340 {
1341 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_CONNECTION;
1342 }
1343 if(oldval & EHPF_RESUMEDTX)
1344 {
1345 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_SUSPEND|UPSF_PORT_ENABLE;
1346 }
1347 if(oldval & EHPF_OVERCURRENTCHG)
1348 {
1349 hc->hc_PortChangeMap[hciport] |= UPSF_PORT_OVER_CURRENT;
1350 }
1351 *mptr = AROS_WORD2LE(hc->hc_PortChangeMap[hciport]);
1352 WRITEREG32_LE(hc->hc_RegBase, portreg, oldval);
1353 KPRINTF(5, ("EHCI Port %ld Change %08lx\n", idx, *mptr));
1354 return(0);
1355 }
1356
1357 }
1358 return(0);
1359 }
1360
1361 }
1362 break;
1363
1364 case (URTF_IN|URTF_CLASS|URTF_DEVICE):
1365 switch(req)
1366 {
1367 case USR_GET_STATUS:
1368 {
1369 UWORD *mptr = ioreq->iouh_Data;
1370 if(len < sizeof(struct UsbHubStatus))
1371 {
1372 return(UHIOERR_STALL);
1373 }
1374 *mptr++ = 0;
1375 *mptr++ = 0;
1376 ioreq->iouh_Actual = 4;
1377 return(0);
1378 }
1379
1380 case USR_GET_DESCRIPTOR:
1381 switch(val>>8)
1382 {
1383 case UDT_HUB:
1384 {
1385 ULONG hubdesclen = 9;
1386 ULONG powergood = 1;
1387
1388 struct UsbHubDesc *uhd = (struct UsbHubDesc *) ioreq->iouh_Data;
1389 KPRINTF(1, ("RH: GetHubDescriptor (%ld)\n", len));
1390
1391 if(unit->hu_RootHubPorts > 7) // needs two bytes for port masks
1392 {
1393 hubdesclen += 2;
1394 }
1395
1396 ioreq->iouh_Actual = (len > hubdesclen) ? hubdesclen : len;
1397 CopyMem((APTR) &RHHubDesc, ioreq->iouh_Data, ioreq->iouh_Actual);
1398
1399 if(ioreq->iouh_Length)
1400 {
1401 uhd->bLength = hubdesclen;
1402 }
1403
1404 if(ioreq->iouh_Length >= 6)
1405 {
1406 hc = (struct PCIController *) unit->hu_Controllers.lh_Head;
1407 while(hc->hc_Node.ln_Succ)
1408 {
1409 if(hc->hc_HCIType == HCITYPE_OHCI)
1410 {
1411 ULONG localpwgood = (READREG32_LE(hc->hc_RegBase, OHCI_HUBDESCA) & OHAM_POWERGOOD) >> OHAS_POWERGOOD;
1412 if(localpwgood > powergood)
1413 {
1414 powergood = localpwgood;
1415 KPRINTF(10, ("Increasing power good time to %ld\n", powergood));
1416 }
1417 }
1418 hc = (struct PCIController *) hc->hc_Node.ln_Succ;
1419 }
1420
1421 uhd->bPwrOn2PwrGood = powergood;
1422 }
1423 if(ioreq->iouh_Length >= hubdesclen)
1424 {
1425 uhd->bNbrPorts = unit->hu_RootHubPorts;
1426 if(hubdesclen == 9)
1427 {
1428 uhd->DeviceRemovable = 0;
1429 uhd->PortPwrCtrlMask = (1<<(unit->hu_RootHubPorts+2))-2;
1430 } else {
1431 // each field is now 16 bits wide
1432 uhd->DeviceRemovable = 0;
1433 uhd->PortPwrCtrlMask = 0;
1434 ((UBYTE *) ioreq->iouh_Data)[9] = (1<<(unit->hu_RootHubPorts+2))-2;
1435 ((UBYTE *) ioreq->iouh_Data)[10] = ((1<<(unit->hu_RootHubPorts+2))-2)>>8;
1436 }
1437 }
1438 return(0);
1439 }
1440
1441 default:
1442 KPRINTF(20, ("RH: Unsupported Descriptor %04lx\n", idx));
1443 }
1444 break;
1445 }
1446
1447 }
1448 KPRINTF(20, ("RH: Unsupported command %02lx %02lx %04lx %04lx %04lx!\n", rt, req, idx, val, len));
1449 return(UHIOERR_STALL);
1450 }
1451 /* \\\ */
1452
1453 /* /// "cmdIntXFerRootHub()" */
1454 WORD cmdIntXFerRootHub(struct IOUsbHWReq *ioreq,
1455 struct PCIUnit *unit,
1456 struct PCIDevice *base)
1457 {
1458 if((ioreq->iouh_Endpoint != 1) || (!ioreq->iouh_Length))
1459 {
1460 return(UHIOERR_STALL);
1461 }
1462
1463 if(unit->hu_RootPortChanges)
1464 {
1465 KPRINTF(1, ("Immediate Portchange map %04lx\n", unit->hu_RootPortChanges));
1466 if((unit->hu_RootHubPorts < 8) || (ioreq->iouh_Length == 1))
1467 {
1468 *((UBYTE *) ioreq->iouh_Data) = unit->hu_RootPortChanges;
1469 ioreq->iouh_Actual = 1;
1470 } else {
1471 ((UBYTE *) ioreq->iouh_Data)[0] = unit->hu_RootPortChanges;
1472 ((UBYTE *) ioreq->iouh_Data)[1] = unit->hu_RootPortChanges>>8;
1473 ioreq->iouh_Actual = 2;
1474 }
1475 unit->hu_RootPortChanges = 0;
1476 return(0);
1477 }
1478 ioreq->iouh_Req.io_Flags &= ~IOF_QUICK;
1479 Disable();
1480 AddTail(&unit->hu_RHIOQueue, (struct Node *) ioreq);
1481 Enable();
1482 return(RC_DONTREPLY);
1483 }
1484 /* \\\ */
1485
1486 /* /// "cmdControlXFer()" */
1487 /*
1488 *======================================================================
1489 * cmdControlXFer(ioreq, unit, base)
1490 *======================================================================
1491 *
1492 * This is the device UHCMD_CONTROLXFER routine.
1493 *
1494 * First it check if the usb is in proper state and if user passed arguments
1495 * are valid. If everything is ok, the request is linked to queue of
1496 * pending transfer requests.
1497 *
1498 */
1499
1500 WORD cmdControlXFer(struct IOUsbHWReq *ioreq,
1501 struct PCIUnit *unit,
1502 struct PCIDevice *base)
1503 {
1504 struct PCIController *hc;
1505
1506 KPRINTF(10, ("UHCMD_CONTROLXFER ioreq: 0x%p\n", ioreq));
1507 uhwGetUsbState(ioreq, unit, base);
1508 if(!(ioreq->iouh_State & UHSF_OPERATIONAL))
1509 {
1510 return(UHIOERR_USBOFFLINE);
1511 }
1512 /* Root hub emulation */
1513 if(ioreq->iouh_DevAddr == unit->hu_RootHubAddr)
1514 {
1515 return(cmdControlXFerRootHub(ioreq, unit, base));
1516 }
1517
1518 hc = unit->hu_DevControllers[ioreq->iouh_DevAddr];
1519 if(!hc)
1520 {
1521 KPRINTF(20, ("No Host controller assigned to device address %ld\n", ioreq->iouh_DevAddr));
1522 return(UHIOERR_HOSTERROR);
1523 }
1524
1525 ioreq->iouh_Req.io_Flags &= ~IOF_QUICK;
1526 ioreq->iouh_Actual = 0;
1527
1528 Disable();
1529 AddTail(&hc->hc_CtrlXFerQueue, (struct Node *) ioreq);
1530 Enable();
1531 SureCause(base, &hc->hc_CompleteInt);
1532
1533 KPRINTF(10, ("UHCMD_CONTROLXFER processed ioreq: 0x%p\n", ioreq));
1534 return(RC_DONTREPLY);
1535 }
1536 /* \\\ */
1537
1538 /* /// "cmdBulkXFer()" */
1539 /*
1540 *======================================================================
1541 * cmdBulkXFer(ioreq, unit, base)
1542 *======================================================================
1543 *
1544 * This is the device UHCMD_BULKXFER routine.
1545 *
1546 * First it check if the usb is in proper state and if user passed arguments
1547 * are valid. If everything is ok, the request is linked to queue of
1548 * pending transfer requests.
1549 *
1550 */
1551
1552 WORD cmdBulkXFer(struct IOUsbHWReq *ioreq,
1553 struct PCIUnit *unit,
1554 struct PCIDevice *base)
1555 {
1556 struct PCIController *hc;
1557
1558 KPRINTF(10, ("UHCMD_BULKXFER ioreq: 0x%p\n", ioreq));
1559 uhwGetUsbState(ioreq, unit, base);
1560 if(!(ioreq->iouh_State & UHSF_OPERATIONAL))
1561 {
1562 return(UHIOERR_USBOFFLINE);
1563 }
1564
1565 if(ioreq->iouh_Flags & UHFF_LOWSPEED)
1566 {
1567 return(UHIOERR_BADPARAMS);
1568 }
1569
1570 hc = unit->hu_DevControllers[ioreq->iouh_DevAddr];
1571 if(!hc)
1572 {
1573 return(UHIOERR_HOSTERROR);
1574 }
1575
1576 ioreq->iouh_Req.io_Flags &= ~IOF_QUICK;
1577 ioreq->iouh_Actual = 0;
1578
1579 Disable();
1580 AddTail(&hc->hc_BulkXFerQueue, (struct Node *) ioreq);
1581 Enable();
1582 SureCause(base, &hc->hc_CompleteInt);
1583
1584 KPRINTF(10, ("UHCMD_BULKXFER processed ioreq: 0x%p\n", ioreq));
1585 return(RC_DONTREPLY);
1586 }
1587 /* \\\ */
1588
1589 /* /// "cmdIsoXFer()" */
1590 /*
1591 *======================================================================
1592 * cmdIsoXFer(ioreq, unit, base)
1593 *======================================================================
1594 *
1595 * This is the device UHCMD_ISOXFER routine.
1596 *
1597 * First it check if the usb is in proper state and if user passed arguments
1598 * are valid. If everything is ok, the request is linked to queue of
1599 * pending transfer requests.
1600 *
1601 */
1602
1603 WORD cmdIsoXFer(struct IOUsbHWReq *ioreq,
1604 struct PCIUnit *unit,
1605 struct PCIDevice *base)
1606 {
1607 struct PCIController *hc;
1608
1609 KPRINTF(10, ("UHCMD_ISOXFER ioreq: 0x%p\n", ioreq));
1610 uhwGetUsbState(ioreq, unit, base);
1611 if(!(ioreq->iouh_State & UHSF_OPERATIONAL))
1612 {
1613 return(UHIOERR_USBOFFLINE);
1614 }
1615
1616 if(ioreq->iouh_Flags & UHFF_LOWSPEED)
1617 {
1618 return(UHIOERR_BADPARAMS);
1619 }
1620
1621 hc = unit->hu_DevControllers[ioreq->iouh_DevAddr];
1622 if(!hc)
1623 {
1624 return(UHIOERR_HOSTERROR);
1625 }
1626
1627 ioreq->iouh_Req.io_Flags &= ~IOF_QUICK;
1628 ioreq->iouh_Actual = 0;
1629
1630 Disable();
1631 AddTail(&hc->hc_IsoXFerQueue, (struct Node *) ioreq);
1632 Enable();
1633 SureCause(base, &hc->hc_CompleteInt);
1634
1635 KPRINTF(10, ("UHCMD_ISOXFER processed ioreq: 0x%p\n", ioreq));
1636 return(RC_DONTREPLY);
1637 }
1638 /* \\\ */
1639
1640 /* /// "cmdIntXFer()" */
1641 /*
1642 *======================================================================
1643 * cmdIntXFer(ioreq, unit, base)
1644 *======================================================================
1645 *
1646 * This is the device UHCMD_INTXFER routine.
1647 *
1648 * First it check if the usb is in proper state and if user passed arguments
1649 * are valid. If everything is ok, the request is linked to queue of
1650 * pending transfer requests.
1651 *
1652 */
1653
1654 WORD cmdIntXFer(struct IOUsbHWReq *ioreq,
1655 struct PCIUnit *unit,
1656 struct PCIDevice *base)
1657 {
1658 struct PCIController *hc;
1659
1660 KPRINTF(10, ("UHCMD_INTXFER ioreq: 0x%p\n", ioreq));
1661 //uhwDelayMS(1000, unit); /* Wait 200 ms */
1662 uhwGetUsbState(ioreq, unit, base);
1663 if(!(ioreq->iouh_State & UHSF_OPERATIONAL))
1664 {
1665 return(UHIOERR_USBOFFLINE);
1666 }
1667
1668 /* Root Hub Emulation */
1669 if(ioreq->iouh_DevAddr == unit->hu_RootHubAddr)
1670 {
1671 return(cmdIntXFerRootHub(ioreq, unit, base));
1672 }
1673
1674 hc = unit->hu_DevControllers[ioreq->iouh_DevAddr];
1675 if(!hc)
1676 {
1677 return(UHIOERR_HOSTERROR);
1678 }
1679
1680 ioreq->iouh_Req.io_Flags &= ~IOF_QUICK;
1681 ioreq->iouh_Actual = 0;
1682
1683 Disable();
1684 AddTail(&hc->hc_IntXFerQueue, (struct Node *) ioreq);
1685 Enable();
1686 SureCause(base, &hc->hc_CompleteInt);
1687
1688 KPRINTF(10, ("UHCMD_INTXFER processed ioreq: 0x%p\n", ioreq));
1689 return(RC_DONTREPLY);
1690 }
1691 /* \\\ */
1692
1693 /* /// "cmdFlush()" */
1694 /*
1695 *======================================================================
1696 * cmdFlush(ioreq, base)
1697 *======================================================================
1698 *
1699 * This is the device CMD_FLUSH routine.
1700 *
1701 * This routine abort all pending transfer requests.
1702 *
1703 */
1704
1705 WORD cmdFlush(struct IOUsbHWReq *ioreq,
1706 struct PCIUnit *unit,
1707 struct PCIDevice *base)
1708 {
1709 struct IOUsbHWReq *cmpioreq;
1710 struct PCIController *hc;
1711 UWORD devadrep;
1712
1713 KPRINTF(10, ("CMD_FLUSH ioreq: 0x%p\n", ioreq));
1714
1715 Disable();
1716 cmpioreq = (struct IOUsbHWReq *) unit->hu_RHIOQueue.lh_Head;
1717 while(((struct Node *) cmpioreq)->ln_Succ)
1718 {
1719 Remove(&cmpioreq->iouh_Req.io_Message.mn_Node);
1720 cmpioreq->iouh_Req.io_Error = IOERR_ABORTED;
1721 ReplyMsg(&cmpioreq->iouh_Req.io_Message);
1722 cmpioreq = (struct IOUsbHWReq *) unit->hu_RHIOQueue.lh_Head;
1723 }
1724 hc = (struct PCIController *) unit->hu_Controllers.lh_Head;
1725 while(hc->hc_Node.ln_Succ)
1726 {
1727 cmpioreq = (struct IOUsbHWReq *) hc->hc_CtrlXFerQueue.lh_Head;
1728 while(((struct Node *) cmpioreq)->ln_Succ)
1729 {
1730 Remove(&cmpioreq->iouh_Req.io_Message.mn_Node);
1731 cmpioreq->iouh_Req.io_Error = IOERR_ABORTED;
1732 ReplyMsg(&cmpioreq->iouh_Req.io_Message);
1733 cmpioreq = (struct IOUsbHWReq *) hc->hc_CtrlXFerQueue.lh_Head;
1734 }
1735 cmpioreq = (struct IOUsbHWReq *) hc->hc_IntXFerQueue.lh_Head;
1736 while(((struct Node *) cmpioreq)->ln_Succ)
1737 {
1738 Remove(&cmpioreq->iouh_Req.io_Message.mn_Node);
1739 cmpioreq->iouh_Req.io_Error = IOERR_ABORTED;
1740 ReplyMsg(&cmpioreq->iouh_Req.io_Message);
1741 cmpioreq = (struct IOUsbHWReq *) hc->hc_IntXFerQueue.lh_Head;
1742 }
1743 cmpioreq = (struct IOUsbHWReq *) hc->hc_IsoXFerQueue.lh_Head;
1744 while(((struct Node *) cmpioreq)->ln_Succ)
1745 {
1746 Remove(&cmpioreq->iouh_Req.io_Message.mn_Node);
1747 cmpioreq->iouh_Req.io_Error = IOERR_ABORTED;
1748 ReplyMsg(&cmpioreq->iouh_Req.io_Message);
1749 cmpioreq = (struct IOUsbHWReq *) hc->hc_IsoXFerQueue.lh_Head;
1750 }
1751 cmpioreq = (struct IOUsbHWReq *) hc->hc_BulkXFerQueue.lh_Head;
1752 while(((struct Node *) cmpioreq)->ln_Succ)
1753 {
1754 Remove(&cmpioreq->iouh_Req.io_Message.mn_Node);
1755 cmpioreq->iouh_Req.io_Error = IOERR_ABORTED;
1756 ReplyMsg(&cmpioreq->iouh_Req.io_Message);
1757 cmpioreq = (struct IOUsbHWReq *) hc->hc_BulkXFerQueue.lh_Head;
1758 }
1759 switch(hc->hc_HCIType)
1760 {
1761 case HCITYPE_UHCI:
1762 cmpioreq = (struct IOUsbHWReq *) hc->hc_TDQueue.lh_Head;
1763 while(((struct Node *) cmpioreq)->ln_Succ)
1764 {
1765 Remove(&cmpioreq->iouh_Req.io_Message.mn_Node);
1766 devadrep = (cmpioreq->iouh_DevAddr<<5) + cmpioreq->iouh_Endpoint + ((cmpioreq->iouh_Dir == UHDIR_IN) ? 0x10 : 0);
1767 unit->hu_DevBusyReq[devadrep] = NULL;
1768 uhciFreeQContext(hc, (struct UhciQH *) cmpioreq->iouh_DriverPrivate1);
1769 cmpioreq->iouh_Req.io_Error = IOERR_ABORTED;
1770 ReplyMsg(&cmpioreq->iouh_Req.io_Message);
1771 cmpioreq = (struct IOUsbHWReq *) hc->hc_TDQueue.lh_Head;
1772 }
1773 break;
1774
1775 case HCITYPE_EHCI:
1776 cmpioreq = (struct IOUsbHWReq *) hc->hc_TDQueue.lh_Head;
1777 while(((struct Node *) cmpioreq)->ln_Succ)
1778 {
1779 ehciFreeAsyncContext(hc, cmpioreq);
1780 cmpioreq->iouh_Req.io_Error = IOERR_ABORTED;
1781 ReplyMsg(&cmpioreq->iouh_Req.io_Message);
1782 cmpioreq = (struct IOUsbHWReq *) hc->hc_TDQueue.lh_Head;
1783 }
1784 cmpioreq = (struct IOUsbHWReq *) hc->hc_PeriodicTDQueue.lh_Head;
1785 while(((struct Node *) cmpioreq)->ln_Succ)
1786 {
1787 ehciFreePeriodicContext(hc, cmpioreq);
1788 cmpioreq->iouh_Req.io_Error = IOERR_ABORTED;
1789 ReplyMsg(&cmpioreq->iouh_Req.io_Message);
1790 cmpioreq = (struct IOUsbHWReq *) hc->hc_PeriodicTDQueue.lh_Head;
1791 }
1792 break;
1793 }
1794 hc = (struct PCIController *) hc->hc_Node.ln_Succ;
1795 }
1796 Enable();
1797 /* Return success
1798 */
1799 return RC_OK;
1800 }
1801 /* \\\ */
1802
1803 /* /// "NSD stuff" */
1804
1805 static
1806 const UWORD NSDSupported[] =
1807 {
1808 CMD_FLUSH, CMD_RESET,
1809 UHCMD_QUERYDEVICE, UHCMD_USBRESET,
1810 UHCMD_USBRESUME, UHCMD_USBSUSPEND,
1811 UHCMD_USBOPER, UHCMD_CONTROLXFER ,
1812 UHCMD_ISOXFER, UHCMD_INTXFER,
1813 UHCMD_BULKXFER,
1814 NSCMD_DEVICEQUERY, 0
1815 };
1816
1817 WORD cmdNSDeviceQuery(struct IOStdReq *ioreq,
1818 struct PCIUnit *unit,
1819 struct PCIDevice *base)
1820 {
1821 struct my_NSDeviceQueryResult *query;
1822
1823 query = (struct my_NSDeviceQueryResult *) ioreq->io_Data;
1824
1825 KPRINTF(10, ("NSCMD_DEVICEQUERY ioreq: 0x%p query: 0x%p\n", ioreq, query));
1826
1827 /* NULL ptr?
1828 Enough data?
1829 Valid request?
1830 */
1831 if((!query) ||
1832 (ioreq->io_Length < sizeof(struct my_NSDeviceQueryResult)) ||
1833 (query->DevQueryFormat != 0) ||
1834 (query->SizeAvailable != 0))
1835 {
1836 /* Return error. This is special handling, since iorequest is only
1837 guaranteed to be sizeof(struct IOStdReq). If we'd let our
1838 devBeginIO dispatcher return the error, it would trash some
1839 memory past end of the iorequest (ios2_WireError field).
1840 */
1841 ioreq->io_Error = IOERR_NOCMD;
1842 TermIO((struct IOUsbHWReq *) ioreq, base);
1843
1844 /* Don't reply, we already did.
1845 */
1846 return RC_DONTREPLY;
1847 }
1848
1849 ioreq->io_Actual = query->SizeAvailable
1850 = sizeof(struct my_NSDeviceQueryResult);
1851 query->DeviceType = NSDEVTYPE_USBHARDWARE;
1852 query->DeviceSubType = 0;
1853 query->SupportedCommands = NSDSupported;
1854
1855 /* Return success (note that this will NOT poke ios2_WireError).
1856 */
1857 return RC_OK;
1858 }
1859 /* \\\ */
1860
1861 /* /// "TermIO()" */
1862 /*
1863 *===========================================================
1864 * TermIO(ioreq, base)
1865 *===========================================================
1866 *
1867 * Return completed ioreq to sender.
1868 *
1869 */
1870
1871 void TermIO(struct IOUsbHWReq *ioreq,
1872 struct PCIDevice *base)
1873 {
1874 ioreq->iouh_Req.io_Message.mn_Node.ln_Type = NT_FREEMSG;
1875
1876 /* If not quick I/O, reply the message
1877 */
1878 if(!(ioreq->iouh_Req.io_Flags & IOF_QUICK))
1879 {
1880 ReplyMsg(&ioreq->iouh_Req.io_Message);
1881 }
1882 }
1883 /* \\\ */
1884
1885 /* /// "cmdAbortIO()" */
1886 BOOL cmdAbortIO(struct IOUsbHWReq *ioreq, struct PCIDevice *base)
1887 {
1888 struct PCIUnit *unit = (struct PCIUnit *) ioreq->iouh_Req.io_Unit;
1889 struct IOUsbHWReq *cmpioreq;
1890 struct PCIController *hc;
1891 UWORD devadrep;
1892 BOOL foundit = FALSE;
1893
1894 KPRINTF(10, ("cmdAbort(%p)\n", ioreq));
1895
1896 Disable();
1897 cmpioreq = (struct IOUsbHWReq *) unit->hu_RHIOQueue.lh_Head;
1898 while(((struct Node *) cmpioreq)->ln_Succ)
1899 {
1900 if(ioreq == cmpioreq)
1901 {
1902 Remove(&ioreq->iouh_Req.io_Message.mn_Node);
1903 Enable();
1904 return TRUE;
1905 }
1906 cmpioreq = (struct IOUsbHWReq *) cmpioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
1907 }
1908
1909 hc = (struct PCIController *) unit->hu_Controllers.lh_Head;
1910 while(hc->hc_Node.ln_Succ)
1911 {
1912 cmpioreq = (struct IOUsbHWReq *) hc->hc_CtrlXFerQueue.lh_Head;
1913 while(((struct Node *) cmpioreq)->ln_Succ)
1914 {
1915 if(ioreq == cmpioreq)
1916 {
1917 foundit = TRUE;
1918 break;
1919 }
1920 cmpioreq = (struct IOUsbHWReq *) cmpioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
1921 }
1922 if(!foundit)
1923 {
1924 cmpioreq = (struct IOUsbHWReq *) hc->hc_IntXFerQueue.lh_Head;
1925 while(((struct Node *) cmpioreq)->ln_Succ)
1926 {
1927 if(ioreq == cmpioreq)
1928 {
1929 foundit = TRUE;
1930 break;
1931 }
1932 cmpioreq = (struct IOUsbHWReq *) cmpioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
1933 }
1934 }
1935 if(!foundit)
1936 {
1937 cmpioreq = (struct IOUsbHWReq *) hc->hc_IsoXFerQueue.lh_Head;
1938 while(((struct Node *) cmpioreq)->ln_Succ)
1939 {
1940 if(ioreq == cmpioreq)
1941 {
1942 foundit = TRUE;
1943 break;
1944 }
1945 cmpioreq = (struct IOUsbHWReq *) cmpioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
1946 }
1947 }
1948 if(!foundit)
1949 {
1950 cmpioreq = (struct IOUsbHWReq *) hc->hc_BulkXFerQueue.lh_Head;
1951 while(((struct Node *) cmpioreq)->ln_Succ)
1952 {
1953 if(ioreq == cmpioreq)
1954 {
1955 foundit = TRUE;
1956 break;
1957 }
1958 cmpioreq = (struct IOUsbHWReq *) cmpioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
1959 }
1960 }
1961 if(!foundit)
1962 {
1963 // IOReq is probably pending in some transfer structure
1964 devadrep = (ioreq->iouh_DevAddr<<5) + ioreq->iouh_Endpoint + ((ioreq->iouh_Dir == UHDIR_IN) ? 0x10 : 0);
1965 switch(hc->hc_HCIType)
1966 {
1967 case HCITYPE_UHCI:
1968 cmpioreq = (struct IOUsbHWReq *) hc->hc_TDQueue.lh_Head;
1969 while(((struct Node *) cmpioreq)->ln_Succ)
1970 {
1971 if(ioreq == cmpioreq)
1972 {
1973 foundit = TRUE;
1974 unit->hu_DevBusyReq[devadrep] = NULL;
1975 uhciFreeQContext(hc, (struct UhciQH *) ioreq->iouh_DriverPrivate1);
1976 break;
1977 }
1978 cmpioreq = (struct IOUsbHWReq *) cmpioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
1979 }
1980 break;
1981
1982 case HCITYPE_OHCI:
1983 cmpioreq = (struct IOUsbHWReq *) hc->hc_TDQueue.lh_Head;
1984 while(((struct Node *) cmpioreq)->ln_Succ)
1985 {
1986 if(ioreq == cmpioreq)
1987 {
1988 /*
1989 * Request's ED is in use by the HC, as well as its TDs and
1990 * data buffers.
1991 * Schedule abort on the HC driver and reply the request
1992 * only when done. However return success.
1993 */
1994 ioreq->iouh_Req.io_Error = IOERR_ABORTED;
1995 ohciAbortRequest(hc, ioreq);
1996 Enable();
1997 return TRUE;
1998 }
1999 cmpioreq = (struct IOUsbHWReq *) cmpioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
2000 }
2001 break;
2002
2003 case HCITYPE_EHCI:
2004 cmpioreq = (struct IOUsbHWReq *) hc->hc_TDQueue.lh_Head;
2005 while(((struct Node *) cmpioreq)->ln_Succ)
2006 {
2007 if(ioreq == cmpioreq)
2008 {
2009 /*
2010 * CHECKME: Perhaps immediate freeing can cause issues similar to OHCI.
2011 * Should synchronized abort routine be implemented here too ?
2012 */
2013 ehciFreeAsyncContext(hc, ioreq);
2014 Enable();
2015 ioreq->iouh_Req.io_Error = IOERR_ABORTED;
2016 TermIO(ioreq, base);
2017 return TRUE;
2018 }
2019 cmpioreq = (struct IOUsbHWReq *) cmpioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
2020 }
2021 cmpioreq = (struct IOUsbHWReq *) hc->hc_PeriodicTDQueue.lh_Head;
2022 while(((struct Node *) cmpioreq)->ln_Succ)
2023 {
2024 if(ioreq == cmpioreq)
2025 {
2026 ehciFreePeriodicContext(hc, ioreq);
2027 Enable();
2028 ioreq->iouh_Req.io_Error = IOERR_ABORTED;
2029 TermIO(ioreq, base);
2030 return TRUE;
2031 }
2032 cmpioreq = (struct IOUsbHWReq *) cmpioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
2033 }
2034 break;
2035
2036 }
2037 }
2038 if(foundit)
2039 {
2040 Remove(&ioreq->iouh_Req.io_Message.mn_Node);
2041 break;
2042 }
2043 hc = (struct PCIController *) hc->hc_Node.ln_Succ;
2044 }
2045 Enable();
2046
2047 if (foundit)
2048 {
2049 ioreq->iouh_Req.io_Error = IOERR_ABORTED;
2050 TermIO(ioreq, base);
2051 }
2052 else
2053 {
2054 KPRINTF(20, ("WARNING, could not abort unknown IOReq %p\n", ioreq));
2055 }
2056 return(foundit);
2057 }
2058 /* \\\ */
2059
2060 /* /// "uhwCheckRootHubChanges()" */
2061 void uhwCheckRootHubChanges(struct PCIUnit *unit)
2062 {
2063 struct IOUsbHWReq *ioreq;
2064
2065 if(unit->hu_RootPortChanges && unit->hu_RHIOQueue.lh_Head->ln_Succ)
2066 {
2067 KPRINTF(1, ("Portchange map %04lx\n", unit->hu_RootPortChanges));
2068 Disable();
2069 ioreq = (struct IOUsbHWReq *) unit->hu_RHIOQueue.lh_Head;
2070 while(((struct Node *) ioreq)->ln_Succ)
2071 {
2072 Remove(&ioreq->iouh_Req.io_Message.mn_Node);
2073 if((unit->hu_RootHubPorts < 8) || (ioreq->iouh_Length == 1))
2074 {
2075 *((UBYTE *) ioreq->iouh_Data) = unit->hu_RootPortChanges;
2076 ioreq->iouh_Actual = 1;
2077 } else {
2078 ((UBYTE *) ioreq->iouh_Data)[0] = unit->hu_RootPortChanges;
2079 ((UBYTE *) ioreq->iouh_Data)[1] = unit->hu_RootPortChanges>>8;
2080 ioreq->iouh_Actual = 2;
2081 }
2082 ReplyMsg(&ioreq->iouh_Req.io_Message);
2083 ioreq = (struct IOUsbHWReq *) unit->hu_RHIOQueue.lh_Head;
2084 }
2085 unit->hu_RootPortChanges = 0;
2086 Enable();
2087 }
2088 }
2089 /* \\\ */
2090
2091 /* /// "uhwCheckSpecialCtrlTransfers()" */
2092 void uhwCheckSpecialCtrlTransfers(struct PCIController *hc, struct IOUsbHWReq *ioreq)
2093 {
2094 struct PCIUnit *unit = hc->hc_Unit;
2095
2096 /* Clear Feature(Endpoint halt) */
2097 if((ioreq->iouh_SetupData.bmRequestType == (URTF_STANDARD|URTF_ENDPOINT)) &&
2098 (ioreq->iouh_SetupData.bRequest == USR_CLEAR_FEATURE) &&
2099 (ioreq->iouh_SetupData.wValue == AROS_WORD2LE(UFS_ENDPOINT_HALT)))
2100 {
2101 KPRINTF(10, ("Resetting toggle bit for endpoint %ld\n", AROS_WORD2LE(ioreq->iouh_SetupData.wIndex) & 0xf));
2102 unit->hu_DevDataToggle[(ioreq->iouh_DevAddr<<5)|(AROS_WORD2LE(ioreq->iouh_SetupData.wIndex) & 0xf)|((AROS_WORD2LE(ioreq->iouh_SetupData.wIndex) & 0x80)>>3)] = 0;
2103 }
2104 else if((ioreq->iouh_SetupData.bmRequestType == (URTF_STANDARD|URTF_DEVICE)) &&
2105 (ioreq->iouh_SetupData.bRequest == USR_SET_ADDRESS))
2106 {
2107 /* Set Address -> clear all endpoints */
2108 ULONG epnum;
2109 ULONG adr = AROS_WORD2BE(ioreq->iouh_SetupData.wValue)>>3;
2110 KPRINTF(10, ("Resetting toggle bits for device address %ld\n", adr>>5));
2111 for(epnum = 0; epnum < 31; epnum++)
2112 {
2113 unit->hu_DevDataToggle[adr+epnum] = 0;
2114 }
2115 // transfer host controller ownership
2116 unit->hu_DevControllers[ioreq->iouh_DevAddr] = NULL;
2117 unit->hu_DevControllers[adr>>5] = hc;
2118 }
2119 else if((ioreq->iouh_SetupData.bmRequestType == (URTF_CLASS|URTF_OTHER)) &&
2120 (ioreq->iouh_SetupData.bRequest == USR_SET_FEATURE) &&
2121 (ioreq->iouh_SetupData.wValue == AROS_WORD2LE(UFS_PORT_RESET)))
2122 {
2123 // a hub will be enumerating a device on this host controller soon!
2124 KPRINTF(10, ("Hub RESET caught, assigning Dev0 to %p!\n", hc));
2125 unit->hu_DevControllers[0] = hc;
2126 }
2127 }
2128 /* \\\ */
2129
2130 /* /// "uhwNakTimeoutInt()" */
2131 AROS_INTH1(uhwNakTimeoutInt, struct PCIUnit *, unit)
2132 {
2133 AROS_INTFUNC_INIT
2134
2135 struct PCIDevice *base = unit->hu_Device;
2136 struct PCIController *hc;
2137 struct IOUsbHWReq *ioreq;
2138 struct UhciQH *uqh;
2139 struct UhciTD *utd;
2140 struct EhciQH *eqh;
2141 UWORD devadrep;
2142 UWORD cnt;
2143 ULONG linkelem;
2144 ULONG ctrlstatus;
2145 BOOL causeint;
2146
2147 KPRINTF(1, ("Enter NakTimeoutInt(0x%p)\n", unit));
2148
2149 // check for port status change for UHCI and frame rollovers and NAK Timeouts
2150 hc = (struct PCIController *) unit->hu_Controllers.lh_Head;
2151 while(hc->hc_Node.ln_Succ)
2152 {
2153 if (!(hc->hc_Flags & HCF_ONLINE))
2154 {
2155 hc = (struct PCIController *) hc->hc_Node.ln_Succ;
2156 continue;
2157 }
2158 causeint = FALSE;
2159 switch(hc->hc_HCIType)
2160 {
2161 case HCITYPE_UHCI:
2162 {
2163 ULONG framecnt;
2164 uhciUpdateFrameCounter(hc);
2165 framecnt = hc->hc_FrameCounter;
2166
2167 // NakTimeout
2168 ioreq = (struct IOUsbHWReq *) hc->hc_TDQueue.lh_Head;
2169 while(((struct Node *) ioreq)->ln_Succ)
2170 {
2171 if(ioreq->iouh_Flags & UHFF_NAKTIMEOUT)
2172 {
2173 uqh = (struct UhciQH *) ioreq->iouh_DriverPrivate1;
2174 if(uqh)
2175 {
2176 KPRINTF(1, ("Examining IOReq=%p with UQH=%p\n", ioreq, uqh));
2177 devadrep = (ioreq->iouh_DevAddr<<5) + ioreq->iouh_Endpoint + ((ioreq->iouh_Dir == UHDIR_IN) ? 0x10 : 0);
2178 linkelem = READMEM32_LE(&uqh->uqh_Element);
2179 if(linkelem & UHCI_TERMINATE)
2180 {
2181 KPRINTF(1, ("UQH terminated %08lx\n", linkelem));
2182 if(framecnt > unit->hu_NakTimeoutFrame[devadrep])
2183 {
2184 // give the thing the chance to exit gracefully
2185 KPRINTF(20, ("Terminated? NAK timeout %ld > %ld, IOReq=%p\n", framecnt, unit->hu_NakTimeoutFrame[devadrep], ioreq));
2186 causeint = TRUE;
2187 }
2188 } else {
2189 utd = (struct UhciTD *) (((IPTR)linkelem & UHCI_PTRMASK) - hc->hc_PCIVirtualAdjust - 16); // struct UhciTD starts 16 before physical TD
2190 ctrlstatus = READMEM32_LE(&utd->utd_CtrlStatus);
2191 if(ctrlstatus & UTCF_ACTIVE)
2192 {
2193 if(framecnt > unit->hu_NakTimeoutFrame[devadrep])
2194 {
2195 // give the thing the chance to exit gracefully
2196 KPRINTF(20, ("NAK timeout %ld > %ld, IOReq=%p\n", framecnt, unit->hu_NakTimeoutFrame[devadrep], ioreq));
2197 ctrlstatus &= ~UTCF_ACTIVE;
2198 WRITEMEM32_LE(&utd->utd_CtrlStatus, ctrlstatus);
2199 causeint = TRUE;
2200 }
2201 } else {
2202 if(framecnt > unit->hu_NakTimeoutFrame[devadrep])
2203 {
2204 // give the thing the chance to exit gracefully
2205 KPRINTF(20, ("Terminated? NAK timeout %ld > %ld, IOReq=%p\n", framecnt, unit->hu_NakTimeoutFrame[devadrep], ioreq));
2206 causeint = TRUE;
2207 }
2208 }
2209 }
2210 }
2211 }
2212 ioreq = (struct IOUsbHWReq *) ((struct Node *) ioreq)->ln_Succ;
2213 }
2214
2215 uhciCheckPortStatusChange(hc);
2216 break;
2217 }
2218
2219 case HCITYPE_OHCI:
2220 {
2221 ULONG framecnt;
2222 ohciUpdateFrameCounter(hc);
2223 framecnt = hc->hc_FrameCounter;
2224 // NakTimeout
2225 ioreq = (struct IOUsbHWReq *) hc->hc_TDQueue.lh_Head;
2226 while(((struct Node *) ioreq)->ln_Succ)
2227 {
2228 // Remember the successor because ohciAbortRequest() will move the request to another list
2229 struct IOUsbHWReq *succ = (struct IOUsbHWReq *)ioreq->iouh_Req.io_Message.mn_Node.ln_Succ;
2230
2231 if(ioreq->iouh_Flags & UHFF_NAKTIMEOUT)
2232 {
2233 KPRINTF(1, ("Examining IOReq=%p with OED=%p\n", ioreq, ioreq->iouh_DriverPrivate1));
2234 if (ioreq->iouh_DriverPrivate1)
2235 {
2236 KPRINTF(1, ("CTRL=%04lx, CMD=%01lx, F=%ld, hccaDH=%08lx, hcDH=%08lx, CH=%08lx, CCH=%08lx, IntEn=%08lx\n",
2237 READREG32_LE(hc->hc_RegBase, OHCI_CONTROL),
2238 READREG32_LE(hc->hc_RegBase, OHCI_CMDSTATUS),
2239 READREG32_LE(hc->hc_RegBase, OHCI_FRAMECOUNT),
2240 READMEM32_LE(&hc->hc_OhciHCCA->oha_DoneHead),
2241 READREG32_LE(hc->hc_RegBase, OHCI_DONEHEAD),
2242 READREG32_LE(hc->hc_RegBase, OHCI_CTRL_HEAD_ED),
2243 READREG32_LE(hc->hc_RegBase, OHCI_CTRL_ED),
2244 READREG32_LE(hc->hc_RegBase, OHCI_INTEN)));
2245
2246 devadrep = (ioreq->iouh_DevAddr<<5) + ioreq->iouh_Endpoint + ((ioreq->iouh_Dir == UHDIR_IN) ? 0x10 : 0);
2247 if(framecnt > unit->hu_NakTimeoutFrame[devadrep])
2248 {
2249 // give the thing the chance to exit gracefully
2250 KPRINTF(200, ("HC 0x%p NAK timeout %ld > %ld, IOReq=%p\n", hc, framecnt, unit->hu_NakTimeoutFrame[devadrep], ioreq));
2251 ioreq->iouh_Req.io_Error = UHIOERR_NAKTIMEOUT;
2252 ohciAbortRequest(hc, ioreq);
2253 }
2254 }
2255 }
2256 ioreq = succ;
2257 }
2258 break;
2259 }
2260
2261 case HCITYPE_EHCI:
2262 {
2263 ULONG framecnt;
2264 ehciUpdateFrameCounter(hc);
2265 framecnt = hc->hc_FrameCounter;
2266 // NakTimeout
2267 for(cnt = 0; cnt < 1; cnt++)
2268 {
2269 ioreq = (struct IOUsbHWReq *) (cnt ? hc->hc_PeriodicTDQueue.lh_Head : hc->hc_TDQueue.lh_Head);
2270 while(((struct Node *) ioreq)->ln_Succ)
2271 {
2272 if(ioreq->iouh_Flags & UHFF_NAKTIMEOUT)
2273 {
2274 eqh = (struct EhciQH *) ioreq->iouh_DriverPrivate1;
2275 if(eqh)
2276 {
2277 KPRINTF(1, ("Examining IOReq=%p with EQH=%p\n", ioreq, eqh));
2278 devadrep = (ioreq->iouh_DevAddr<<5) + ioreq->iouh_Endpoint + ((ioreq->iouh_Dir == UHDIR_IN) ? 0x10 : 0);
2279 ctrlstatus = READMEM32_LE(&eqh->eqh_CtrlStatus);
2280 if(ctrlstatus & ETCF_ACTIVE)
2281 {
2282 if(framecnt > unit->hu_NakTimeoutFrame[devadrep])
2283 {
2284 // give the thing the chance to exit gracefully
2285 KPRINTF(20, ("NAK timeout %ld > %ld, IOReq=%p\n", framecnt, unit->hu_NakTimeoutFrame[devadrep], ioreq));
2286 ctrlstatus &= ~ETCF_ACTIVE;
2287 ctrlstatus |= ETSF_HALTED;
2288 WRITEMEM32_LE(&eqh->eqh_CtrlStatus, ctrlstatus);
2289 causeint = TRUE;
2290 }
2291 } else {
2292 if(ctrlstatus & ETCF_READYINTEN)
2293 {
2294 KPRINTF(10, ("INT missed?!? Manually causing it! %08lx, IOReq=%p\n",
2295 ctrlstatus, ioreq));
2296 causeint = TRUE;
2297 }
2298 }
2299 }
2300 }
2301 ioreq = (struct IOUsbHWReq *) ((struct Node *) ioreq)->ln_Succ;
2302 }
2303 }
2304 break;
2305 }
2306
2307 }
2308 if(causeint)
2309 {
2310 SureCause(base, &hc->hc_CompleteInt);
2311 }
2312
2313 hc = (struct PCIController *) hc->hc_Node.ln_Succ;
2314 }
2315
2316 uhwCheckRootHubChanges(unit);
2317
2318 unit->hu_NakTimeoutReq.tr_time.tv_micro = 150*1000;
2319 SendIO((APTR) &unit->hu_NakTimeoutReq);
2320
2321 KPRINTF(1, ("Exit NakTimeoutInt(0x%p)\n", unit));
2322
2323 return FALSE;
2324
2325 AROS_INTFUNC_EXIT
2326 }
2327 /* \\\ */
2328
Mirror of AROS' svn.