workbench/c/CPUInfo/x86_Intel.c

   1 /*
   2     Copyright © 2000, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: Probe installed Intel CPUs and display relevant information
   6     Lang: english
   7 */
   8
   9 /* BIG TO DO - SEPERATE THE INDIVIDUAL PROCESSOR FAMILY "PROBES" INTO RUNTIME SHARED LIBS OR SIMILAR */
  10
  11 /****************************************************************************************************
  12      Currently Supports:
  13
  14         i386 compatable families...
  15             Intel P5/P54C/P55C/P24T/P6/P2/P3/PM/Itanium(IA-64)
  16
  17 *****************************************************************************************************/
  18
  19 #include "x86.h"
  20
  21 /********************************************
  22                          Structures
  23  ********************************************/
  24
  25 #define i386_intel_MAXBRANDS 23
  26 char *i386_intel_Brands[i386_intel_MAXBRANDS] = {
  27     "not supported",
  28     "0.18 µm Intel Celeron processor",
  29     "0.18 µm Intel Pentium III processor",
  30     "0.18 µm Intel Pentium III Xeon processor/0.13 µm Intel Celeron",
  31     "0.13 µm Intel Pentium III processor",
  32     "not supported",
  33     "not supported",
  34     "0.13 µm Intel Celeron mobile processor",
  35     "0.18 µm Intel Pentium 4 processor/0.13 µm Intel Celeron 4 mobile (0F24h)",
  36     "0.13 µm Intel Pentium 4 processor",
  37     "0.18 µm Intel Celeron 4 ",
  38     "0.18 µm Intel Pentium 4 Xeon MP/0.13 µm Intel Pentium 4 Xeon ",
  39     "0.13 µm Intel Pentium 4 Xeon MP",
  40     "not supported",
  41     "0.13 µm Intel Pentium 4 mobile (production)",
  42     "0.13 µm Intel Celeron 4 mobile (0F27h)/0.13 µm Intel Pentium 4 mobile (samples)",
  43     "not supported",
  44     "not supported",
  45     "not supported",
  46     "not supported",
  47     "not supported",
  48     "not supported",
  49     "0.13 µm Intel Pentium M",
  50 };
  51
  52 /********************************************
  53                      Intel CPU Features
  54  ********************************************/
  55
  56 char *Intel_feature_flags[] = {
  57     "FPU    : Floating Point Unit",
  58     "VME    : Virtual 8086 Mode Enhancements",
  59     "DE     : Debugging Extensions",
  60     "PSE    : Page Size Extensions",
  61     "TSC    : Time Stamp Counter",
  62     "MSR    : Model Specific Registers",
  63     "PAE    : Physical Address Extension",
  64     "MCE    : Machine Check Exception",
  65     "CX8    : COMPXCHG8B Instruction",
  66     "APIC   : On-chip Advanced Programmable Interrupt Controller present and enabled",
  67     "10     : Reserved",
  68     "SEP    : Fast System Call",
  69     "MTRR   : Memory Type Range Registers",
  70     "PGE    : PTE Global Flag",
  71     "MCA    : Machine Check Architecture",
  72     "CMOV   : Conditional Move and Compare Instructions",
  73     "FGPAT  : Page Attribute Table",
  74     "PSE-36 : 36-bit Page Size Extension",
  75     "PN     : Processor Serial Number present and enabled",
  76     "CLFSH  : CFLUSH instruction",
  77     "20     : reserved",
  78     "DS     : Debug store",
  79     "ACPI   : Thermal Monitor and Clock Ctrl",
  80     "MMX    : MMX instruction set",
  81     "FXSR   : Fast FP/MMX Streaming SIMD Extensions save/restore",
  82     "SSE    : Streaming SIMD Extensions instruction set",
  83     "SSE2   : SSE2 extensions",
  84     "SS     : Self Snoop",
  85     "HT     : Hyper Threading",
  86     "TM     : Thermal monitor",
  87     "30     : reserved",
  88     "31     : reserved",
  89 };
  90
  91 /********************************************
  92         Intel specific information
  93  ********************************************/
  94
  95 /* Decode Intel TLB and cache info descriptors */
  96
  97 char   *i386_intel_TLB_decode ( int tlb, char *BUFF_STR )
  98 {
  99     tlb &= 0xff;
 100     if(tlb != 0)  sprintf( BUFF_STR,"%02x: ",tlb);
 101
 102     sprintf( BUFF_STR,"        ");
 103
 104     switch ( tlb )
 105     {
 106     case 0:
 107         break;
 108     case 0x1:
 109         sprintf( BUFF_STR,"Instruction TLB: 4KB pages, 4-way set assoc, 32 entries\n" );
 110         break;
 111     case 0x2:
 112         sprintf( BUFF_STR,"Instruction TLB: 4MB pages, 4-way set assoc, 2 entries\n" );
 113         break;
 114     case 0x3:
 115         sprintf( BUFF_STR,"Data TLB: 4KB pages, 4-way set assoc, 64 entries\n" );
 116         break;
 117     case 0x4:
 118         sprintf( BUFF_STR,"Data TLB: 4MB pages, 4-way set assoc, 8 entries\n" );
 119         break;
 120     case 0x6:
 121         sprintf( BUFF_STR,"1st-level instruction cache: 8KB, 4-way set assoc, 32 byte line size\n" );
 122         break;
 123     case 0x8:
 124         sprintf( BUFF_STR,"1st-level instruction cache: 16KB, 4-way set assoc, 32 byte line size\n" );
 125         break;
 126     case 0xa:
 127         sprintf( BUFF_STR,"1st-level data cache: 8KB, 2-way set assoc, 32 byte line size\n" );
 128         break;
 129     case 0xc:
 130         sprintf( BUFF_STR,"1st-level data cache: 16KB, 4-way set assoc, 32 byte line size\n" );
 131         break;
 132
 133
 134     case 0x40:
 135         sprintf( BUFF_STR,"No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache\n" );
 136         break;
 137     case 0x41:
 138         sprintf( BUFF_STR,"2nd-level cache: 128KB, 4-way set assoc, 32 byte line size\n" );
 139         break;
 140     case 0x42:
 141         sprintf( BUFF_STR,"2nd-level cache: 256KB, 4-way set assoc, 32 byte line size\n" );
 142         break;
 143     case 0x43:
 144         sprintf( BUFF_STR,"2nd-level cache: 512KB, 4-way set assoc, 32 byte line size\n" );
 145         break;
 146     case 0x44:
 147         sprintf( BUFF_STR,"2nd-level cache: 1MB, 4-way set assoc, 32 byte line size\n" );
 148         break;
 149     case 0x45:
 150         sprintf( BUFF_STR,"2nd-level cache: 2MB, 4-way set assoc, 32 byte line size\n" );
 151         break;
 152
 153
 154     case 0x50:
 155         sprintf( BUFF_STR,"Instruction TLB: 4KB and 2MB or 4MB pages, 64 entries\n" );
 156         break;
 157     case 0x51:
 158         sprintf( BUFF_STR,"Instruction TLB: 4KB and 2MB or 4MB pages, 128 entries\n" );
 159         break;
 160     case 0x52:
 161         sprintf( BUFF_STR,"Instruction TLB: 4KB and 2MB or 4MB pages, 256 entries\n" );
 162         break;
 163     case 0x5b:
 164         sprintf( BUFF_STR,"Data TLB: 4KB and 4MB pages, 64 entries\n" );
 165         break;
 166     case 0x5c:
 167         sprintf( BUFF_STR,"Data TLB: 4KB and 4MB pages, 128 entries\n" );
 168         break;
 169     case 0x5d:
 170         sprintf( BUFF_STR,"Data TLB: 4KB and 4MB pages, 256 entries\n" );
 171         break;
 172
 173
 174     case 0x66:
 175         sprintf( BUFF_STR,"1st-level data cache: 8KB, 4-way set assoc, 64 byte line size\n" );
 176         break;
 177     case 0x67:
 178         sprintf( BUFF_STR,"1st-level data cache: 16KB, 4-way set assoc, 64 byte line size\n" );
 179         break;
 180     case 0x68:
 181         sprintf( BUFF_STR,"1st-level data cache: 32KB, 4-way set assoc, 64 byte line size\n" );
 182         break;
 183
 184
 185     case 0x70:
 186         sprintf( BUFF_STR,"Trace cache: 12K-micro-op, 4-way set assoc\n" );
 187         break;
 188     case 0x71:
 189         sprintf( BUFF_STR,"Trace cache: 16K-micro-op, 4-way set assoc\n" );
 190         break;
 191     case 0x72:
 192         sprintf( BUFF_STR,"Trace cache: 32K-micro-op, 4-way set assoc\n" );
 193         break;
 194
 195
 196     case 0x79:
 197         sprintf( BUFF_STR,"2nd-level cache: 128KB, 8-way set assoc, sectored, 64 byte line size\n" );
 198         break;
 199     case 0x7a:
 200         sprintf( BUFF_STR,"2nd-level cache: 256KB, 8-way set assoc, sectored, 64 byte line size\n" );
 201         break;
 202     case 0x7b:
 203         sprintf( BUFF_STR,"2nd-level cache: 512KB, 8-way set assoc, sectored, 64 byte line size\n" );
 204         break;
 205     case 0x7c:
 206         sprintf( BUFF_STR,"2nd-level cache: 1MB, 8-way set assoc, sectored, 64 byte line size\n" );
 207         break;
 208
 209
 210     case 0x82:
 211         sprintf( BUFF_STR,"2nd-level cache: 256KB, 8-way set assoc, 32 byte line size\n" );
 212         break;
 213     case 0x83:
 214         sprintf( BUFF_STR,"2nd-level cache: 512KB, 8-way set assoc 32 byte line size\n" );
 215         break;
 216     case 0x84:
 217         sprintf( BUFF_STR,"2nd-level cache: 1MB, 8-way set assoc, 32 byte line size\n" );
 218         break;
 219     case 0x85:
 220         sprintf( BUFF_STR,"2nd-level cache: 2MB, 8-way set assoc, 32 byte line size\n" );
 221         break;
 222
 223
 224     default:
 225         sprintf( BUFF_STR,"unknown TLB/cache descriptor\n" );
 226         break;
 227     }
 228
 229     return BUFF_STR;
 230 }
 231
 232 /********************************************/
 233
 234 void    parse_i386_Intel ( int maxi, struct i386_compat_intern * CPUi386 )
 235 {
 236     struct  CPU_INTERN_DATA *global;
 237     ULONG __unused__        speed, maxei,unused;
 238     int __unused__          family = 0;
 239     char                    *BUFF_STR, *Intel_CPU_NAME, *Intel_CPU_IDENTITY, *Intel_CPU_FEATURES, *Intel_CPU_CACHE, *Intel_CPU_ADDR;
 240     int                     Intel_CPU_NAME_cnt, Intel_CPU_IDENTITY_cnt, Intel_CPU_FEATURES_cnt, Intel_CPU_CACHE_cnt, Intel_CPU_ADDR_cnt;
 241
 242     if ((global = AllocMem(sizeof(struct CPU_INTERN_DATA),MEMF_PUBLIC|MEMF_CLEAR)))
 243     {
 244         Intel_CPU_NAME          = global->CPU_NAME;
 245         Intel_CPU_IDENTITY      = global->CPU_IDENTITY;
 246         Intel_CPU_FEATURES      = global->CPU_FEATURES;
 247         Intel_CPU_CACHE         = global->CPU_CACHE;
 248         Intel_CPU_ADDR          = global->CPU_ADDR;
 249         BUFF_STR                = global->CPU_BUFF;
 250
 251         Intel_CPU_NAME_cnt = Intel_CPU_IDENTITY_cnt = Intel_CPU_FEATURES_cnt = Intel_CPU_CACHE_cnt = Intel_CPU_ADDR_cnt = 0;
 252
 253         Intel_CPU_FEATURES_cnt = AddBufferLine( Intel_CPU_FEATURES_cnt, Intel_CPU_FEATURES, "    Intel-specific functions\n" );
 254
 255         if ( maxi >= 1 )                                                                    /* Family/model/type etc */
 256         {
 257             int clf,apic_id,feature_flags;
 258             int extended_model = -1,extended_family = -1;
 259             unsigned long eax,ebx,edx,unused;
 260             int stepping,model,family,type,reserved,brand,siblings;
 261             int i;
 262
 263             i386_cpuid( 1, eax, ebx, unused, edx );
 264
 265             sprintf( BUFF_STR,"    Version %08lx:\n",eax);
 266             Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 267
 268             stepping    = eax & 0xf;
 269             model       = (eax >> 4) & 0xf;
 270             family      = (eax >> 8) & 0xf;
 271             type        = (eax >> 12) & 0x3;
 272             reserved    = eax >> 14;
 273
 274             clf         = (ebx >> 8) & 0xff;
 275             siblings    = (ebx >> 16) & 0xff;
 276             apic_id     = (ebx >> 24) & 0xff;
 277
 278             feature_flags = edx;
 279
 280             sprintf( BUFF_STR,"    Type [%d] - ",type );
 281             Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 282             switch ( type )
 283             {
 284             case 0:
 285                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Primary");
 286                 break;
 287             case 1:
 288                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Overdrive");
 289                 break;
 290             case 2:
 291                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Secondary");
 292                 break;
 293             case 3:
 294                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Reserved");
 295                 break;
 296             }
 297
 298             sprintf( BUFF_STR," Family [%d] - ",family);
 299             Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 300             switch ( family )
 301             {
 302             case 3:
 303                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "i386" );
 304                 break;
 305             case 4:
 306                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "i486" );
 307                 break;
 308             case 5:
 309                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium" );
 310                 break;
 311             case 6:
 312                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium Pro" );
 313                 break;
 314             case 15:
 315                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium 4" );
 316             }
 317             Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "\n");
 318
 319             if ( family == 15 )
 320             {
 321                 extended_family = (eax >> 20) & 0xff;
 322                 sprintf( BUFF_STR,"    Extended family %d",extended_family);
 323                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 324
 325                 switch ( extended_family )
 326                 {
 327                 case 0:
 328                     Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Intel P4" );
 329                     break;
 330                 case 1:
 331                     Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Intel Itanium 2 (IA-64)" );
 332                     break;
 333                 }
 334             }
 335
 336             sprintf( BUFF_STR,"    Model %d - ",model);
 337             Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 338             switch ( family )
 339             {
 340             case 3:
 341                 break;
 342             case 4:
 343                 switch ( model )
 344                 {
 345                 case 0:
 346                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "486DX-25/33");
 347                         break;
 348                 case 1:
 349                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "486DX-50");
 350                         break;
 351                 case 2:
 352                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "486SX");
 353                         break;
 354                 case 3:
 355                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "486DX2");
 356                         break;
 357                 case 4:
 358                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "486SL");
 359                         break;
 360                 case 5:
 361                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "486SX2");
 362                         break;
 363                 case 7:
 364                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "486DX2-WB (write-back enhanced)");
 365                         break;
 366                 case 8:
 367                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "486DX4");
 368                         break;
 369                 case 9:
 370                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "486DX4-WB (write-back enhanced)");
 371                         break;
 372                 }
 373             break;
 374             case 5:
 375                 switch ( model )
 376                 {
 377                 case 0:
 378                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "P5 A-step");
 379                         break;
 380                 case 1:
 381                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "P5");
 382                         break;
 383                 case 2:
 384                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "P54C");
 385                         break;
 386                 case 3:
 387                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "P24T Overdrive");
 388                         break;
 389                 case 4:
 390                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "P55C");
 391                         break;
 392                 case 7:
 393                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "P54C");
 394                         break;
 395                 case 8:
 396                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "P55C (0.25µm)");
 397                         break;
 398                 }
 399             break;
 400             case 6:
 401                 switch ( model )
 402                 {
 403                 case 0:
 404                     Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium Pro (P6 A-step)");
 405                         break;
 406                 case 1:
 407                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium Pro (P6)");
 408                         break;
 409                 case 3:
 410                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium II Model 3 (0.28 µm)");
 411                         break;
 412                 case 5:
 413                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium II Model 5/Xeon/Celeron (0.25 µm)");
 414                         break;
 415                 case 6:
 416                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Celeron (PII with on-die L2 cache)");
 417                         break;
 418                 case 7:
 419                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium III/Pentium III Xeon external L2 cache (0.25 µm)");
 420                         break;
 421                 case 8:
 422                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium III/Pentium III Xeon with 256 KB on-die L2 cache (0.18 µm)");
 423                         break;
 424                 case 9:
 425                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "PM - with 1 MB on-die L2 cache  (0.13 µm)");
 426                         break;
 427                 case 10:
 428                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium III with 1 or 2 MB on-die L2 cache (0.18 µm)");
 429                         break;
 430                 case 11:
 431                         Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium III with 256 or 512 KB on-die L2 cache (0.13 µm)");
 432                         break;
 433                 }
 434             break;
 435                     case 15:
 436                             switch ( model )
 437                 {
 438                             case 0:
 439                             case 1:
 440                     Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium 4/Celeron (0.18)");
 441                                     break;
 442                             case 2:
 443                     Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium 4/Celeron (0.13)");
 444                     break;
 445                             case 3:
 446                     Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "Pentium 4 (0.09)");
 447                     break;
 448                             }
 449                     break;
 450
 451             }
 452             Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "\n");
 453
 454             if ( model == 15 )
 455             {
 456                 extended_model = (eax >> 16) & 0xf;
 457                 sprintf( BUFF_STR,"    Extended model %d\n",extended_model);
 458                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 459             }
 460
 461             sprintf( BUFF_STR,"    Stepping %d\n",stepping);
 462             Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 463
 464             sprintf( BUFF_STR,"    Reserved %d\n\n",reserved);
 465             Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 466
 467             brand = ebx & 0xff;
 468             if ( brand > 0 )
 469             {
 470                 sprintf( BUFF_STR,"    Brand index: %d [",brand);
 471                 Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 472                 if (brand  < i386_intel_MAXBRANDS)
 473                 {
 474                     sprintf( BUFF_STR,"%s]\n",i386_intel_Brands[brand]);
 475                     Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, BUFF_STR);
 476                 }
 477                 else Intel_CPU_IDENTITY_cnt = AddBufferLine(Intel_CPU_IDENTITY_cnt, Intel_CPU_IDENTITY, "not in table]\n");
 478             }
 479
 480             i386_cpuid( 0x80000000, eax, ebx, unused, edx );
 481             if ( eax & 0x80000000 )                                                            /* Extended feature/signature bits supported */
 482             {
 483                 int maxe = eax;
 484                 if( maxe >= 0x80000004 )
 485                 {
 486                         int i;
 487
 488                         Intel_CPU_NAME_cnt = AddBufferLine(Intel_CPU_NAME_cnt, Intel_CPU_NAME, "    Extended brand string: \"" );
 489                         for( i=0x80000002; i<=0x80000004 ;i++ )
 490                     {
 491                             unsigned long eax,ebx,ecx,edx;
 492
 493                             i386_cpuid(i,eax,ebx,ecx,edx);
 494                             Intel_CPU_NAME_cnt = i386_sprintregs(Intel_CPU_NAME_cnt, Intel_CPU_NAME, eax,ebx,ecx,edx);
 495                         }
 496                         Intel_CPU_NAME_cnt = AddBufferLine(Intel_CPU_NAME_cnt, Intel_CPU_NAME, "\"\n");
 497                 }
 498             }
 499             if ( clf )
 500             {
 501                 sprintf( BUFF_STR,"    CLFLUSH instruction cache line size: %d\n", clf );
 502                 Intel_CPU_FEATURES_cnt = AddBufferLine(Intel_CPU_FEATURES_cnt, Intel_CPU_FEATURES, BUFF_STR);
 503             }
 504
 505             if ( apic_id )
 506             {
 507                 sprintf( BUFF_STR,"    Initial APIC ID: %d\n", apic_id );
 508                 Intel_CPU_FEATURES_cnt = AddBufferLine(Intel_CPU_FEATURES_cnt, Intel_CPU_FEATURES, BUFF_STR);
 509             }
 510
 511             if ( feature_flags & (1<<28) )
 512             {
 513                 sprintf( BUFF_STR,"    Hyper threading siblings: %d\n", siblings );
 514                 Intel_CPU_FEATURES_cnt = AddBufferLine(Intel_CPU_FEATURES_cnt, Intel_CPU_FEATURES, BUFF_STR);
 515             }
 516
 517             sprintf( BUFF_STR,"\n    Feature flags [%08x]:\n", feature_flags );
 518             Intel_CPU_FEATURES_cnt = AddBufferLine(Intel_CPU_FEATURES_cnt, Intel_CPU_FEATURES, BUFF_STR);
 519             for(i=0;i<32;i++)
 520             {
 521                 if( feature_flags & (1<<i) )
 522                 {
 523                     sprintf( BUFF_STR,"        %s\n", Intel_feature_flags[i] );
 524                     Intel_CPU_FEATURES_cnt = AddBufferLine(Intel_CPU_FEATURES_cnt, Intel_CPU_FEATURES, BUFF_STR);
 525                 }
 526             }
 527             Intel_CPU_FEATURES_cnt = AddBufferLine(Intel_CPU_FEATURES_cnt, Intel_CPU_FEATURES, "\n");
 528         }
 529
 530         if ( maxi >= 2 )                                                                /* Decode TLB and cache info */
 531         {
 532             int ntlb,i;
 533
 534             ntlb = 255;
 535             Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, "    TLB and cache info:\n");
 536             for( i=0; i<ntlb ;i++ )
 537             {
 538                 unsigned long eax,ebx,ecx,edx;
 539
 540                 i386_cpuid(2,eax,ebx,ecx,edx);
 541                 ntlb =  eax & 0xff;
 542                 Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( eax >> 8, BUFF_STR ));
 543                 Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( eax >> 16, BUFF_STR ));
 544                 Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( eax >> 24, BUFF_STR ));
 545
 546                 if (( ebx & 0x80000000 ) == 0 )
 547                 {
 548                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( ebx, BUFF_STR ));
 549                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( ebx >> 8, BUFF_STR ));
 550                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( ebx >> 16, BUFF_STR ));
 551                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( ebx >> 24, BUFF_STR ));
 552                 }
 553                 if (( ecx & 0x80000000 ) == 0 )
 554                 {
 555                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( ecx, BUFF_STR ));
 556                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( ecx >> 8, BUFF_STR ));
 557                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( ecx >> 16, BUFF_STR ));
 558                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( ecx >> 24, BUFF_STR ));
 559                 }
 560                 if (( edx & 0x80000000 ) == 0 )
 561                 {
 562                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( edx, BUFF_STR ));
 563                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( edx >> 8, BUFF_STR ));
 564                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( edx >> 16, BUFF_STR ));
 565                         Intel_CPU_CACHE_cnt = AddBufferLine(Intel_CPU_CACHE_cnt, Intel_CPU_CACHE, i386_intel_TLB_decode( edx >> 24, BUFF_STR ));
 566                 }
 567             }
 568         }
 569
 570         if ( maxi >= 3 )                                                                   /* Pentium III CPU serial number */
 571         {
 572             unsigned long signature,unused,ecx,edx;
 573
 574             i386_cpuid(1,signature,unused,unused,unused);
 575             i386_cpuid(3,unused,unused,ecx,edx);
 576
 577             Intel_CPU_NAME_cnt = AddBufferLine(Intel_CPU_NAME_cnt, Intel_CPU_NAME, "    Processor serial: ");
 578
 579             sprintf( BUFF_STR,"%04lX",signature >> 16);
 580             Intel_CPU_NAME_cnt = AddBufferLine(Intel_CPU_NAME_cnt, Intel_CPU_NAME, BUFF_STR);
 581             sprintf( BUFF_STR,"-%04lX",signature & 0xffff);
 582             Intel_CPU_NAME_cnt = AddBufferLine(Intel_CPU_NAME_cnt, Intel_CPU_NAME, BUFF_STR);
 583             sprintf( BUFF_STR,"-%04lX",edx >> 16);
 584             Intel_CPU_NAME_cnt = AddBufferLine(Intel_CPU_NAME_cnt, Intel_CPU_NAME, BUFF_STR);
 585             sprintf( BUFF_STR,"-%04lX",edx & 0xffff);
 586             Intel_CPU_NAME_cnt = AddBufferLine(Intel_CPU_NAME_cnt, Intel_CPU_NAME, BUFF_STR);
 587             sprintf( BUFF_STR,"-%04lX",ecx >> 16);
 588             Intel_CPU_NAME_cnt = AddBufferLine(Intel_CPU_NAME_cnt, Intel_CPU_NAME, BUFF_STR);
 589             sprintf( BUFF_STR,"-%04lX\n",ecx & 0xffff);
 590             Intel_CPU_NAME_cnt = AddBufferLine(Intel_CPU_NAME_cnt, Intel_CPU_NAME, BUFF_STR);
 591         }
 592
 593     /** DUMP ALL THE INFORMATION WE HAVE GATHERED **/
 594
 595         if ( Intel_CPU_NAME_cnt > 0 ) printf( Intel_CPU_NAME );             /* CPUs Retail Name     */
 596
 597         speed = i386_approx_mhz();
 598
 599         /* TODO : Calculate FSB ..     */
 600
 601         if ( Intel_CPU_IDENTITY_cnt > 0 ) printf( Intel_CPU_IDENTITY );     /* CPUs Internal Name   */
 602         if ( Intel_CPU_FEATURES_cnt > 0 ) printf( Intel_CPU_FEATURES );     /* CPUs Feature Set     */
 603         if ( Intel_CPU_ADDR_cnt > 0 ) printf( Intel_CPU_ADDR );             /* CPUs Address Range   */
 604         if ( Intel_CPU_CACHE_cnt > 0 ) printf( Intel_CPU_CACHE );           /* CPUs Cache Details   */
 605     }
 606     else
 607     {
 608         printf( "ERROR: Couldn't allocate memory to parse CPU information .." );
 609         return;
 610     }
 611     FreeMem(global,sizeof(struct CPU_INTERN_DATA));
 612 }