workbench/devs/AHI/Drivers/CMI8738/regs.h

   1 /*      $NetBSD: cmpcireg.h,v 1.6 2003/12/04 13:57:31 keihan Exp $      */
   2
   3 /*
   4  * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Takuya SHIOZAKI <tshiozak@NetBSD.org> .
   9  *
  10  * This code is derived from software contributed to The NetBSD Foundation
  11  * by ITOH Yasufumi.
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  * 1. Redistributions of source code must retain the above copyright
  17  *    notice, this list of conditions and the following disclaimer.
  18  * 2. Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  */
  35
  36 /* C-Media CMI8x38 Audio Chip Support */
  37
  38 #ifndef _DEV_PCI_CMPCIREG_H_
  39 #define _DEV_PCI_CMPCIREG_H_ (1)
  40
  41 /*
  42  * PCI Configuration Registers
  43  */
  44
  45 #define CMPCI_PCI_IOBASEREG     (PCI_MAPREG_START)
  46
  47
  48 /*
  49  * I/O Space
  50  */
  51
  52 #define CMPCI_REG_FUNC_0                0x00
  53 #  define CMPCI_REG_CH0_DIR             0x00000001
  54 #  define CMPCI_REG_CH1_DIR             0x00000002
  55 #  define CMPCI_REG_CH0_PAUSE           0x00000004
  56 #  define CMPCI_REG_CH1_PAUSE           0x00000008
  57 #  define CMPCI_REG_CH0_ENABLE          0x00010000
  58 #  define CMPCI_REG_CH1_ENABLE          0x00020000
  59 #  define CMPCI_REG_CH0_RESET           0x00040000
  60 #  define CMPCI_REG_CH1_RESET           0x00080000
  61
  62 #define CMPCI_REG_FUNC_1                0x04
  63 #  define CMPCI_REG_ZV_ENABLE          0x00000001
  64 #  define CMPCI_REG_JOY_ENABLE          0x00000002
  65 #  define CMPCI_REG_UART_ENABLE         0x00000004
  66 #  define CMPCI_REG_LEGACY_ENABLE       0x00000008
  67 #  define CMPCI_REG_BREQ                0x00000010
  68 #  define CMPCI_REG_MCBINTR_ENABLE      0x00000020
  69 #  define CMPCI_REG_SPDIFOUT_DAC        0x00000040
  70 #  define CMPCI_REG_SPDIF_LOOP          0x00000080
  71 #  define CMPCI_REG_SPDIF0_ENABLE       0x00000100
  72 #  define CMPCI_REG_SPDIF1_ENABLE       0x00000200
  73 #  define CMPCI_REG_DAC_FS_SHIFT        10
  74 #  define CMPCI_REG_DAC_FS_MASK         0x00000007
  75 #  define CMPCI_REG_ADC_FS_SHIFT        13
  76 #  define CMPCI_REG_ADC_FS_MASK         0x00000007
  77
  78 #define CMPCI_REG_CHANNEL_FORMAT        0x08
  79 #  define CMPCI_REG_SPDIN_PHASE         0x80
  80 #  define CMPCI_REG_CH0_FORMAT_SHIFT    0
  81 #  define CMPCI_REG_CH0_FORMAT_MASK     0x00000003
  82 #  define CMPCI_REG_CH1_FORMAT_SHIFT    2
  83 #  define CMPCI_REG_CH1_FORMAT_MASK     0x00000003
  84 #  define CMPCI_REG_FORMAT_MONO         0x00000000
  85 #  define CMPCI_REG_FORMAT_STEREO       0x00000001
  86 #  define CMPCI_REG_FORMAT_8BIT         0x00000000
  87 #  define CMPCI_REG_FORMAT_16BIT        0x00000002
  88 #  define CMPCI_REG_VERSION_37          0x01000000 // hardware revision 37
  89
  90 #define CMPCI_REG_INTR_CTRL             0x0c
  91 #  define CMPCI_REG_CH0_INTR_ENABLE     0x00010000
  92 #  define CMPCI_REG_CH1_INTR_ENABLE     0x00020000
  93 #  define CMPCI_REG_TDMA_INTR_ENABLE    0x00040000
  94 #  define CMPCI_REG_VERSION_MASK        0xFF000000 // version number mask (bits 31:24)
  95 #  define CMPCI_REG_VERSION_39          0x04000000 // revision 39
  96 #  define CMPCI_REG_VERSION_39B         0x01000000 // 6 channel version of revision 39
  97 #  define CMPCI_REG_VERSION_55          0x08000000 // revision 55
  98 #  define CMPCI_REG_VERSION_68          0x20000000 // revision 68 (8768)
  99
 100 #define CMPCI_REG_INTR_STATUS           0x10
 101 #  define CMPCI_REG_CH0_INTR            0x00000001
 102 #  define CMPCI_REG_CH1_INTR            0x00000002
 103 #  define CMPCI_REG_CH0_BUSY            0x00000004
 104 #  define CMPCI_REG_CH1_BUSY            0x00000008
 105 #  define CMPCI_REG_LEGACY_STEREO       0x00000010
 106 #  define CMPCI_REG_LEGACY_HDMA         0x00000020
 107 #  define CMPCI_REG_DMASTAT             0x00000040
 108 #  define CMPCI_REG_XDO46               0x00000080
 109 #  define CMPCI_REG_HTDMA_INTR          0x00004000
 110 #  define CMPCI_REG_LTDMA_INTR          0x00008000
 111 #  define CMPCI_REG_UART_INTR           0x00010000
 112 #  define CMPCI_REG_MCB_INTR            0x04000000
 113 #  define CMPCI_REG_VCO                 0x08000000
 114 #  define CMPCI_REG_ANY_INTR            0x80000000
 115
 116 #define CMPCI_REG_LEGACY_CTRL           0x14
 117 #  define CMPCI_REG_LEGACY_SPDIF_ENABLE 0x00200000 // wave/pcm to /spdif out: causes distortion
 118 #  define CMPCI_REG_SPDIF_COPYRIGHT     0x00400000
 119 #  define CMPCI_REG_XSPDIF_ENABLE       0x00800000 // turns on the red light
 120 #  define CMPCI_REG_FMSEL_SHIFT         24
 121 #  define CMPCI_REG_FMSEL_MASK          0x00000003
 122 #  define CMPCI_REG_VSBSEL_SHIFT        26
 123 #  define CMPCI_REG_VSBSEL_MASK         0x00000003
 124 #  define CMPCI_REG_VMPUSEL_SHIFT       29
 125 #  define CMPCI_REG_VMPUSEL_MASK        0x00000003
 126 #  define CMPCI_REG_ENABLE_5_1          0x00008000
 127
 128 #define CMPCI_REG_MISC                  0x18
 129 #  define CMPCI_REG_2ND_SPDIFIN         0x00000100
 130 #  define CMPCI_REG_SPDIFOUT_48K        0x00008000
 131 #  define CMPCI_REG_FM_ENABLE           0x00080000
 132 #  define CMPCI_REG_SPDFLOOPI           0x00100000
 133 #  define CMPCI_REG_SPDIF48K            0x01000000
 134 #  define CMPCI_REG_5V                  0x02000000
 135 #  define CMPCI_REG_N4SPK3D             0x04000000
 136 #  define CMPCI_REG_BUS_AND_DSP_RESET   0x40000000
 137 #  define CMPCI_REG_POWER_DOWN          0x80000000
 138
 139 #define CMPCI_REG_SBDATA                0x22
 140 #define CMPCI_REG_SBADDR                0x23
 141 #  define CMPCI_SB16_MIXER_RESET        0x00
 142
 143 #  define CMPCI_SB16_MIXER_MASTER_L     0x30 // mixer levels for output
 144 #  define CMPCI_SB16_MIXER_MASTER_R     0x31
 145 #  define CMPCI_SB16_MIXER_VOICE_L      0x32
 146 #  define CMPCI_SB16_MIXER_VOICE_R      0x33
 147 #  define CMPCI_SB16_MIXER_FM_L         0x34
 148 #  define CMPCI_SB16_MIXER_FM_R         0x35
 149 #  define CMPCI_SB16_MIXER_CDDA_L       0x36
 150 #  define CMPCI_SB16_MIXER_CDDA_R       0x37
 151 #  define CMPCI_SB16_MIXER_LINE_L       0x38
 152 #  define CMPCI_SB16_MIXER_LINE_R       0x39
 153 #  define CMPCI_SB16_MIXER_MIC          0x3A
 154 #    define CMPCI_SB16_MIXER_VALBITS            5
 155 #  define CMPCI_SB16_MIXER_SPEAKER      0x3B
 156 #    define CMPCI_SB16_MIXER_SPEAKER_VALBITS    2
 157
 158 #  define CMPCI_SB16_MIXER_OUTMIX       0x3C  // mutes for output
 159 #    define CMPCI_SB16_SW_MIC           0x01
 160 #    define CMPCI_SB16_SW_CD_R          0x02
 161 #    define CMPCI_SB16_SW_CD_L          0x04
 162 #    define CMPCI_SB16_SW_CD            (CMPCI_SB16_SW_CD_L|CMPCI_SB16_SW_CD_R)
 163 #    define CMPCI_SB16_SW_LINE_R        0x08
 164 #    define CMPCI_SB16_SW_LINE_L        0x10
 165 #    define CMPCI_SB16_SW_LINE  (CMPCI_SB16_SW_LINE_L|CMPCI_SB16_SW_LINE_R)
 166 #    define CMPCI_SB16_SW_FM_R          0x20
 167 #    define CMPCI_SB16_SW_FM_L          0x40
 168 #    define CMPCI_SB16_SW_FM            (CMPCI_SB16_SW_FM_L|CMPCI_SB16_SW_FM_R)
 169
 170 #  define CMPCI_SB16_MIXER_ADCMIX_L     0x3D // select/mute recording inputs
 171 #  define CMPCI_SB16_MIXER_ADCMIX_R     0x3E
 172 #    define CMPCI_SB16_MIXER_FM_SRC_R   0x20
 173 #    define CMPCI_SB16_MIXER_LINE_SRC_R 0x08
 174 #    define CMPCI_SB16_MIXER_CD_SRC_R   0x02
 175 #    define CMPCI_SB16_MIXER_MIC_SRC    0x01
 176 #    define CMPCI_SB16_MIXER_SRC_R_TO_L(v)      ((v) << 1)
 177
 178 #  define CMPCI_SB16_MIXER_L_TO_R(addr) ((addr)+1)
 179
 180 #  define CMPCI_ADJUST_MIC_GAIN(sc, x)  cmpci_adjust((x), 0xf8)
 181 #  define CMPCI_ADJUST_GAIN(sc, x)      cmpci_adjust((x), 0xf8)
 182 #  define CMPCI_ADJUST_2_GAIN(sc, x)    cmpci_adjust((x), 0xc0)
 183
 184 #define CMPCI_REG_MIXER24               0x24
 185 #  define CMPCI_REG_SPDIN_MONITOR       0x01
 186 #  define CMPCI_REG_SURROUND            0x02
 187 #  define CMPCI_REG_INDIVIDUAL          0x20
 188 #  define CMPCI_REG_REVERSE_FR          0x10
 189 #  define CMPCI_REG_FMMUTE              0x80
 190 #  define CMPCI_REG_WSMUTE              0x40
 191 #  define CMPCI_REG_WAVEINL             0x08
 192 #  define CMPCI_REG_WAVEINR             0x04
 193
 194 #define CMPCI_REG_MIXER25               0x25
 195 #  define CMPCI_REG_RAUXREN             0x80
 196 #  define CMPCI_REG_RAUXLEN             0x40
 197 #  define CMPCI_REG_VAUXRM              0x20    /* 0: mute, 1: unmute */
 198 #  define CMPCI_REG_VAUXLM              0x10
 199 #  define CMPCI_REG_VADMIC              0x0E
 200 #  define CMPCI_REG_MICGAINZ            0x01    /* 1: disable preamp */
 201
 202 #  define CMPCI_ADJUST_ADMIC_GAIN(sc, x)        (cmpci_adjust((x), 0xe0) >> 5)
 203 #  define CMPCI_REG_ADMIC_VALBITS       3
 204 #  define CMPCI_REG_ADMIC_MASK          0x07
 205 #  define CMPCI_REG_ADMIC_SHIFT         0x01
 206
 207 /* Note that the doc tells a lie */
 208 #define CMPCI_REG_MIXER_AUX             0x26
 209 #  define CMPCI_ADJUST_AUX_GAIN(sc, l, r)       \
 210         (cmpci_adjust((l), 0xc0) >> 4 | cmpci_adjust((r), 0xc0))
 211 #  define CMPCI_REG_AUX_VALBITS 4
 212
 213 #define CMPCI_REG_MPU_BASE              0x40
 214 #define CMPCI_REG_MPU_SIZE              0x10
 215 #define CMPCI_REG_FM_BASE               0x50
 216 #define CMPCI_REG_FM_SIZE               0x10
 217
 218 #define CMPCI_REG_DMA0_BASE             0x80
 219 #define CMPCI_REG_DMA0_LENGTH           0x84 // total sample frames - 1 allocated
 220 #define CMPCI_REG_DMA0_INTLEN           0x86 // nr of sample frames - 1 before an interrupt occurs
 221 #define CMPCI_REG_DMA1_BASE             0x88
 222 #define CMPCI_REG_DMA1_LENGTH           0x8C
 223 #define CMPCI_REG_DMA1_INTLEN           0x8E
 224
 225
 226 /* sample rate */
 227 #define CMPCI_REG_RATE_5512             0
 228 #define CMPCI_REG_RATE_11025            1
 229 #define CMPCI_REG_RATE_22050            2
 230 #define CMPCI_REG_RATE_44100            3
 231 #define CMPCI_REG_RATE_8000             4
 232 #define CMPCI_REG_RATE_16000            5
 233 #define CMPCI_REG_RATE_32000            6
 234 #define CMPCI_REG_RATE_48000            7
 235 #define CMPCI_REG_NUMRATE               8
 236
 237
 238 /*
 239  * Mixer device
 240  *
 241  * Note that cmpci_query_devinfo() is optimized depending on
 242  * the order of this.  Be careful if you change the values.
 243  */
 244 #define CMPCI_DAC_VOL                   0       /* inputs.dac */
 245 #define CMPCI_FM_VOL                    1       /* inputs.fmsynth */
 246 #define CMPCI_CD_VOL                    2       /* inputs.cd */
 247 #define CMPCI_LINE_IN_VOL               3       /* inputs.line */
 248 #define CMPCI_AUX_IN_VOL                4       /* inputs.aux */
 249 #define CMPCI_MIC_VOL                   5       /* inputs.mic */
 250
 251 #define CMPCI_DAC_MUTE                  6       /* inputs.dac.mute */
 252 #define CMPCI_FM_MUTE                   7       /* inputs.fmsynth.mute */
 253 #define CMPCI_CD_MUTE                   8       /* inputs.cd.mute */
 254 #define CMPCI_LINE_IN_MUTE              9       /* inputs.line.mute */
 255 #define CMPCI_AUX_IN_MUTE               10      /* inputs.aux.mute */
 256 #define CMPCI_MIC_MUTE                  11      /* inputs.mic.mute */
 257
 258 #define CMPCI_MIC_PREAMP                12      /* inputs.mic.preamp */
 259 #define CMPCI_PCSPEAKER                 13      /* inputs.speaker */
 260
 261 #define CMPCI_RECORD_SOURCE             14      /* record.source */
 262 #define CMPCI_MIC_RECVOL                15      /* record.mic */
 263
 264 #define CMPCI_PLAYBACK_MODE             16      /* playback.mode */
 265 #define CMPCI_SPDIF_IN_SELECT           17      /* spdif.input */
 266 #define CMPCI_SPDIF_IN_PHASE            18      /* spdif.input.phase */
 267 #define CMPCI_SPDIF_LOOP                19      /* spdif.output */
 268 #define CMPCI_SPDIF_OUT_PLAYBACK        20      /* spdif.output.playback */
 269 #define CMPCI_SPDIF_OUT_VOLTAGE         21      /* spdif.output.voltage */
 270 #define CMPCI_MONITOR_DAC               22      /* spdif.monitor */
 271
 272 #define CMPCI_MASTER_VOL                23      /* outputs.master */
 273 #define CMPCI_REAR                      24      /* outputs.rear */
 274 #define CMPCI_INDIVIDUAL                25      /* outputs.rear.individual */
 275 #define CMPCI_REVERSE                   26      /* outputs.rear.reverse */
 276 #define CMPCI_SURROUND                  27      /* outputs.surround */
 277
 278 #define CMPCI_NDEVS                     28
 279
 280 #define CMPCI_INPUT_CLASS               28
 281 #define CMPCI_OUTPUT_CLASS              29
 282 #define CMPCI_RECORD_CLASS              30
 283 #define CMPCI_PLAYBACK_CLASS            31
 284 #define CMPCI_SPDIF_CLASS               32
 285
 286
 287 #define CMPCI_LEFT      0
 288 #define CMPCI_RIGHT     1
 289 #define CMPCI_LR        0
 290
 291 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
 292 #define CM_CHB3D                0x20000000      /* 4 channels */
 293
 294
 295
 296 #endif /* _DEV_PCI_CMPCIREG_H_ */
 297
 298 /* end of file */
 299