workbench/devs/AHI/Drivers/EMU10kx/8010.h

   1 /*
   2  **********************************************************************
   3  *     8010.h
   4  *     Copyright 1999-2001 Creative Labs, Inc.
   5  *
   6  **********************************************************************
   7  *
   8  *     Date                 Author          Summary of changes
   9  *     ----                 ------          ------------------
  10  *     October 20, 1999     Bertrand Lee    base code release
  11  *     November 2, 1999     Alan Cox        Cleaned of 8bit chars, DOS
  12  *                                          line endings
  13  *     December 8, 1999     Jon Taylor      Added lots of new register info
  14  *     May 16, 2001         Daniel Bertrand Added unofficial DBG register info
  15  *     Oct-Nov 2001         D.B.            Added unofficial Audigy registers
  16  *
  17  **********************************************************************
  18  *
  19  *     This program is free software; you can redistribute it and/or
  20  *     modify it under the terms of the GNU General Public License as
  21  *     published by the Free Software Foundation; either version 2 of
  22  *     the License, or (at your option) any later version.
  23  *
  24  *     This program is distributed in the hope that it will be useful,
  25  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  *     GNU General Public License for more details.
  28  *
  29  *     You should have received a copy of the GNU General Public
  30  *     License along with this program; if not, write to the Free
  31  *     Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
  32  *     USA.
  33  *
  34  *
  35  **********************************************************************
  36  */
  37
  38
  39 #ifndef _8010_H
  40 #define _8010_H
  41
  42 //#include <linux/types.h>
  43
  44 // Driver version:
  45 #define MAJOR_VER 0
  46 #define MINOR_VER 20
  47 #define DRIVER_VERSION "0.20a"
  48
  49
  50 // Audigy specify registers are prefixed with 'A_'
  51
  52 /************************************************************************************************/
  53 /* PCI function 0 registers, address = <val> + PCIBASE0                                         */
  54 /************************************************************************************************/
  55
  56 #define PTR                     0x00            /* Indexed register set pointer register        */
  57                                                 /* NOTE: The CHANNELNUM and ADDRESS words can   */
  58                                                 /* be modified independently of each other.     */
  59 #define PTR_CHANNELNUM_MASK     0x0000003f      /* For each per-channel register, indicates the */
  60                                                 /* channel number of the register to be         */
  61                                                 /* accessed.  For non per-channel registers the */
  62                                                 /* value should be set to zero.                 */
  63 #define PTR_ADDRESS_MASK        0x07ff0000      /* Register index                               */
  64
  65 #define DATA                    0x04            /* Indexed register set data register           */
  66
  67 #define IPR                     0x08            /* Global interrupt pending register            */
  68                                                 /* Clear pending interrupts by writing a 1 to   */
  69                                                 /* the relevant bits and zero to the other bits */
  70
  71 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1)                   */
  72 #define A_IPR_MIDITRANSBUFEMPTY2        0x10000000      /* MIDI UART transmit buffer empty              */
  73 #define A_IPR_MIDIRECVBUFEMPTY2 0x08000000      /* MIDI UART receive buffer empty               */
  74
  75 #define IPR_SAMPLERATETRACKER   0x01000000      /* Sample rate tracker lock status change       */
  76 #define IPR_FXDSP               0x00800000      /* Enable FX DSP interrupts                     */
  77 #define IPR_FORCEINT            0x00400000      /* Force Sound Blaster interrupt                */
  78 #define IPR_PCIERROR            0x00200000      /* PCI bus error                                */
  79 #define IPR_VOLINCR             0x00100000      /* Volume increment button pressed              */
  80 #define IPR_VOLDECR             0x00080000      /* Volume decrement button pressed              */
  81 #define IPR_MUTE                0x00040000      /* Mute button pressed                          */
  82 #define IPR_MICBUFFULL          0x00020000      /* Microphone buffer full                       */
  83 #define IPR_MICBUFHALFFULL      0x00010000      /* Microphone buffer half full                  */
  84 #define IPR_ADCBUFFULL          0x00008000      /* ADC buffer full                              */
  85 #define IPR_ADCBUFHALFFULL      0x00004000      /* ADC buffer half full                         */
  86 #define IPR_EFXBUFFULL          0x00002000      /* Effects buffer full                          */
  87 #define IPR_EFXBUFHALFFULL      0x00001000      /* Effects buffer half full                     */
  88 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800      /* GPSPDIF channel status change                */
  89 #define IPR_CDROMSTATUSCHANGE   0x00000400      /* CD-ROM channel status change                 */
  90 #define IPR_INTERVALTIMER       0x00000200      /* Interval timer terminal count                */
  91 #define IPR_MIDITRANSBUFEMPTY   0x00000100      /* MIDI UART transmit buffer empty              */
  92 #define IPR_MIDIRECVBUFEMPTY    0x00000080      /* MIDI UART receive buffer empty               */
  93 #define IPR_CHANNELLOOP         0x00000040      /* One or more channel loop interrupts pending  */
  94 #define IPR_CHANNELNUMBERMASK   0x0000003f      /* When IPR_CHANNELLOOP is set, indicates the   */
  95                                                 /* Highest set channel in CLIPL or CLIPH.  When */
  96                                                 /* IP is written with CL set, the bit in CLIPL  */
  97                                                 /* or CLIPH corresponding to the CIN value      */
  98                                                 /* written will be cleared.                     */
  99 #define A_IPR_MIDITRANSBUFEMPTY1        IPR_MIDITRANSBUFEMPTY   /* MIDI UART transmit buffer empty              */
 100 #define A_IPR_MIDIRECVBUFEMPTY1 IPR_MIDIRECVBUFEMPTY    /* MIDI UART receive buffer empty               */
 101
 102
 103
 104 #define INTE                    0x0c            /* Interrupt enable register                    */
 105 #define INTE_VIRTUALSB_MASK     0xc0000000      /* Virtual Soundblaster I/O port capture        */
 106 #define INTE_VIRTUALSB_220      0x00000000      /* Capture at I/O base address 0x220-0x22f      */
 107 #define INTE_VIRTUALSB_240      0x40000000      /* Capture at I/O base address 0x240            */
 108 #define INTE_VIRTUALSB_260      0x80000000      /* Capture at I/O base address 0x260            */
 109 #define INTE_VIRTUALSB_280      0xc0000000      /* Capture at I/O base address 0x280            */
 110 #define INTE_VIRTUALMPU_MASK    0x30000000      /* Virtual MPU I/O port capture                 */
 111 #define INTE_VIRTUALMPU_300     0x00000000      /* Capture at I/O base address 0x300-0x301      */
 112 #define INTE_VIRTUALMPU_310     0x10000000      /* Capture at I/O base address 0x310            */
 113 #define INTE_VIRTUALMPU_320     0x20000000      /* Capture at I/O base address 0x320            */
 114 #define INTE_VIRTUALMPU_330     0x30000000      /* Capture at I/O base address 0x330            */
 115 #define INTE_MASTERDMAENABLE    0x08000000      /* Master DMA emulation at 0x000-0x00f          */
 116 #define INTE_SLAVEDMAENABLE     0x04000000      /* Slave DMA emulation at 0x0c0-0x0df           */
 117 #define INTE_MASTERPICENABLE    0x02000000      /* Master PIC emulation at 0x020-0x021          */
 118 #define INTE_SLAVEPICENABLE     0x01000000      /* Slave PIC emulation at 0x0a0-0x0a1           */
 119 #define INTE_VSBENABLE          0x00800000      /* Enable virtual Soundblaster                  */
 120 #define INTE_ADLIBENABLE        0x00400000      /* Enable AdLib emulation at 0x388-0x38b        */
 121 #define INTE_MPUENABLE          0x00200000      /* Enable virtual MPU                           */
 122 #define INTE_FORCEINT           0x00100000      /* Continuously assert INTAN                    */
 123
 124 #define INTE_MRHANDENABLE       0x00080000      /* Enable the "Mr. Hand" logic                  */
 125                                                 /* NOTE: There is no reason to use this under   */
 126                                                 /* Linux, and it will cause odd hardware        */
 127                                                 /* behavior and possibly random segfaults and   */
 128                                                 /* lockups if enabled.                          */
 129
 130 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1)                   */
 131 #define A_INTE_MIDITXENABLE2    0x00020000      /* Enable MIDI transmit-buffer-empty interrupts */
 132 #define A_INTE_MIDIRXENABLE2    0x00010000      /* Enable MIDI receive-buffer-empty interrupts  */
 133
 134
 135 #define INTE_SAMPLERATETRACKER  0x00002000      /* Enable sample rate tracker interrupts        */
 136                                                 /* NOTE: This bit must always be enabled        */
 137 #define INTE_FXDSPENABLE        0x00001000      /* Enable FX DSP interrupts                     */
 138 #define INTE_PCIERRORENABLE     0x00000800      /* Enable PCI bus error interrupts              */
 139 #define INTE_VOLINCRENABLE      0x00000400      /* Enable volume increment button interrupts    */
 140 #define INTE_VOLDECRENABLE      0x00000200      /* Enable volume decrement button interrupts    */
 141 #define INTE_MUTEENABLE         0x00000100      /* Enable mute button interrupts                */
 142 #define INTE_MICBUFENABLE       0x00000080      /* Enable microphone buffer interrupts          */
 143 #define INTE_ADCBUFENABLE       0x00000040      /* Enable ADC buffer interrupts                 */
 144 #define INTE_EFXBUFENABLE       0x00000020      /* Enable Effects buffer interrupts             */
 145 #define INTE_GPSPDIFENABLE      0x00000010      /* Enable GPSPDIF status interrupts             */
 146 #define INTE_CDSPDIFENABLE      0x00000008      /* Enable CDSPDIF status interrupts             */
 147 #define INTE_INTERVALTIMERENB   0x00000004      /* Enable interval timer interrupts             */
 148 #define INTE_MIDITXENABLE       0x00000002      /* Enable MIDI transmit-buffer-empty interrupts */
 149 #define INTE_MIDIRXENABLE       0x00000001      /* Enable MIDI receive-buffer-empty interrupts  */
 150
 151 /* The next two interrupts are for the midi port on the Audigy (A_MPU2) */
 152 #define A_INTE_MIDITXENABLE1    INTE_MIDITXENABLE
 153 #define A_INTE_MIDIRXENABLE1    INTE_MIDIRXENABLE
 154
 155 #define WC                      0x10            /* Wall Clock register                          */
 156 #define WC_SAMPLECOUNTER_MASK   0x03FFFFC0      /* Sample periods elapsed since reset           */
 157 #define WC_SAMPLECOUNTER        0x14060010
 158 #define WC_CURRENTCHANNEL       0x0000003F      /* Channel [0..63] currently being serviced     */
 159                                                 /* NOTE: Each channel takes 1/64th of a sample  */
 160                                                 /* period to be serviced.                       */
 161
 162 #define HCFG                    0x14            /* Hardware config register                     */
 163                                                 /* NOTE: There is no reason to use the legacy   */
 164                                                 /* SoundBlaster emulation stuff described below */
 165                                                 /* under Linux, and all kinds of weird hardware */
 166                                                 /* behavior can result if you try.  Don't.      */
 167 #define HCFG_LEGACYFUNC_MASK    0xe0000000      /* Legacy function number                       */
 168 #define HCFG_LEGACYFUNC_MPU     0x00000000      /* Legacy MPU                                   */
 169 #define HCFG_LEGACYFUNC_SB      0x40000000      /* Legacy SB                                    */
 170 #define HCFG_LEGACYFUNC_AD      0x60000000      /* Legacy AD                                    */
 171 #define HCFG_LEGACYFUNC_MPIC    0x80000000      /* Legacy MPIC                                  */
 172 #define HCFG_LEGACYFUNC_MDMA    0xa0000000      /* Legacy MDMA                                  */
 173 #define HCFG_LEGACYFUNC_SPCI    0xc0000000      /* Legacy SPCI                                  */
 174 #define HCFG_LEGACYFUNC_SDMA    0xe0000000      /* Legacy SDMA                                  */
 175 #define HCFG_IOCAPTUREADDR      0x1f000000      /* The 4 LSBs of the captured I/O address.      */
 176 #define HCFG_LEGACYWRITE        0x00800000      /* 1 = write, 0 = read                          */
 177 #define HCFG_LEGACYWORD         0x00400000      /* 1 = word, 0 = byte                           */
 178 #define HCFG_LEGACYINT          0x00200000      /* 1 = legacy event captured. Write 1 to clear. */
 179                                                 /* NOTE: The rest of the bits in this register  */
 180                                                 /* _are_ relevant under Linux.                  */
 181 #define HCFG_CODECFORMAT_MASK   0x00070000      /* CODEC format                                 */
 182 #define HCFG_CODECFORMAT_AC97   0x00000000      /* AC97 CODEC format -- Primary Output          */
 183 #define HCFG_CODECFORMAT_I2S    0x00010000      /* I2S CODEC format -- Secondary (Rear) Output  */
 184 #define HCFG_GPINPUT0           0x00004000      /* External pin112                              */
 185 #define HCFG_GPINPUT1           0x00002000      /* External pin110                              */
 186
 187 #define HCFG_GPOUTPUT_MASK      0x00001c00      /* External pins which may be controlled        */
 188 #define HCFG_GPOUT0             0x00001000      /* set to enable digital out on 5.1 cards       */
 189
 190 #define HCFG_JOYENABLE          0x00000200      /* Internal joystick enable                     */
 191 #define HCFG_PHASETRACKENABLE   0x00000100      /* Phase tracking enable                        */
 192                                                 /* 1 = Force all 3 async digital inputs to use  */
 193                                                 /* the same async sample rate tracker (ZVIDEO)  */
 194 #define HCFG_AC3ENABLE_MASK     0x0x0000e0      /* AC3 async input control - Not implemented    */
 195 #define HCFG_AC3ENABLE_ZVIDEO   0x00000080      /* Channels 0 and 1 replace ZVIDEO              */
 196 #define HCFG_AC3ENABLE_CDSPDIF  0x00000040      /* Channels 0 and 1 replace CDSPDIF             */
 197 #define HCFG_AC3ENABLE_GPSPDIF  0x00000020      /* Channels 0 and 1 replace GPSPDIF             */
 198 #define HCFG_AUTOMUTE           0x00000010      /* When set, the async sample rate convertors   */
 199                                                 /* will automatically mute their output when    */
 200                                                 /* they are not rate-locked to the external     */
 201                                                 /* async audio source                           */
 202 #define HCFG_LOCKSOUNDCACHE     0x00000008      /* 1 = Cancel bustmaster accesses to soundcache */
 203                                                 /* NOTE: This should generally never be used.   */
 204 #define HCFG_LOCKTANKCACHE_MASK 0x00000004      /* 1 = Cancel bustmaster accesses to tankcache  */
 205                                                 /* NOTE: This should generally never be used.   */
 206 #define HCFG_LOCKTANKCACHE      0x01020014
 207 #define HCFG_MUTEBUTTONENABLE   0x00000002      /* 1 = Master mute button sets AUDIOENABLE = 0. */
 208                                                 /* NOTE: This is a 'cheap' way to implement a   */
 209                                                 /* master mute function on the mute button, and */
 210                                                 /* in general should not be used unless a more  */
 211                                                 /* sophisticated master mute function has not   */
 212                                                 /* been written.                                */
 213 #define HCFG_AUDIOENABLE        0x00000001      /* 0 = CODECs transmit zero-valued samples      */
 214                                                 /* Should be set to 1 when the EMU10K1 is       */
 215                                                 /* completely initialized.                      */
 216
 217 //For Audigy, MPU port move to 0x70-0x74 ptr register
 218
 219 #define MUDATA                  0x18            /* MPU401 data register (8 bits)                */
 220
 221 #define MUCMD                   0x19            /* MPU401 command register (8 bits)             */
 222 #define MUCMD_RESET             0xff            /* RESET command                                */
 223 #define MUCMD_ENTERUARTMODE     0x3f            /* Enter_UART_mode command                      */
 224                                                 /* NOTE: All other commands are ignored         */
 225
 226 #define MUSTAT                  MUCMD           /* MPU401 status register (8 bits)              */
 227 #define MUSTAT_IRDYN            0x80            /* 0 = MIDI data or command ACK                 */
 228 #define MUSTAT_ORDYN            0x40            /* 0 = MUDATA can accept a command or data      */
 229
 230 #define A_IOCFG                 0x18            /* GPIO on Audigy card (16bits)                 */
 231 #define A_GPINPUT_MASK          0xff00
 232 #define A_GPOUTPUT_MASK         0x00ff
 233
 234 #define TIMER                   0x1a            /* Timer terminal count register (16-bit)       */
 235                                                 /* NOTE: After the rate is changed, a maximum   */
 236                                                 /* of 1024 sample periods should be allowed     */
 237                                                 /* before the new rate is guaranteed accurate.  */
 238 #define TIMER_RATE_MASK         0x03ff          /* Timer interrupt rate in sample periods       */
 239                                                 /* 0 == 1024 periods, [1..4] are not useful     */
 240
 241 #define AC97DATA                0x1c            /* AC97 register set data register (16 bit)     */
 242
 243 #define AC97ADDRESS             0x1e            /* AC97 register set address register (8 bit)   */
 244 #define AC97ADDRESS_READY       0x80            /* Read-only bit, reflects CODEC READY signal   */
 245 #define AC97ADDRESS_ADDRESS     0x7f            /* Address of indexed AC97 register             */
 246
 247 /********************************************************************************************************/
 248 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers                     */
 249 /********************************************************************************************************/
 250
 251 #define CPF                     0x00            /* Current pitch and fraction register                  */
 252 #define CPF_CURRENTPITCH_MASK   0xffff0000      /* Current pitch (linear, 0x4000 == unity pitch shift)  */
 253 #define CPF_CURRENTPITCH        0x10100000
 254 #define CPF_STEREO_MASK         0x00008000      /* 1 = Even channel interleave, odd channel locked      */
 255 #define CPF_STOP_MASK           0x00004000      /* 1 = Current pitch forced to 0                        */
 256 #define CPF_FRACADDRESS_MASK    0x00003fff      /* Linear fractional address of the current channel     */
 257
 258 #define PTRX                    0x01            /* Pitch target and send A/B amounts register           */
 259 #define PTRX_PITCHTARGET_MASK   0xffff0000      /* Pitch target of specified channel                    */
 260 #define PTRX_PITCHTARGET        0x10100001
 261 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00     /* Linear level of channel output sent to FX send bus A */
 262 #define PTRX_FXSENDAMOUNT_A     0x08080001
 263 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff     /* Linear level of channel output sent to FX send bus B */
 264 #define PTRX_FXSENDAMOUNT_B     0x08000001
 265
 266 #define CVCF                    0x02            /* Current volume and filter cutoff register            */
 267 #define CVCF_CURRENTVOL_MASK    0xffff0000      /* Current linear volume of specified channel           */
 268 #define CVCF_CURRENTVOL         0x10100002
 269 #define CVCF_CURRENTFILTER_MASK 0x0000ffff      /* Current filter cutoff frequency of specified channel */
 270 #define CVCF_CURRENTFILTER      0x10000002
 271
 272 #define VTFT                    0x03            /* Volume target and filter cutoff target register      */
 273 #define VTFT_VOLUMETARGET_MASK  0xffff0000      /* Volume target of specified channel                   */
 274 #define VTFT_FILTERTARGET_MASK  0x0000ffff      /* Filter cutoff target of specified channel            */
 275
 276 #define Z1                      0x05            /* Filter delay memory 1 register                       */
 277
 278 #define Z2                      0x04            /* Filter delay memory 2 register                       */
 279
 280 #define PSST                    0x06            /* Send C amount and loop start address register        */
 281 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000     /* Linear level of channel output sent to FX send bus C */
 282
 283 #define PSST_FXSENDAMOUNT_C     0x08180006
 284
 285 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff      /* Loop start address of the specified channel          */
 286 #define PSST_LOOPSTARTADDR      0x18000006
 287
 288 #define DSL                     0x07            /* Send D amount and loop start address register        */
 289 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000      /* Linear level of channel output sent to FX send bus D */
 290
 291 #define DSL_FXSENDAMOUNT_D      0x08180007
 292
 293 #define DSL_LOOPENDADDR_MASK    0x00ffffff      /* Loop end address of the specified channel            */
 294 #define DSL_LOOPENDADDR         0x18000007
 295
 296 #define CCCA                    0x08            /* Filter Q, interp. ROM, byte size, cur. addr register */
 297 #define CCCA_RESONANCE          0xf0000000      /* Lowpass filter resonance (Q) height                  */
 298 #define CCCA_INTERPROMMASK      0x0e000000      /* Selects passband of interpolation ROM                */
 299                                                 /* 1 == full band, 7 == lowpass                         */
 300                                                 /* ROM 0 is used when pitch shifting downward or less   */
 301                                                 /* then 3 semitones upward.  Increasingly higher ROM    */
 302                                                 /* numbers are used, typically in steps of 3 semitones, */
 303                                                 /* as upward pitch shifting is performed.               */
 304 #define CCCA_INTERPROM_0        0x00000000      /* Select interpolation ROM 0                           */
 305 #define CCCA_INTERPROM_1        0x02000000      /* Select interpolation ROM 1                           */
 306 #define CCCA_INTERPROM_2        0x04000000      /* Select interpolation ROM 2                           */
 307 #define CCCA_INTERPROM_3        0x06000000      /* Select interpolation ROM 3                           */
 308 #define CCCA_INTERPROM_4        0x08000000      /* Select interpolation ROM 4                           */
 309 #define CCCA_INTERPROM_5        0x0a000000      /* Select interpolation ROM 5                           */
 310 #define CCCA_INTERPROM_6        0x0c000000      /* Select interpolation ROM 6                           */
 311 #define CCCA_INTERPROM_7        0x0e000000      /* Select interpolation ROM 7                           */
 312 #define CCCA_8BITSELECT         0x01000000      /* 1 = Sound memory for this channel uses 8-bit samples */
 313 #define CCCA_CURRADDR_MASK      0x00ffffff      /* Current address of the selected channel              */
 314 #define CCCA_CURRADDR           0x18000008
 315
 316 #define CCR                     0x09            /* Cache control register                               */
 317 #define CCR_CACHEINVALIDSIZE    0x07190009
 318 #define CCR_CACHEINVALIDSIZE_MASK       0xfe000000      /* Number of invalid samples cache for this channel     */
 319 #define CCR_CACHELOOPFLAG       0x01000000      /* 1 = Cache has a loop service pending                 */
 320 #define CCR_INTERLEAVEDSAMPLES  0x00800000      /* 1 = A cache service will fetch interleaved samples   */
 321 #define CCR_WORDSIZEDSAMPLES    0x00400000      /* 1 = A cache service will fetch word sized samples    */
 322 #define CCR_READADDRESS         0x06100009
 323 #define CCR_READADDRESS_MASK    0x003f0000      /* Location of cache just beyond current cache service  */
 324 #define CCR_LOOPINVALSIZE       0x0000fe00      /* Number of invalid samples in cache prior to loop     */
 325                                                 /* NOTE: This is valid only if CACHELOOPFLAG is set     */
 326 #define CCR_LOOPFLAG            0x00000100      /* Set for a single sample period when a loop occurs    */
 327 #define CCR_CACHELOOPADDRHI     0x000000ff      /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set  */
 328
 329 #define CLP                     0x0a            /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
 330                                                 /* NOTE: This register is normally not used             */
 331 #define CLP_CACHELOOPADDR       0x0000ffff      /* Cache loop address (DSL_LOOPSTARTADDR [0..15])       */
 332
 333 #define FXRT                    0x0b            /* Effects send routing register                        */
 334                                                 /* NOTE: It is illegal to assign the same routing to    */
 335                                                 /* two effects sends.                                   */
 336 #define FXRT_CHANNELA           0x000f0000      /* Effects send bus number for channel's effects send A */
 337 #define FXRT_CHANNELB           0x00f00000      /* Effects send bus number for channel's effects send B */
 338 #define FXRT_CHANNELC           0x0f000000      /* Effects send bus number for channel's effects send C */
 339 #define FXRT_CHANNELD           0xf0000000      /* Effects send bus number for channel's effects send D */
 340
 341 #define MAPA                    0x0c            /* Cache map A                                          */
 342
 343 #define MAPB                    0x0d            /* Cache map B                                          */
 344
 345 #define MAP_PTE_MASK            0xffffe000      /* The 19 MSBs of the PTE indexed by the PTI            */
 346 #define MAP_PTI_MASK            0x00001fff      /* The 13 bit index to one of the 8192 PTE dwords       */
 347
 348 #define ENVVOL                  0x10            /* Volume envelope register                             */
 349 #define ENVVOL_MASK             0x0000ffff      /* Current value of volume envelope state variable      */
 350                                                 /* 0x8000-n == 666*n usec delay                         */
 351
 352 #define ATKHLDV                 0x11            /* Volume envelope hold and attack register             */
 353 #define ATKHLDV_PHASE0          0x00008000      /* 0 = Begin attack phase                               */
 354 #define ATKHLDV_HOLDTIME_MASK   0x00007f00      /* Envelope hold time (127-n == n*88.2msec)             */
 355 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f      /* Envelope attack time, log encoded                    */
 356                                                 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec       */
 357
 358 #define DCYSUSV                 0x12            /* Volume envelope sustain and decay register           */
 359 #define DCYSUSV_PHASE1_MASK     0x00008000      /* 0 = Begin attack phase, 1 = begin release phase      */
 360 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00    /* 127 = full, 0 = off, 0.75dB increments               */
 361 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080   /* 1 = Inhibit envelope engine from writing values in   */
 362                                                 /* this channel and from writing to pitch, filter and   */
 363                                                 /* volume targets.                                      */
 364 #define DCYSUSV_DECAYTIME_MASK  0x0000007f      /* Volume envelope decay time, log encoded              */
 365                                                 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec            */
 366
 367 #define LFOVAL1                 0x13            /* Modulation LFO value                                 */
 368 #define LFOVAL_MASK             0x0000ffff      /* Current value of modulation LFO state variable       */
 369                                                 /* 0x8000-n == 666*n usec delay                         */
 370
 371 #define ENVVAL                  0x14            /* Modulation envelope register                         */
 372 #define ENVVAL_MASK             0x0000ffff      /* Current value of modulation envelope state variable  */
 373                                                 /* 0x8000-n == 666*n usec delay                         */
 374
 375 #define ATKHLDM                 0x15            /* Modulation envelope hold and attack register         */
 376 #define ATKHLDM_PHASE0          0x00008000      /* 0 = Begin attack phase                               */
 377 #define ATKHLDM_HOLDTIME        0x00007f00      /* Envelope hold time (127-n == n*42msec)               */
 378 #define ATKHLDM_ATTACKTIME      0x0000007f      /* Envelope attack time, log encoded                    */
 379                                                 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec         */
 380
 381 #define DCYSUSM                 0x16            /* Modulation envelope decay and sustain register       */
 382 #define DCYSUSM_PHASE1_MASK     0x00008000      /* 0 = Begin attack phase, 1 = begin release phase      */
 383 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00    /* 127 = full, 0 = off, 0.75dB increments               */
 384 #define DCYSUSM_DECAYTIME_MASK  0x0000007f      /* Envelope decay time, log encoded                     */
 385                                                 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec            */
 386
 387 #define LFOVAL2                 0x17            /* Vibrato LFO register                                 */
 388 #define LFOVAL2_MASK            0x0000ffff      /* Current value of vibrato LFO state variable          */
 389                                                 /* 0x8000-n == 666*n usec delay                         */
 390
 391 #define IP                      0x18            /* Initial pitch register                               */
 392 #define IP_MASK                 0x0000ffff      /* Exponential initial pitch shift                      */
 393                                                 /* 4 bits of octave, 12 bits of fractional octave       */
 394 #define IP_UNITY                0x0000e000      /* Unity pitch shift                                    */
 395
 396 #define IFATN                   0x19            /* Initial filter cutoff and attenuation register       */
 397 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00      /* Initial filter cutoff frequency in exponential units */
 398                                                 /* 6 most significant bits are semitones                */
 399                                                 /* 2 least significant bits are fractions               */
 400 #define IFATN_FILTERCUTOFF      0x08080019
 401 #define IFATN_ATTENUATION_MASK  0x000000ff      /* Initial attenuation in 0.375dB steps                 */
 402 #define IFATN_ATTENUATION       0x08000019
 403
 404
 405 #define PEFE                    0x1a            /* Pitch envelope and filter envelope amount register   */
 406 #define PEFE_PITCHAMOUNT_MASK   0x0000ff00      /* Pitch envlope amount                                 */
 407                                                 /* Signed 2's complement, +/- one octave peak extremes  */
 408 #define PEFE_PITCHAMOUNT        0x0808001a
 409 #define PEFE_FILTERAMOUNT_MASK  0x000000ff      /* Filter envlope amount                                */
 410                                                 /* Signed 2's complement, +/- six octaves peak extremes */
 411 #define PEFE_FILTERAMOUNT       0x0800001a
 412 #define FMMOD                   0x1b            /* Vibrato/filter modulation from LFO register          */
 413 #define FMMOD_MODVIBRATO        0x0000ff00      /* Vibrato LFO modulation depth                         */
 414                                                 /* Signed 2's complement, +/- one octave extremes       */
 415 #define FMMOD_MOFILTER          0x000000ff      /* Filter LFO modulation depth                          */
 416                                                 /* Signed 2's complement, +/- three octave extremes     */
 417
 418
 419 #define TREMFRQ                 0x1c            /* Tremolo amount and modulation LFO frequency register */
 420 #define TREMFRQ_DEPTH           0x0000ff00      /* Tremolo depth                                        */
 421                                                 /* Signed 2's complement, with +/- 12dB extremes        */
 422 #define TREMFRQ_FREQUENCY       0x000000ff      /* Tremolo LFO frequency                                */
 423                                                 /* ??Hz steps, maximum of ?? Hz.                        */
 424
 425 #define FM2FRQ2                 0x1d            /* Vibrato amount and vibrato LFO frequency register    */
 426 #define FM2FRQ2_DEPTH           0x0000ff00      /* Vibrato LFO vibrato depth                            */
 427                                                 /* Signed 2's complement, +/- one octave extremes       */
 428 #define FM2FRQ2_FREQUENCY       0x000000ff      /* Vibrato LFO frequency                                */
 429                                                 /* 0.039Hz steps, maximum of 9.85 Hz.                   */
 430
 431 #define TEMPENV                 0x1e            /* Tempory envelope register                            */
 432 #define TEMPENV_MASK            0x0000ffff      /* 16-bit value                                         */
 433                                                 /* NOTE: All channels contain internal variables; do    */
 434                                                 /* not write to these locations.                        */
 435
 436 #define CD0                     0x20            /* Cache data 0 register                                */
 437 #define CD1                     0x21            /* Cache data 1 register                                */
 438 #define CD2                     0x22            /* Cache data 2 register                                */
 439 #define CD3                     0x23            /* Cache data 3 register                                */
 440 #define CD4                     0x24            /* Cache data 4 register                                */
 441 #define CD5                     0x25            /* Cache data 5 register                                */
 442 #define CD6                     0x26            /* Cache data 6 register                                */
 443 #define CD7                     0x27            /* Cache data 7 register                                */
 444 #define CD8                     0x28            /* Cache data 8 register                                */
 445 #define CD9                     0x29            /* Cache data 9 register                                */
 446 #define CDA                     0x2a            /* Cache data A register                                */
 447 #define CDB                     0x2b            /* Cache data B register                                */
 448 #define CDC                     0x2c            /* Cache data C register                                */
 449 #define CDD                     0x2d            /* Cache data D register                                */
 450 #define CDE                     0x2e            /* Cache data E register                                */
 451 #define CDF                     0x2f            /* Cache data F register                                */
 452
 453 #define PTB                     0x40            /* Page table base register                             */
 454 #define PTB_MASK                0xfffff000      /* Physical address of the page table in host memory    */
 455
 456 #define TCB                     0x41            /* Tank cache base register                             */
 457 #define TCB_MASK                0xfffff000      /* Physical address of the bottom of host based TRAM    */
 458
 459 #define ADCCR                   0x42            /* ADC sample rate/stereo control register              */
 460 #define ADCCR_RCHANENABLE       0x00000010      /* Enables right channel for writing to the host        */
 461 #define ADCCR_LCHANENABLE       0x00000008      /* Enables left channel for writing to the host         */
 462                                                 /* NOTE: To guarantee phase coherency, both channels    */
 463                                                 /* must be disabled prior to enabling both channels.    */
 464 #define A_ADCCR_RCHANENABLE     0x00000020
 465 #define A_ADCCR_LCHANENABLE     0x00000010
 466
 467 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F      /* Audigy sample rate convertor output rate             */
 468 #define ADCCR_SAMPLERATE_MASK   0x00000007      /* Sample rate convertor output rate                    */
 469
 470 #define ADCCR_SAMPLERATE_48     0x00000000      /* 48kHz sample rate                                    */
 471 #define ADCCR_SAMPLERATE_44     0x00000001      /* 44.1kHz sample rate                                  */
 472 #define ADCCR_SAMPLERATE_32     0x00000002      /* 32kHz sample rate                                    */
 473 #define ADCCR_SAMPLERATE_24     0x00000003      /* 24kHz sample rate                                    */
 474 #define ADCCR_SAMPLERATE_22     0x00000004      /* 22.05kHz sample rate                                 */
 475 #define ADCCR_SAMPLERATE_16     0x00000005      /* 16kHz sample rate                                    */
 476 #define ADCCR_SAMPLERATE_11     0x00000006      /* 11.025kHz sample rate                                */
 477 #define ADCCR_SAMPLERATE_8      0x00000007      /* 8kHz sample rate                                     */
 478
 479 #define A_ADCCR_SAMPLERATE_12   0x00000006      /* 12kHz sample rate                                    */
 480 #define A_ADCCR_SAMPLERATE_11   0x00000007      /* 11.025kHz sample rate                                */
 481 #define A_ADCCR_SAMPLERATE_8    0x00000008      /* 8kHz sample rate                                     */
 482
 483 #define FXWC                    0x43            /* FX output write channels register                    */
 484                                                 /* When set, each bit enables the writing of the        */
 485                                                 /* corresponding FX output channel (internal registers  */
 486                                                 /* 0x20-0x3f) into host memory. This mode of recording  */
 487                                                 /* is 16bit, 48KHz only. All 32 channels can be enabled */
 488                                                 /* simultaneously.                                      */
 489 #define TCBS                    0x44            /* Tank cache buffer size register                      */
 490 #define TCBS_MASK               0x00000007      /* Tank cache buffer size field                         */
 491 #define TCBS_BUFFSIZE_16K       0x00000000
 492 #define TCBS_BUFFSIZE_32K       0x00000001
 493 #define TCBS_BUFFSIZE_64K       0x00000002
 494 #define TCBS_BUFFSIZE_128K      0x00000003
 495 #define TCBS_BUFFSIZE_256K      0x00000004
 496 #define TCBS_BUFFSIZE_512K      0x00000005
 497 #define TCBS_BUFFSIZE_1024K     0x00000006
 498 #define TCBS_BUFFSIZE_2048K     0x00000007
 499
 500 #define MICBA                   0x45            /* AC97 microphone buffer address register              */
 501 #define MICBA_MASK              0xfffff000      /* 20 bit base address                                  */
 502
 503 #define ADCBA                   0x46            /* ADC buffer address register                          */
 504 #define ADCBA_MASK              0xfffff000      /* 20 bit base address                                  */
 505
 506 #define FXBA                    0x47            /* FX Buffer Address */
 507 #define FXBA_MASK               0xfffff000      /* 20 bit base address                                  */
 508
 509 #define MICBS                   0x49            /* Microphone buffer size register                      */
 510
 511 #define ADCBS                   0x4a            /* ADC buffer size register                             */
 512
 513 #define FXBS                    0x4b            /* FX buffer size register                              */
 514
 515 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
 516 #define ADCBS_BUFSIZE_NONE      0x00000000
 517 #define ADCBS_BUFSIZE_384       0x00000001
 518 #define ADCBS_BUFSIZE_448       0x00000002
 519 #define ADCBS_BUFSIZE_512       0x00000003
 520 #define ADCBS_BUFSIZE_640       0x00000004
 521 #define ADCBS_BUFSIZE_768       0x00000005
 522 #define ADCBS_BUFSIZE_896       0x00000006
 523 #define ADCBS_BUFSIZE_1024      0x00000007
 524 #define ADCBS_BUFSIZE_1280      0x00000008
 525 #define ADCBS_BUFSIZE_1536      0x00000009
 526 #define ADCBS_BUFSIZE_1792      0x0000000a
 527 #define ADCBS_BUFSIZE_2048      0x0000000b
 528 #define ADCBS_BUFSIZE_2560      0x0000000c
 529 #define ADCBS_BUFSIZE_3072      0x0000000d
 530 #define ADCBS_BUFSIZE_3584      0x0000000e
 531 #define ADCBS_BUFSIZE_4096      0x0000000f
 532 #define ADCBS_BUFSIZE_5120      0x00000010
 533 #define ADCBS_BUFSIZE_6144      0x00000011
 534 #define ADCBS_BUFSIZE_7168      0x00000012
 535 #define ADCBS_BUFSIZE_8192      0x00000013
 536 #define ADCBS_BUFSIZE_10240     0x00000014
 537 #define ADCBS_BUFSIZE_12288     0x00000015
 538 #define ADCBS_BUFSIZE_14366     0x00000016
 539 #define ADCBS_BUFSIZE_16384     0x00000017
 540 #define ADCBS_BUFSIZE_20480     0x00000018
 541 #define ADCBS_BUFSIZE_24576     0x00000019
 542 #define ADCBS_BUFSIZE_28672     0x0000001a
 543 #define ADCBS_BUFSIZE_32768     0x0000001b
 544 #define ADCBS_BUFSIZE_40960     0x0000001c
 545 #define ADCBS_BUFSIZE_49152     0x0000001d
 546 #define ADCBS_BUFSIZE_57344     0x0000001e
 547 #define ADCBS_BUFSIZE_65536     0x0000001f
 548
 549
 550 #define CDCS                    0x50            /* CD-ROM digital channel status register       */
 551
 552 #define GPSCS                   0x51            /* General Purpose SPDIF channel status register*/
 553
 554 #define DBG                     0x52            /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
 555
 556 /* definitions for debug register - taken from the alsa drivers */
 557 #define DBG_ZC                  0x80000000      /* zero tram counter */
 558 #define DBG_SATURATION_OCCURED  0x02000000      /* saturation control */
 559 #define DBG_SATURATION_ADDR     0x01ff0000      /* saturation address */
 560 #define DBG_SINGLE_STEP         0x00008000      /* single step mode */
 561 #define DBG_STEP                0x00004000      /* start single step */
 562 #define DBG_CONDITION_CODE      0x00003e00      /* condition code */
 563 #define DBG_SINGLE_STEP_ADDR    0x000001ff      /* single step address */
 564
 565
 566 #define REG53                   0x53            /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
 567
 568 #define A_DBG                    0x53
 569 #define A_DBG_SINGLE_STEP        0x00020000     /* Set to zero to start dsp */
 570 #define A_DBG_ZC                 0x40000000     /* zero tram counter */
 571 #define A_DBG_STEP_ADDR          0x000003ff
 572 #define A_DBG_SATURATION_OCCURED 0x20000000
 573 #define A_DBG_SATURATION_ADDR    0x0ffc0000
 574
 575 #define SPCS0                   0x54            /* SPDIF output Channel Status 0 register       */
 576
 577 #define SPCS1                   0x55            /* SPDIF output Channel Status 1 register       */
 578
 579 #define SPCS2                   0x56            /* SPDIF output Channel Status 2 register       */
 580
 581 #define SPCS_CLKACCYMASK        0x30000000      /* Clock accuracy                               */
 582 #define SPCS_CLKACCY_1000PPM    0x00000000      /* 1000 parts per million                       */
 583 #define SPCS_CLKACCY_50PPM      0x10000000      /* 50 parts per million                         */
 584 #define SPCS_CLKACCY_VARIABLE   0x20000000      /* Variable accuracy                            */
 585 #define SPCS_SAMPLERATEMASK     0x0f000000      /* Sample rate                                  */
 586 #define SPCS_SAMPLERATE_44      0x00000000      /* 44.1kHz sample rate                          */
 587 #define SPCS_SAMPLERATE_48      0x02000000      /* 48kHz sample rate                            */
 588 #define SPCS_SAMPLERATE_32      0x03000000      /* 32kHz sample rate                            */
 589 #define SPCS_CHANNELNUMMASK     0x00f00000      /* Channel number                               */
 590 #define SPCS_CHANNELNUM_UNSPEC  0x00000000      /* Unspecified channel number                   */
 591 #define SPCS_CHANNELNUM_LEFT    0x00100000      /* Left channel                                 */
 592 #define SPCS_CHANNELNUM_RIGHT   0x00200000      /* Right channel                                */
 593 #define SPCS_SOURCENUMMASK      0x000f0000      /* Source number                                */
 594 #define SPCS_SOURCENUM_UNSPEC   0x00000000      /* Unspecified source number                    */
 595 #define SPCS_GENERATIONSTATUS   0x00008000      /* Originality flag (see IEC-958 spec)          */
 596 #define SPCS_CATEGORYCODEMASK   0x00007f00      /* Category code (see IEC-958 spec)             */
 597 #define SPCS_MODEMASK           0x000000c0      /* Mode (see IEC-958 spec)                      */
 598 #define SPCS_EMPHASISMASK       0x00000038      /* Emphasis                                     */
 599 #define SPCS_EMPHASIS_NONE      0x00000000      /* No emphasis                                  */
 600 #define SPCS_EMPHASIS_50_15     0x00000008      /* 50/15 usec 2 channel                         */
 601 #define SPCS_COPYRIGHT          0x00000004      /* Copyright asserted flag -- do not modify     */
 602 #define SPCS_NOTAUDIODATA       0x00000002      /* 0 = Digital audio, 1 = not audio             */
 603 #define SPCS_PROFESSIONAL       0x00000001      /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992)  */
 604
 605 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status               */
 606 #define CLIEL                   0x58            /* Channel loop interrupt enable low register   */
 607
 608 #define CLIEH                   0x59            /* Channel loop interrupt enable high register  */
 609
 610 #define CLIPL                   0x5a            /* Channel loop interrupt pending low register  */
 611
 612 #define CLIPH                   0x5b            /* Channel loop interrupt pending high register */
 613
 614 #define SOLEL                   0x5c            /* Stop on loop enable low register             */
 615
 616 #define SOLEH                   0x5d            /* Stop on loop enable high register            */
 617
 618 #define SPBYPASS                0x5e            /* SPDIF BYPASS mode register                   */
 619 #define SPBYPASS_ENABLE         0x00000001      /* Enable SPDIF bypass mode                     */
 620
 621 #define AC97SLOT                0x5f            /* additional AC97 slots enable bits */
 622 #define AC97SLOT_CNTR           0x10            /* Center enable */
 623 #define AC97SLOT_LFE            0x20            /* LFE enable */
 624
 625 #define CDSRCS                  0x60            /* CD-ROM Sample Rate Converter status register */
 626
 627 #define GPSRCS                  0x61            /* General Purpose SPDIF sample rate cvt status */
 628
 629 #define ZVSRCS                  0x62            /* ZVideo sample rate converter status          */
 630                                                 /* NOTE: This one has no SPDIFLOCKED field      */
 631                                                 /* Assumes sample lock                          */
 632
 633 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS.                 */
 634 #define SRCS_SPDIFLOCKED        0x02000000      /* SPDIF stream locked                          */
 635 #define SRCS_RATELOCKED         0x01000000      /* Sample rate locked                           */
 636 #define SRCS_ESTSAMPLERATE      0x0007ffff      /* Do not modify this field.                    */
 637
 638
 639 /* Note that these values can vary +/- by a small amount                                        */
 640 #define SRCS_SPDIFRATE_44       0x0003acd9
 641 #define SRCS_SPDIFRATE_48       0x00040000
 642 #define SRCS_SPDIFRATE_96       0x00080000
 643
 644 #define MICIDX                  0x63            /* Microphone recording buffer index register   */
 645 #define MICIDX_MASK             0x0000ffff      /* 16-bit value                                 */
 646 #define MICIDX_IDX              0x10000063
 647
 648 #define A_ADCIDX                0x63
 649 #define A_ADCIDX_IDX            0x10000063
 650
 651 #define ADCIDX                  0x64            /* ADC recording buffer index register          */
 652 #define ADCIDX_MASK             0x0000ffff      /* 16 bit index field                           */
 653 #define ADCIDX_IDX              0x10000064
 654
 655 #define FXIDX                   0x65            /* FX recording buffer index register           */
 656 #define FXIDX_MASK              0x0000ffff      /* 16-bit value                                 */
 657 #define FXIDX_IDX               0x10000065
 658
 659 /* This is the MPU port on the card (via the game port)                                         */
 660 #define A_MUDATA1               0x70
 661 #define A_MUCMD1                0x71
 662 #define A_MUSTAT1               A_MUCMD1
 663
 664 /* This is the MPU port on the Audigy Drive                                                     */
 665 #define A_MUDATA2               0x72
 666 #define A_MUCMD2                0x73
 667 #define A_MUSTAT2               A_MUCMD2
 668
 669 /* The next two are the Audigy equivalent of FXWC                                               */
 670 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously)             */
 671 /* Each bit selects a channel for recording */
 672 #define A_FXWC1                 0x74            /* Selects 0x7f-0x60 for FX recording           */
 673 #define A_FXWC2                 0x75            /* Selects 0x9f-0x80 for FX recording           */
 674
 675 #define A_SPDIF_SAMPLERATE      0x76            /* Set the sample rate of SPDIF output          */
 676 #define A_SPDIF_48000           0x00000080
 677 #define A_SPDIF_44100           0x00000000
 678 #define A_SPDIF_96000           0x00000040
 679
 680 #define A_FXRT2                 0x7c
 681 #define A_FXRT_CHANNELE         0x0000003f      /* Effects send bus number for channel's effects send E */
 682 #define A_FXRT_CHANNELF         0x00003f00      /* Effects send bus number for channel's effects send F */
 683 #define A_FXRT_CHANNELG         0x003f0000      /* Effects send bus number for channel's effects send G */
 684 #define A_FXRT_CHANNELH         0x3f000000      /* Effects send bus number for channel's effects send H */
 685
 686 #define A_SENDAMOUNTS           0x7d
 687 #define A_FXSENDAMOUNT_E_MASK   0xff000000
 688 #define A_FXSENDAMOUNT_F_MASK   0x00ff0000
 689 #define A_FXSENDAMOUNT_G_MASK   0x0000ff00
 690 #define A_FXSENDAMOUNT_H_MASK   0x000000ff
 691
 692 /* The send amounts for this one are the same as used with the emu10k1 */
 693 #define A_FXRT1                 0x7e
 694 #define A_FXRT_CHANNELA         0x0000003f
 695 #define A_FXRT_CHANNELB         0x00003f00
 696 #define A_FXRT_CHANNELC         0x003f0000
 697 #define A_FXRT_CHANNELD         0x3f000000
 698
 699
 700 /* Each FX general purpose register is 32 bits in length, all bits are used                     */
 701 #define FXGPREGBASE             0x100           /* FX general purpose registers base            */
 702 #define A_FXGPREGBASE           0x400           /* Audigy GPRs, 0x400 to 0x5ff                  */
 703 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is  */
 704 /* decompressed back to 20 bits on a read.  There are a total of 160 locations, the last 32     */
 705 /* locations are for external TRAM.                                                             */
 706 #define TANKMEMDATAREGBASE      0x200           /* Tank memory data registers base              */
 707 #define TANKMEMDATAREG_MASK     0x000fffff      /* 20 bit tank audio data field                 */
 708
 709 /* Combined address field and memory opcode or flag field.  160 locations, last 32 are external */
 710 #define TANKMEMADDRREGBASE      0x300           /* Tank memory address registers base           */
 711 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff     /* 20 bit tank address field                    */
 712 #define TANKMEMADDRREG_CLEAR    0x00800000      /* Clear tank memory                            */
 713 #define TANKMEMADDRREG_ALIGN    0x00400000      /* Align read or write relative to tank access  */
 714 #define TANKMEMADDRREG_WRITE    0x00200000      /* Write to tank memory                         */
 715 #define TANKMEMADDRREG_READ     0x00100000      /* Read from tank memory                        */
 716
 717 #define MICROCODEBASE           0x400           /* Microcode data base address                  */
 718
 719 /* Each DSP microcode instruction is mapped into 2 doublewords                                  */
 720 /* NOTE: When writing, always write the LO doubleword first.  Reads can be in either order.     */
 721 #define LOWORD_OPX_MASK         0x000ffc00      /* Instruction operand X                        */
 722 #define LOWORD_OPY_MASK         0x000003ff      /* Instruction operand Y                        */
 723 #define HIWORD_OPCODE_MASK      0x00f00000      /* Instruction opcode                           */
 724 #define HIWORD_RESULT_MASK      0x000ffc00      /* Instruction result                           */
 725 #define HIWORD_OPA_MASK         0x000003ff      /* Instruction operand A                        */
 726
 727
 728 /* Audigy Soundcard have a different instruction format */
 729 #define AUDIGY_CODEBASE         0x600
 730 #define A_LOWORD_OPY_MASK       0x000007ff
 731 #define A_LOWORD_OPX_MASK       0x007ff000
 732 #define A_HIWORD_OPCODE_MASK    0x0f000000
 733 #define A_HIWORD_RESULT_MASK    0x007ff000
 734 #define A_HIWORD_OPA_MASK       0x000007ff
 735
 736
 737 #endif /* _8010_H */