workbench/devs/AHI/Drivers/EMU10kx/efxmgr.h

   1 /*
   2  **********************************************************************
   3  *     sblive_fx.h
   4  *     Copyright 1999, 2000 Creative Labs, Inc.
   5  *
   6  **********************************************************************
   7  *
   8  *     Date                 Author          Summary of changes
   9  *     ----                 ------          ------------------
  10  *     October 20, 1999     Bertrand Lee    base code release
  11  *
  12  **********************************************************************
  13  *
  14  *     This program is free software; you can redistribute it and/or
  15  *     modify it under the terms of the GNU General Public License as
  16  *     published by the Free Software Foundation; either version 2 of
  17  *     the License, or (at your option) any later version.
  18  *
  19  *     This program is distributed in the hope that it will be useful,
  20  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  *     GNU General Public License for more details.
  23  *
  24  *     You should have received a copy of the GNU General Public
  25  *     License along with this program; if not, write to the Free
  26  *     Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
  27  *     USA.
  28  *
  29  **********************************************************************
  30  */
  31
  32 #ifndef _EFXMGR_H
  33 #define _EFXMGR_H
  34
  35 struct emu_efx_info_t{
  36         int opcode_shift;
  37         int high_operand_shift;
  38         int instruction_start;
  39         int gpr_base;
  40         int output_base;
  41 };
  42
  43
  44 #define WRITE_EFX(a, b, c) sblive_writeptr((a), emu_efx_info[card->is_audigy].instruction_start + (b), 0, (c))
  45
  46 #define OP(op, z, w, x, y) \
  47         do { WRITE_EFX(card, (pc) * 2, ((x) << emu_efx_info[card->is_audigy].high_operand_shift) | (y)); \
  48         WRITE_EFX(card, (pc) * 2 + 1, ((op) << emu_efx_info[card->is_audigy].opcode_shift ) | ((z) << emu_efx_info[card->is_audigy].high_operand_shift) | (w)); \
  49         ++pc; } while (0)
  50
  51 #define NUM_INPUTS 0x20
  52 #define NUM_OUTPUTS 0x20
  53 #define NUM_GPRS 0x100
  54
  55 #define A_NUM_INPUTS 0x60
  56 #define A_NUM_OUTPUTS 0x60  //fixme: this may or may not be true
  57 #define A_NUM_GPRS 0x200
  58
  59 #define GPR_NAME_SIZE   32
  60 #define PATCH_NAME_SIZE 32
  61
  62 struct dsp_rpatch {
  63         char name[PATCH_NAME_SIZE];
  64         u16 code_start;
  65         u16 code_size;
  66
  67         unsigned long gpr_used[NUM_GPRS / (sizeof(unsigned long) * 8) + 1];
  68         unsigned long gpr_input[NUM_GPRS / (sizeof(unsigned long) * 8) + 1];
  69         unsigned long route[NUM_OUTPUTS];
  70         unsigned long route_v[NUM_OUTPUTS];
  71 };
  72
  73 struct dsp_patch {
  74         char name[PATCH_NAME_SIZE];
  75         u8 id;
  76         unsigned long input;                      /* bitmap of the lines used as inputs */
  77         unsigned long output;                     /* bitmap of the lines used as outputs */
  78         u16 code_start;
  79         u16 code_size;
  80
  81         unsigned long gpr_used[NUM_GPRS / (sizeof(unsigned long) * 8) + 1];    /* bitmap of used gprs */
  82         unsigned long gpr_input[NUM_GPRS / (sizeof(unsigned long) * 8) + 1];
  83         u8 traml_istart;  /* starting address of the internal tram lines used */
  84         u8 traml_isize;   /* number of internal tram lines used */
  85
  86         u8 traml_estart;
  87         u8 traml_esize;
  88
  89         u16 tramb_istart;        /* starting address of the internal tram memory used */
  90         u16 tramb_isize;         /* amount of internal memory used */
  91         u32 tramb_estart;
  92         u32 tramb_esize;
  93 };
  94
  95 struct dsp_gpr {
  96         u8 type;                      /* gpr type, STATIC, DYNAMIC, INPUT, OUTPUT, CONTROL */
  97         char name[GPR_NAME_SIZE];       /* gpr value, only valid for control gprs */
  98         s32 min, max;         /* value range for this gpr, only valid for control gprs */
  99         u8 line;                    /* which input/output line is the gpr attached, only valid for input/output gprs */
 100         u8 usage;
 101 };
 102
 103 enum {
 104         GPR_TYPE_NULL = 0,
 105         GPR_TYPE_IO,
 106         GPR_TYPE_STATIC,
 107         GPR_TYPE_DYNAMIC,
 108         GPR_TYPE_CONTROL,
 109         GPR_TYPE_CONSTANT
 110 };
 111
 112 #define GPR_BASE 0x100
 113 #define OUTPUT_BASE 0x20
 114
 115 #define A_GPR_BASE 0x400
 116 #define A_OUTPUT_BASE 0x60
 117
 118 #define MAX_PATCHES_PAGES 32
 119
 120 struct patch_manager {
 121         void *patch[MAX_PATCHES_PAGES];
 122         int current_pages;
 123         struct dsp_rpatch rpatch;
 124         struct dsp_gpr gpr[NUM_GPRS];   /* gpr usage table */
 125 //      spinlock_t lock;
 126         s16 ctrl_gpr[SOUND_MIXER_NRDEVICES][2];
 127 };
 128
 129 #define PATCHES_PER_PAGE (PAGE_SIZE / sizeof(struct dsp_patch))
 130
 131 #define PATCH(mgr, i) ((struct dsp_patch *) (mgr)->patch[(i) / PATCHES_PER_PAGE] + (i) % PATCHES_PER_PAGE)
 132
 133 #ifdef AHI
 134
 135 /* AHI streams */
 136 #define AHI_FRONT_L             0x00
 137 #define AHI_FRONT_R             0x01
 138 #define AHI_REAR_L              0x04
 139 #define AHI_REAR_R              0x05
 140 #define AHI_SURROUND_L          0x06
 141 #define AHI_SURROUND_R          0x07
 142 #define AHI_CENTER              0x08
 143 #define AHI_LFE                 0x09
 144
 145 /* Hardware outputs */
 146 #define L_ANALOG_FRONT_L        0x20
 147 #define L_ANALOG_FRONT_R        0x21
 148 #define L_ANALOG_REAR_L         0x28
 149 #define L_ANALOG_REAR_R         0x29
 150 #define L_ANALOG_CENTER         0x31
 151 #define L_ANALOG_LFE            0x32
 152
 153 #define L_SPDIF_FRONT_L         0x22
 154 #define L_SPDIF_FRONT_R         0x23
 155 //#define L_SPDIF_REAR_L        (Shared with Analog Rear)
 156 //#define L_SPDIF_REAR_R        (Shared with Analog Rear)
 157 #define L_SPDIF_SURROUND_L      0x26
 158 #define L_SPDIF_SURROUND_R      0x27
 159 #define L_SPDIF_CENTER          0x24
 160 #define L_SPDIF_LFE             0x25
 161
 162 #define L_ADC_REC_L             0x2a
 163 #define L_ADC_REC_R             0x2b
 164
 165
 166 #define A_ANALOG_FRONT_L        0x68
 167 #define A_ANALOG_FRONT_R        0x69
 168 #define A_ANALOG_REAR_L         0x6e
 169 #define A_ANALOG_REAR_R         0x6f
 170 #define A_ANALOG_SURROUND_L     0x6c    // Correct??
 171 #define A_ANALOG_SURROUND_R     0x6d    // Correct??
 172 #define A_ANALOG_CENTER         0x6a
 173 #define A_ANALOG_LFE            0x6b
 174
 175 #define A_SPDIF_FRONT_L         0x60
 176 #define A_SPDIF_FRONT_R         0x61
 177 #define A_SPDIF_REAR_L          0x66
 178 #define A_SPDIF_REAR_R          0x67
 179 #define A_SPDIF_SURROUND_L      0x64
 180 #define A_SPDIF_SURROUND_R      0x65
 181 #define A_SPDIF_CENTER          0x62
 182 #define A_SPDIF_LFE             0x63
 183
 184 #define A_ADC_REC_L             0x76
 185 #define A_ADC_REC_R             0x77
 186
 187
 188 /* Hardware inputs */
 189 #define L_AC97_IN_L             0x10
 190 #define L_AC97_IN_R             0x11
 191 #define L_SPDIF_CD_L            0x12
 192 #define L_SPDIF_CD_R            0x13
 193 #define L_SPDIF_IN_L            0x16
 194 #define L_SPDIF_IN_R            0x17
 195
 196 #define A_AC97_IN_L             0x40
 197 #define A_AC97_IN_R             0x41
 198 #define A_SPDIF_CD_L            0x42
 199 #define A_SPDIF_CD_R            0x43
 200 #define A_SPDIF_IN_L            0x44
 201 #define A_SPDIF_IN_R            0x45
 202
 203 /* Input volume GPR */
 204 #define VOL_AHI_FRONT_L         0x00
 205 #define VOL_AHI_FRONT_R         0x01
 206 #define VOL_AHI_REAR_L          0x02
 207 #define VOL_AHI_REAR_R          0x03
 208 #define VOL_AHI_SURROUND_L      0x04
 209 #define VOL_AHI_SURROUND_R      0x05
 210 #define VOL_AHI_CENTER          0x06
 211 #define VOL_AHI_LFE             0x07
 212
 213 #define VOL_SPDIF_CD_L          0x08
 214 #define VOL_SPDIF_CD_R          0x09
 215 #define VOL_SPDIF_IN_L          0x0a
 216 #define VOL_SPDIF_IN_R          0x0b
 217
 218 /* Output volume GPR */
 219 #define VOL_SPDIF_FRONT_L       0x10
 220 #define VOL_SPDIF_FRONT_R       0x11
 221 #define VOL_SPDIF_REAR_L        0x12
 222 #define VOL_SPDIF_REAR_R        0x13
 223 #define VOL_SPDIF_SURROUND_L    0x14
 224 #define VOL_SPDIF_SURROUND_R    0x15
 225 #define VOL_SPDIF_CENTER        0x16
 226 #define VOL_SPDIF_LFE           0x17
 227
 228 #define VOL_ANALOG_FRONT_L      0x18
 229 #define VOL_ANALOG_FRONT_R      0x19
 230 #define VOL_ANALOG_REAR_L       0x1a
 231 #define VOL_ANALOG_REAR_R       0x1b
 232 #define VOL_ANALOG_SURROUND_L   0x1c
 233 #define VOL_ANALOG_SURROUND_R   0x1d
 234 #define VOL_ANALOG_CENTER       0x1e
 235 #define VOL_ANALOG_LFE          0x1f
 236
 237 /* AHI_FRONT-to-rear GPR */
 238 #define VOL_FRONT_REAR_L        0x20
 239 #define VOL_FRONT_REAR_R        0x21
 240
 241 /* AHI_SURROUND-to-rear GPR */
 242 #define VOL_SURROUND_REAR_L     0x22
 243 #define VOL_SURROUND_REAR_R     0x23
 244
 245 /* AHI_FRONT-to-center and AHI_FRONT-to-LFE GPRs */
 246 #define VOL_FRONT_CENTER        0x24
 247 #define VOL_FRONT_LFE           0x25
 248
 249 /* Temporary GPRs */
 250 #define RES_JUNK                0x7f;
 251 #define RES_AHI_FRONT_L         0x80
 252 #define RES_AHI_FRONT_R         0x81
 253 #define RES_AHI_REAR_L          0x82
 254 #define RES_AHI_REAR_R          0x83
 255 #define RES_AHI_SURROUND_L      0x84
 256 #define RES_AHI_SURROUND_R      0x85
 257 #define RES_AHI_CENTER          0x86
 258 #define RES_AHI_LFE             0x87
 259
 260 #define RES_SPDIF_CD_L          0x88
 261 #define RES_SPDIF_CD_R          0x89
 262 #define RES_SPDIF_IN_L          0x8a
 263 #define RES_SPDIF_IN_R          0x8b
 264
 265 #define SUM_FRONT_L             0x90
 266 #define SUM_FRONT_R             0x91
 267 #define SUM_REAR_L              0x92
 268 #define SUM_REAR_R              0x93
 269 #define SUM_SURROUND_L          0x94
 270 #define SUM_SURROUND_R          0x95
 271 #define SUM_CENTER              0x96
 272 #define SUM_LFE                 0x97
 273
 274 #define RES_FRONT_REAR_L        0xa0
 275 #define RES_FRONT_REAR_R        0xa1
 276 #define RES_SURROUND_REAR_L     0xa2
 277 #define RES_SURROUND_REAR_R     0xa3
 278 #define RES_FRONT_CENTER        0xa4
 279 #define RES_FRONT_LFE           0xa5
 280 #define RES_FRONT_MONO          0xa6
 281
 282 #else
 283
 284 /* PCM volume control */
 285 #define TMP_PCM_L     0x100 //temp PCM L (after the vol control)
 286 #define TMP_PCM_R     0x101
 287 #define VOL_PCM_L     0x102 //vol PCM
 288 #define VOL_PCM_R     0x103
 289
 290 /* Routing patch */
 291 #define TMP_AC_L      0x104 //tmp ac97 out
 292 #define TMP_AC_R      0x105
 293 #define TMP_REAR_L    0x106 //output - Temp Rear
 294 #define TMP_REAR_R    0x107
 295 #define TMP_DIGI_L    0x108 //output - Temp digital
 296 #define TMP_DIGI_R    0x109
 297 #define DSP_VOL_L     0x10a // main dsp volume
 298 #define DSP_VOL_R     0x10b
 299
 300 /* hw inputs */
 301 #define PCM_IN_L        0x00
 302 #define PCM_IN_R        0x01
 303
 304 #define PCM1_IN_L        0x04
 305 #define PCM1_IN_R        0x05
 306 //mutilchannel playback stream appear here:
 307
 308 #define MULTI_FRONT_L   0x08
 309 #define MULTI_FRONT_R   0x09
 310 #define MULTI_REAR_L    0x0a
 311 #define MULTI_REAR_R    0x0b
 312 #define MULTI_CENTER    0x0c
 313 #define MULTI_LFE       0x0d
 314
 315 #define AC97_IN_L       0x10
 316 #define AC97_IN_R       0x11
 317 #define SPDIF_CD_L      0x12
 318 #define SPDIF_CD_R      0x13
 319
 320 /* hw outputs */
 321 #define AC97_FRONT_L    0x20
 322 #define AC97_FRONT_R    0x21
 323 #define DIGITAL_OUT_L   0x22
 324 #define DIGITAL_OUT_R   0x23
 325 #define DIGITAL_CENTER  0x24
 326 #define DIGITAL_LFE     0x25
 327
 328 #define ANALOG_REAR_L   0x28
 329 #define ANALOG_REAR_R   0x29
 330 #define ADC_REC_L       0x2a
 331 #define ADC_REC_R       0x2b
 332
 333 #define ANALOG_CENTER   0x31
 334 #define ANALOG_LFE      0x32
 335
 336 #endif // AHI
 337
 338
 339 #define INPUT_PATCH_START(patch, nm, ln, i)             \
 340 do {                                                    \
 341         patch = PATCH(mgr, patch_n);                    \
 342         strcpy(patch->name, nm);                        \
 343         patch->code_start = pc * 2;                     \
 344         patch->input = (1<<(0x1f&ln));                  \
 345         patch->output= (1<<(0x1f&ln));                  \
 346         patch->id = i;                                  \
 347 } while(0)
 348
 349 #define INPUT_PATCH_END(patch)                          \
 350 do {                                                    \
 351         patch->code_size = pc * 2 - patch->code_start;  \
 352         patch_n++;                                      \
 353 } while(0)
 354
 355
 356 #define ROUTING_PATCH_START(patch, nm)  \
 357 do {                                    \
 358         patch = &mgr->rpatch;           \
 359         strcpy(patch->name, nm);        \
 360         patch->code_start = pc * 2;     \
 361 } while(0)
 362
 363 #define ROUTING_PATCH_END(patch)                        \
 364 do {                                                    \
 365         patch->code_size = pc * 2 - patch->code_start;      \
 366 } while(0)
 367
 368 #define CONNECT(input, output) set_bit(input, &rpatch->route[(output) - OUTPUT_BASE]);
 369
 370 #define CONNECT_V(input, output) set_bit(input, &rpatch->route_v[(output) - OUTPUT_BASE]);
 371
 372 #define OUTPUT_PATCH_START(patch, nm, ln, i)            \
 373 do {                                                    \
 374         patch = PATCH(mgr, patch_n);                    \
 375         strcpy(patch->name, nm);                        \
 376         patch->code_start = pc * 2;                     \
 377         patch->input = (1<<(0x1f&ln));                  \
 378         patch->output= (1<<(0x1f&ln));                  \
 379         patch->id = i;                                  \
 380 } while(0)
 381
 382 #define OUTPUT_PATCH_END(patch)                         \
 383 do {                                                    \
 384         patch->code_size = pc * 2 - patch->code_start;  \
 385         patch_n++;                                      \
 386 } while(0)
 387
 388 #define GET_OUTPUT_GPR(patch, g, ln)                    \
 389 do {                                                    \
 390         mgr->gpr[(g) - GPR_BASE].type = GPR_TYPE_IO;    \
 391         mgr->gpr[(g) - GPR_BASE].usage++;               \
 392         mgr->gpr[(g) - GPR_BASE].line = ln;             \
 393         set_bit((g) - GPR_BASE, patch->gpr_used);       \
 394 } while(0)
 395
 396 #define GET_INPUT_GPR(patch, g, ln)                     \
 397 do {                                                    \
 398         mgr->gpr[(g) - GPR_BASE].type = GPR_TYPE_IO;    \
 399         mgr->gpr[(g) - GPR_BASE].usage++;               \
 400         mgr->gpr[(g) - GPR_BASE].line = ln;             \
 401         set_bit((g) - GPR_BASE, patch->gpr_used);       \
 402         set_bit((g) - GPR_BASE, patch->gpr_input);      \
 403 } while(0)
 404
 405 #define GET_DYNAMIC_GPR(patch, g)                               \
 406 do {                                                            \
 407         mgr->gpr[(g) - GPR_BASE].type = GPR_TYPE_DYNAMIC;       \
 408         mgr->gpr[(g) - GPR_BASE].usage++;                       \
 409         set_bit((g) - GPR_BASE, patch->gpr_used);               \
 410 } while(0)
 411
 412 #define GET_CONTROL_GPR(patch, g, nm, a, b)                     \
 413 do {                                                            \
 414         strcpy(mgr->gpr[(g) - GPR_BASE].name, nm);              \
 415         mgr->gpr[(g) - GPR_BASE].type = GPR_TYPE_CONTROL;       \
 416         mgr->gpr[(g) - GPR_BASE].usage++;                       \
 417         mgr->gpr[(g) - GPR_BASE].min = a;                       \
 418         mgr->gpr[(g) - GPR_BASE].max = b;                       \
 419         sblive_writeptr(card, g, 0, b);                         \
 420         set_bit((g) - GPR_BASE, patch->gpr_used);               \
 421 } while(0)
 422
 423 #endif /* _EFXMGR_H */