?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
grub2: bring back build of aros-side grub2 tools
[AROS.git] / workbench / devs / networks / pcnet32 / unit.c
blobdf25c099b4fe0cd3d7649dd1714cbff6f631c2cc
1 /*
2 * $Id$
3 */
4
5 /*
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA.
20 */
21
22 #include <exec/types.h>
23 #include <exec/resident.h>
24 #include <exec/io.h>
25 #include <exec/ports.h>
26 #include <exec/errors.h>
27
28 #include <aros/io.h>
29
30 #include <devices/sana2.h>
31 #include <devices/sana2specialstats.h>
32 #include <devices/newstyle.h>
33 #include <devices/timer.h>
34
35 #include <utility/utility.h>
36 #include <utility/tagitem.h>
37 #include <utility/hooks.h>
38
39 #include <proto/exec.h>
40 #include <proto/dos.h>
41 #include <proto/oop.h>
42 #include <proto/timer.h>
43 #include <proto/utility.h>
44
45 #include <stdlib.h>
46
47 #include "pcnet32.h"
48 #include "unit.h"
49 #include LC_LIBDEFS_FILE
50
51 /* BYTE IO */
52 UBYTE readb(APTR base)
53 {
54 return BYTEIN(base);
55 }
56 void writeb(UBYTE val, APTR base)
57 {
58 BYTEOUT(base, val);
59 }
60
61 /* WORD IO */
62 UWORD readw(APTR base)
63 {
64 return WORDIN(base);
65 }
66 void writew(UWORD val, APTR base)
67 {
68 WORDOUT(base, val);
69 }
70
71 /* LONG IO */
72 ULONG readl(APTR base)
73 {
74 return *((volatile ULONG*)base);
75 }
76 void writel(ULONG val, APTR base)
77 {
78 *((volatile ULONG*)base) = val;
79 }
80
81 /* 16/32bit control funcs */
82 static UWORD pcnet32_readcsr_16(APTR base, int index)
83 {
84 writew( index, base + 0x12);
85 return readw( base + 0x10);
86 }
87
88 static void pcnet32_writecsr_16(APTR base, int index, UWORD val)
89 {
90 writew( index, base + 0x12);
91 writew( val, base + 0x10);
92 }
93
94 static UWORD pcnet32_readbcr_16(APTR base, int index)
95 {
96 writew( index, base + 0x12);
97 return readw( base + 0x16);
98 }
99
100 static void pcnet32_writebcr_16(APTR base, int index, UWORD val)
101 {
102 writew( index, base + 0x12);
103 writew( val, base + 0x16);
104 }
105
106 static UWORD pcnet32_readrap_16(APTR base)
107 {
108 return readw(base + 0x12);
109 }
110
111 static void pcnet32_writerap_16(APTR base, UWORD val)
112 {
113 writew( val, base + 0x12);
114 }
115
116 static void pcnet32_reset_16(APTR base)
117 {
118 readw(base + 0x14);
119 }
120
121 static int pcnet32_check_16(APTR base)
122 {
123 writew(88, base + 0x12);
124 return (readw( base + 0x12) == 88);
125 }
126
127 /**/
128
129 static UWORD pcnet32_readcsr_32(APTR base, int index)
130 {
131 writel( index, base + 0x14);
132 return (readl( base + 0x10) & 0xffff);
133 }
134
135 static void pcnet32_writecsr_32(APTR base, int index, UWORD val)
136 {
137 writel( index, base + 0x14);
138 writel( val, base + 0x10);
139 }
140
141 static UWORD pcnet32_readbcr_32(APTR base, int index)
142 {
143 writel( index, base + 0x14);
144 return (readl( base + 0x1c) & 0xffff);
145 }
146
147 static void pcnet32_writebcr_32(APTR base, int index, UWORD val)
148 {
149 writel( index, base + 0x14);
150 writel( val, base + 0x1c);
151 }
152
153 static UWORD pcnet32_readrap_32(APTR base)
154 {
155 return (readl(base + 0x14) & 0xffff);
156 }
157
158 static void pcnet32_writerap_32(APTR base, UWORD val)
159 {
160 writel( val, base + 0x14);
161 }
162
163 static void pcnet32_reset_32(APTR base)
164 {
165 readl(base + 0x18);
166 }
167
168 static int pcnet32_check_32(APTR base)
169 {
170 writel(88, base + 0x14);
171 return ((readw( base + 0x14) & 0xffff) == 88);
172 }
173
174 /*
175 * Report incoming events to all hyphotetical event receivers
176 */
177 VOID ReportEvents(struct PCN32Base *PCNet32Base, struct PCN32Unit *unit, ULONG events)
178 {
179 struct IOSana2Req *request, *tail, *next_request;
180 struct List *list;
181
182 list = &unit->pcnu_request_ports[EVENT_QUEUE]->mp_MsgList;
183 next_request = (APTR)list->lh_Head;
184 tail = (APTR)&list->lh_Tail;
185
186 /* Go through list of event listeners. If send messages to receivers if event found */
187 Disable();
188 while(next_request != tail)
189 {
190 request = next_request;
191 next_request = (APTR)request->ios2_Req.io_Message.mn_Node.ln_Succ;
192
193 if((request->ios2_WireError&events) != 0)
194 {
195 request->ios2_WireError = events;
196 Remove((APTR)request);
197 ReplyMsg((APTR)request);
198 }
199 }
200 Enable();
201
202 return;
203 }
204
205 struct TypeStats *FindTypeStats(struct PCN32Base *PCNet32Base, struct PCN32Unit *unit,
206 struct MinList *list, ULONG packet_type)
207 {
208 struct TypeStats *stats, *tail;
209 BOOL found = FALSE;
210
211 stats = (APTR)list->mlh_Head;
212 tail = (APTR)&list->mlh_Tail;
213
214 while(stats != tail && !found)
215 {
216 if(stats->packet_type == packet_type)
217 found = TRUE;
218 else
219 stats = (APTR)stats->node.mln_Succ;
220 }
221
222 if(!found)
223 stats = NULL;
224
225 return stats;
226 }
227
228 void FlushUnit(LIBBASETYPEPTR LIBBASE, struct PCN32Unit *unit, UBYTE last_queue, BYTE error)
229 {
230 struct IORequest *request;
231 UBYTE i;
232 struct Opener *opener, *tail;
233
234 D(bug("[pcnet32] unit.FlushUnit\n"));
235
236 /* Abort queued operations */
237
238 for (i=0; i <= last_queue; i++)
239 {
240 while ((request = (APTR)GetMsg(unit->pcnu_request_ports[i])) != NULL)
241 {
242 request->io_Error = IOERR_ABORTED;
243 ReplyMsg((struct Message *)request);
244 }
245 }
246
247 opener = (APTR)unit->pcnu_Openers.mlh_Head;
248 tail = (APTR)unit->pcnu_Openers.mlh_Tail;
249
250 /* Flush every opener's read queue */
251
252 while(opener != tail)
253 {
254 while ((request = (APTR)GetMsg(&opener->read_port)) != NULL)
255 {
256 request->io_Error = error;
257 ReplyMsg((struct Message *)request);
258 }
259 opener = (struct Opener *)opener->node.mln_Succ;
260 }
261 }
262
263 static inline void pci_push(UBYTE *base)
264 {
265 /* force out pending posted writes */
266 readl(base);
267 }
268
269 /*
270 * Interrupt handler called whenever pcnet32 NIC interface generates interrupt.
271 * It's duty is to iterate throgh RX queue searching for new packets.
272 *
273 * Please note, that allthough multicast support could be done on interface
274 * basis, it is done in this function as result of quick integration of both
275 * the forcedeth driver (IFF_ALLMULTI flag) and etherling3 driver (AddressMatch
276 * filter function).
277 */
278 AROS_INTH1(PCN32_RX_Int, struct PCN32Unit *, unit)
279 {
280 AROS_INTFUNC_INIT
281
282 struct PCN32Base *PCNet32Base = unit->pcnu_device;
283 struct fe_priv *np = unit->pcnu_fe_priv;
284 UWORD Flags;
285 struct TypeStats *tracker;
286 ULONG packet_type;
287 struct Opener *opener, *opener_tail;
288 struct IOSana2Req *request, *request_tail;
289 BOOL accepted, is_orphan;
290
291 D(bug("%s: PCN32_RX_Int() !!!!\n", unit->pcnu_name));
292 np->cur_rx = 0;
293
294 /* Endless loop, with break from inside */
295 for(;;)
296 {
297 int i;
298 UWORD len=0;
299 struct eth_frame *frame;
300
301 if (np->cur_rx >= RX_RING_SIZE)
302 break; /* we scanned the whole ring - do not continue */
303
304 /* Get the in-queue number */
305 i = np->cur_rx % RX_RING_SIZE;
306 Flags = AROS_LE2WORD(((struct rx_ring_desc *)np->ring_addr)[i].BufferStatus);
307 len = AROS_LE2WORD(((struct rx_ring_desc *)np->ring_addr)[i].BufferMsgLength);
308
309 D(bug("%s: PCN32_RX_Int: looking at packet %d:%d, Flags 0x%x, len %d\n",
310 unit->pcnu_name, np->cur_rx, i, Flags, len));
311
312 /* Do we own the packet or the chipset? */
313 if ((Flags & (1 << 15))!=0)
314 {
315 D(bug("%s: PCN32_RX_Int: packet owned by chipset\n", unit->pcnu_name));
316 goto next_pkt; /* still owned by hardware, */
317 }
318
319 D(bug("%s: PCN32_RX_Int: packet is for us\n", unit->pcnu_name));
320
321 /* the packet is for us - get it :) */
322
323 if (Flags & (1 << 7)) { // Bus Parity Error
324 D(bug("%s: PCN32_RX_Int: packet has Bus Parity error!\n", unit->pcnu_name));
325 ReportEvents(LIBBASE, unit, S2EVENT_ERROR | S2EVENT_HARDWARE | S2EVENT_RX);
326 unit->pcnu_stats.BadData++;
327 goto next_pkt;
328 }
329
330 if (Flags & (1 << 8)) { // End of Packet
331 D(bug("%s: PCN32_RX_Int: END of Packet\n", unit->pcnu_name));
332 }
333 if (Flags & (1 << 9)) { // Start of Packet
334 D(bug("%s: PCN32_RX_Int: START of Packet\n", unit->pcnu_name));
335 }
336
337 if (Flags & (1 << 10)) { // Buffer Error
338 D(bug("%s: PCN32_RX_Int: packet has CRC error!\n", unit->pcnu_name));
339 ReportEvents(LIBBASE, unit, S2EVENT_ERROR | S2EVENT_HARDWARE | S2EVENT_RX);
340 unit->pcnu_stats.BadData++;
341 goto next_pkt;
342 }
343 if (Flags & (1 << 11)) { // CRC Error
344 D(bug("%s: PCN32_RX_Int: packet has CRC error!\n", unit->pcnu_name));
345 ReportEvents(LIBBASE, unit, S2EVENT_ERROR | S2EVENT_HARDWARE | S2EVENT_RX);
346 unit->pcnu_stats.BadData++;
347 goto next_pkt;
348 }
349 if (Flags & (1 << 12)) { // OVERFLOW Error
350 D(bug("%s: PCN32_RX_Int: packet has OVERFLOW error!\n", unit->pcnu_name));
351 ReportEvents(LIBBASE, unit, S2EVENT_ERROR | S2EVENT_HARDWARE | S2EVENT_RX);
352 unit->pcnu_stats.BadData++;
353 goto next_pkt;
354 }
355 if (Flags & (1 << 13)) { // Framing Error
356 ReportEvents(LIBBASE, unit, S2EVENT_ERROR | S2EVENT_HARDWARE | S2EVENT_RX);
357 unit->pcnu_stats.BadData++;
358 goto next_pkt;
359 }
360
361 D(bug("%s: PCN32_RX_Int: packet doesnt report errors\n", unit->pcnu_name));
362
363 /* got a valid packet - forward it to the network core */
364 frame = &np->rx_buffer[i];
365 is_orphan = TRUE;
366
367 /* Dump contents of frame if DEBUG enabled */
368 #ifdef DEBUG
369 {
370 int j;
371 for (j=0; j<64; j++) {
372 if ((j%16) == 0)
373 D(bug("\n%03x:", j));
374 D(bug(" %02x", ((unsigned char*)frame)[j]));
375 }
376 D(bug("\n"));
377 }
378 #endif
379
380 /* Check for address validity */
381 if(AddressFilter(LIBBASE, unit, frame->eth_packet_dest))
382 {
383 /* Packet is addressed to this driver */
384 packet_type = AROS_BE2WORD(frame->eth_packet_type);
385 D(bug("%s: PCN32_RX_Int: Packet IP accepted with type = %d\n", unit->pcnu_name, packet_type));
386
387 opener = (APTR)unit->pcnu_Openers.mlh_Head;
388 opener_tail = (APTR)&unit->pcnu_Openers.mlh_Tail;
389
390 /* Offer packet to every opener */
391 while(opener != opener_tail)
392 {
393 request = (APTR)opener->read_port.mp_MsgList.lh_Head;
394 request_tail = (APTR)&opener->read_port.mp_MsgList.lh_Tail;
395 accepted = FALSE;
396
397 /* Offer packet to each request until it's accepted */
398 while((request != request_tail) && !accepted)
399 {
400 if((request->ios2_PacketType == packet_type)
401 || ((request->ios2_PacketType <= ETH_MTU)
402 && (packet_type <= ETH_MTU)))
403 {
404 D(bug("%s: PCN32_RX_Int: copy packet for opener ..\n", unit->pcnu_name));
405 CopyPacket(LIBBASE, unit, request, len, packet_type, frame);
406 accepted = TRUE;
407 }
408 request =
409 (struct IOSana2Req *)request->ios2_Req.io_Message.mn_Node.ln_Succ;
410 }
411
412 if(accepted)
413 is_orphan = FALSE;
414
415 opener = (APTR)opener->node.mln_Succ;
416 }
417
418 /* If packet was unwanted, give it to S2_READORPHAN request */
419 if(is_orphan)
420 {
421 unit->pcnu_stats.UnknownTypesReceived++;
422
423 if(!IsMsgPortEmpty(unit->pcnu_request_ports[ADOPT_QUEUE]))
424 {
425 CopyPacket(LIBBASE, unit,
426 (APTR)unit->pcnu_request_ports[ADOPT_QUEUE]->
427 mp_MsgList.lh_Head, len, packet_type, frame);
428 D(bug("%s: PCN32_RX_Int: packet copied to orphan queue\n", unit->pcnu_name));
429 }
430 }
431
432 /* Update remaining statistics */
433
434 tracker =
435 FindTypeStats(LIBBASE, unit, &unit->pcnu_type_trackers, packet_type);
436
437 if(tracker != NULL)
438 {
439 tracker->stats.PacketsReceived++;
440 tracker->stats.BytesReceived += len;
441 }
442 }
443
444 unit->pcnu_stats.PacketsReceived++;
445 ((struct rx_ring_desc *)np->ring_addr)[i].BufferStatus = AROS_WORD2LE((1 << 8)|(1 << 9)|(1 << 15)); // Mark packet as available again
446 next_pkt:
447 np->cur_rx++;
448 }
449
450 return FALSE;
451
452 AROS_INTFUNC_EXIT
453 }
454
455 /*
456 * Interrupt generated by Cause() to push new packets into the NIC interface
457 */
458 AROS_INTH1(PCN32_TX_Int, struct PCN32Unit *, unit)
459 {
460 AROS_INTFUNC_INIT
461
462 struct fe_priv *np = unit->pcnu_fe_priv;
463 struct PCN32Base *PCNet32Base = unit->pcnu_device;
464 int nr, try_count=1;
465 BOOL proceed = FALSE; /* Fails by default */
466
467 D(bug("%s: PCN32_TX_Int()\n", unit->pcnu_name));
468
469 /* send packet only if there is free space on tx queue. Otherwise do nothing */
470 if (!netif_queue_stopped(unit))
471 {
472 UWORD packet_size, data_size;
473 struct IOSana2Req *request;
474 struct Opener *opener;
475 UBYTE *buffer;
476 ULONG wire_error=0;
477 BYTE error;
478 struct MsgPort *port;
479 struct TypeStats *tracker;
480
481 proceed = TRUE; /* Success by default */
482 port = unit->pcnu_request_ports[WRITE_QUEUE];
483
484 /* Still no error and there are packets to be sent? */
485 while(proceed && (!IsMsgPortEmpty(port)))
486 {
487 nr = np->next_tx % TX_RING_SIZE;
488 error = 0;
489
490 if (!((((struct tx_ring_desc *)np->ring_addr)[nr + RX_RING_SIZE].BufferStatus) & (1 << 15)))
491 {
492
493 request = (APTR)port->mp_MsgList.lh_Head;
494 data_size = packet_size = request->ios2_DataLength;
495
496 opener = (APTR)request->ios2_BufferManagement;
497
498 if((request->ios2_Req.io_Flags & SANA2IOF_RAW) == 0)
499 {
500 packet_size += ETH_PACKET_DATA;
501 CopyMem(request->ios2_DstAddr, np->tx_buffer[nr].eth_packet_dest, ETH_ADDRESSSIZE);
502 CopyMem(unit->pcnu_dev_addr, np->tx_buffer[nr].eth_packet_source, ETH_ADDRESSSIZE);
503 np->tx_buffer[nr].eth_packet_type = AROS_WORD2BE(request->ios2_PacketType);
504
505 buffer = np->tx_buffer[nr].eth_packet_data;
506 }
507 else
508 buffer = (UBYTE*)&np->tx_buffer[nr];
509
510 if (!opener->tx_function(buffer, request->ios2_Data, data_size))
511 {
512 error = S2ERR_NO_RESOURCES;
513 wire_error = S2WERR_BUFF_ERROR;
514 ReportEvents(LIBBASE, unit,
515 S2EVENT_ERROR | S2EVENT_SOFTWARE | S2EVENT_BUFF
516 | S2EVENT_TX);
517 }
518
519 /* Now the packet is already in TX buffer, update flags for NIC */
520 if (error == 0)
521 {
522 Disable();
523 D(bug("%s: PCN32_TX_Int: packet %d:%d [type = %d] queued for transmission.", unit->pcnu_name, np->next_tx, nr, np->tx_buffer[nr].eth_packet_type));
524
525 /* DEBUG? Dump frame if so */
526 #ifdef DEBUG
527 {
528 int j;
529 for (j=0; j<64; j++) {
530 if ((j%16) == 0)
531 D(bug("\n%03x:", j));
532 D(bug(" %02x", ((unsigned char*)&np->tx_buffer[nr])[j]));
533 }
534 D(bug("\n"));
535 }
536 #endif
537
538 Enable();
539
540 /* Set the ring details for the packet .. */
541 ((struct tx_ring_desc *)np->ring_addr)[nr + RX_RING_SIZE].BufferLength = AROS_WORD2LE(-packet_size);
542 ((struct tx_ring_desc *)np->ring_addr)[nr + RX_RING_SIZE].Misc = 0x00000000;
543 ((struct tx_ring_desc *)np->ring_addr)[nr + RX_RING_SIZE].PacketBuffer = AROS_LONG2LE((IPTR)&np->tx_buffer[nr]);
544 ((struct tx_ring_desc *)np->ring_addr)[nr + RX_RING_SIZE].BufferStatus = AROS_WORD2LE(0x8300);
545
546 unit->write_csr((APTR)unit->pcnu_BaseMem,0, ((1 << 6)|(1 << 3))); /* .. And trigger an imediate Tx poll */
547 D(bug("%s: PCN32_TX_Int: send poll triggered.\n", unit->pcnu_name));
548 }
549
550 /* Reply packet */
551
552 request->ios2_Req.io_Error = error;
553 request->ios2_WireError = wire_error;
554 Disable();
555 Remove((APTR)request);
556 Enable();
557 ReplyMsg((APTR)request);
558
559 /* Update statistics */
560
561 if(error == 0)
562 {
563 tracker = FindTypeStats(LIBBASE, unit, &unit->pcnu_type_trackers,
564 request->ios2_PacketType);
565 if(tracker != NULL)
566 {
567 tracker->stats.PacketsSent++;
568 tracker->stats.BytesSent += packet_size;
569 }
570 }
571 try_count=0;
572 }
573 np->next_tx++;
574 try_count++;
575
576 /*
577 * If we've just run out of free space on the TX queue, stop
578 * it and give up pushing further frames
579 */
580 if ( (try_count + 1) >= TX_RING_SIZE)
581 {
582 D(bug("%s: output queue full!. Stopping [count = %d, TX_RING_SIZE = %d\n", unit->pcnu_name, try_count, TX_RING_SIZE));
583 netif_stop_queue(unit);
584 proceed = FALSE;
585 }
586 }
587 }
588
589 /* Was there success? Enable incomming of new packets */
590 if(proceed)
591 unit->pcnu_request_ports[WRITE_QUEUE]->mp_Flags = PA_SOFTINT;
592 else
593 unit->pcnu_request_ports[WRITE_QUEUE]->mp_Flags = PA_IGNORE;
594
595 return FALSE;
596
597 AROS_INTFUNC_EXIT
598 }
599
600 /*
601 * Interrupt used to restart the real one
602 */
603 AROS_INTH1(PCN32_TX_End_Int, struct PCN32Unit *, unit)
604 {
605 AROS_INTFUNC_INIT
606
607 struct PCN32Base *PCNet32Base = unit->pcnu_device;
608 struct PCN32Unit *dev = unit;
609 struct fe_priv *np = dev->pcnu_fe_priv;
610 // UBYTE *base = (UBYTE*) dev->pcnu_BaseMem;
611
612 D(bug("%s: PCN32_TX_End_Int()\n", unit->pcnu_name));
613
614 int i;
615 UWORD Flags;
616
617 for(i = 0; i < TX_RING_SIZE; i++)
618 {
619 Flags = AROS_LE2WORD(((struct tx_ring_desc *)np->ring_addr)[i + RX_RING_SIZE].BufferStatus);
620 /* Do we own the packet or the chipset? */
621 D(bug("%s: PCN32_TX_End_Int: looking at TxRing packet %d:, Flags 0x%x\n",
622 unit->pcnu_name, i, Flags));
623 if ((Flags & (1 << 15))==0)
624 {
625 D(bug("%s: PCN32_TX_End_Int: TxRing packet %d owned by us\n", unit->pcnu_name, i));
626 /* TODO: We should report send errors here .. */
627
628 if (Flags & (1 << 14))
629 {
630 D(bug("%s: PCN32_TX_End_Int: Errors occured transmitting packet\n", unit->pcnu_name));
631 if (Flags & (1 << 11))
632 {
633 D(bug("%s: PCN32_TX_End_Int: packet reports CRC Error\n", unit->pcnu_name));
634 }
635
636 if (Flags & (1 << 12))
637 {
638 D(bug("%s: PCN32_TX_End_Int: packet reports OVERFLOW error\n", unit->pcnu_name));
639 }
640
641 if (Flags & (1 << 13))
642 {
643 D(bug("%s: PCN32_TX_End_Int: packet reports FRAMING error\n", unit->pcnu_name));
644 }
645 ReportEvents(LIBBASE, unit, S2EVENT_ERROR | S2EVENT_HARDWARE | S2EVENT_TX);
646 }
647 else unit->pcnu_stats.PacketsSent++;
648
649 if ((Flags & (1 << 8))||(Flags &(1 << 9))) //(ENP | STP)
650 {
651 D(bug("%s: PCN32_TX_End_Int: freeing TxRing packet for use\n", unit->pcnu_name));
652 ((struct tx_ring_desc *)np->ring_addr)[i + RX_RING_SIZE].BufferStatus = 0;
653 ((struct tx_ring_desc *)np->ring_addr)[i + RX_RING_SIZE].PacketBuffer = 0;
654 }
655 else
656 {
657 D(bug("%s: PCN32_TX_End_Int: TxRing packet unused ..??\n", unit->pcnu_name));
658 }
659 }
660 }
661
662 return FALSE;
663
664 AROS_INTFUNC_EXIT
665 }
666
667 #if (0)
668 /*
669 * Maximum number of loops until we assume that a bit in the irq mask
670 * is stuck. Overridable with module param.
671 */
672 static const int max_interrupt_work = 5;
673 #endif
674
675 /*
676 * Handle timeouts and other strange cases
677 */
678 static AROS_INTH1(PCN32_TimeoutHandler,struct PCN32Unit *, dev)
679 {
680 AROS_INTFUNC_INIT
681
682 struct timeval time;
683 struct Device *TimerBase = dev->pcnu_TimerSlowReq->tr_node.io_Device;
684
685 GetSysTime(&time);
686 //D(bug("%s: PCN32_TimeoutHandler()\n", dev->pcnu_name));
687
688 /*
689 * If timeout timer is expected, and time elapsed - regenerate the
690 * interrupt handler
691 */
692 if (dev->pcnu_toutNEED && (CmpTime(&time, &dev->pcnu_toutPOLL ) < 0))
693 {
694 dev->pcnu_toutNEED = FALSE;
695 Cause(&dev->pcnu_tx_end_int);
696 }
697
698 return FALSE;
699
700 AROS_INTFUNC_EXIT
701 }
702
703 /*
704 * The interrupt handler - schedules code execution to proper handlers depending
705 * on the message from nForce.
706 *
707 * NOTE.
708 *
709 * Don't be surprised - this driver used to restart itself several times, in
710 * order to handle events which occur when the driver was handling previous
711 * events. It reduces the latency and amount of dropped packets. Additionally,
712 * this interrupt may put itself into deep sleep (or just quit) and restarts
713 * after certain amount of time (POLL_WAIT).
714 */
715 static AROS_INTH1(PCN32_IntHandler, struct PCN32Unit *, dev)
716 {
717 AROS_INTFUNC_INIT
718
719 // struct fe_priv *np = dev->pcnu_fe_priv;
720 // UBYTE *base = (UBYTE*) dev->pcnu_BaseMem;
721 // ULONG events;
722 // int i;
723 struct Device *TimerBase = dev->pcnu_TimerSlowReq->tr_node.io_Device;
724 struct timeval time;
725
726 GetSysTime(&time);
727 int csr_0 = 0;
728 // int csr_4 = 0;
729 D(bug("%s: PCN32_IntHandler()!!!!!!!\n", dev->pcnu_name));
730
731 while ( (csr_0 = dev->read_csr(dev->pcnu_BaseMem, 0)) & (1 << 7))
732 {
733 dev->write_csr(dev->pcnu_BaseMem, 0, csr_0);
734 D(bug("%s: PCN32_IntHandler: csr[0] : %x\n", dev->pcnu_name, csr_0));
735
736 if ( csr_0 & (1 << 0) ) // (INIT) is the card initialising?
737 {
738 D(bug("%s: PCN32_IntHandler: Chipset init detected .. ", dev->pcnu_name));
739 BOOL have_Tx = FALSE, have_Rx = FALSE;
740
741 if ( csr_0 & (1 << 1) ) // (STRT) Start/ed/ing?
742 {
743 D(bug("[STRT]"));
744 }
745
746 if ( csr_0 & (1 << 2) ) // (STOP) Chipset is stopped
747 {
748 D(bug("[STOP]"));
749 have_Tx = TRUE;
750 }
751
752 if ( csr_0 & (1 << 4) ) // (TXON) Transmitter ON?
753 {
754 D(bug("[TXON]"));
755 have_Tx = TRUE;
756 }
757 else
758 {
759 D(bug("[TXON:OFF]"));
760 }
761
762 if ( csr_0 & (1 << 5) ) // (RXON) Reciever ON?
763 {
764 D(bug("[RXON]"));
765 have_Rx = TRUE;
766 }
767 else
768 {
769 D(bug("[RXON:OFF]"));
770 }
771
772 if ( csr_0 & (1 << 8) ) // (IDON) Initialisation Done?
773 {
774 D(bug("[IDON]"));
775 }
776 D(bug("\n"));
777 if ((!(have_Tx))&&(!(have_Rx)))
778 {
779 D(bug("%s: PCN32_IntHandler: Chipset is OFFLINE!\n", dev->pcnu_name));
780 }
781 }
782
783 if ( csr_0 & (1 << 10) ) // (RINT) Chipset has Recieved packet(s)
784 {
785 D(bug("%s: PCN32_IntHandler: Packet Reception detected!\n", dev->pcnu_name));
786 Cause(&dev->pcnu_rx_int);
787 }
788
789 if ( csr_0 & (1 << 9) ) // (TINT) Chipset has Sent packet(s)
790 {
791 D(bug("%s: PCN32_IntHandler: Packet Transmition detected!\n", dev->pcnu_name));
792 Cause(&dev->pcnu_tx_end_int);
793 }
794
795 if ( csr_0 & (1 << 15) ) // (ERR) Chipset has Reported an ERROR
796 {
797 D(bug("%s: PCN32_IntHandler: (ERR) ERROR Detected\n", dev->pcnu_name));
798 break;
799 }
800 }
801
802 return FALSE;
803
804 AROS_INTFUNC_EXIT
805 }
806
807 VOID CopyPacket(struct PCN32Base *PCNet32Base, struct PCN32Unit *unit,
808 struct IOSana2Req *request, UWORD packet_size, UWORD packet_type,
809 struct eth_frame *buffer)
810 {
811 struct Opener *opener;
812 BOOL filtered = FALSE;
813 UBYTE *ptr;
814 const UBYTE broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
815
816 D(bug("%s: CopyPacket(packet @ %x, len = %d)\n", unit->pcnu_name, buffer, packet_size));
817
818 /* Set multicast and broadcast flags */
819
820 request->ios2_Req.io_Flags &= ~(SANA2IOF_BCAST | SANA2IOF_MCAST);
821 if(memcmp(buffer->eth_packet_dest, broadcast, 6) == 0)
822 {
823 request->ios2_Req.io_Flags |= SANA2IOF_BCAST;
824 D(bug("%s: CopyPacket: BROADCAST Flag set\n", unit->pcnu_name));
825 }
826 else if((buffer->eth_packet_dest[0] & 0x1) != 0)
827 {
828 request->ios2_Req.io_Flags |= SANA2IOF_MCAST;
829 D(bug("%s: CopyPacket: MULTICAST Flag set\n", unit->pcnu_name));
830 }
831
832 /* Set source and destination addresses and packet type */
833 CopyMem(buffer->eth_packet_source, request->ios2_SrcAddr, ETH_ADDRESSSIZE);
834 CopyMem(buffer->eth_packet_dest, request->ios2_DstAddr, ETH_ADDRESSSIZE);
835 request->ios2_PacketType = packet_type;
836
837 /* Adjust for cooked packet request */
838
839 if((request->ios2_Req.io_Flags & SANA2IOF_RAW) == 0)
840 {
841 packet_size -= ETH_PACKET_DATA;
842 ptr = (UBYTE*)&buffer->eth_packet_data[0];
843 }
844 else
845 {
846 ptr = (UBYTE*)buffer;
847 }
848
849 request->ios2_DataLength = packet_size;
850
851 D(bug("%s: CopyPacket: packet @ %x (%d bytes)\n", unit->pcnu_name, ptr, packet_size));
852
853 /* Filter packet */
854
855 opener = request->ios2_BufferManagement;
856 if((request->ios2_Req.io_Command == CMD_READ) &&
857 (opener->filter_hook != NULL))
858 if(!CallHookPkt(opener->filter_hook, request, ptr))
859 {
860 D(bug("%s: CopyPacket: packet filtered\n", unit->pcnu_name));
861 filtered = TRUE;
862 }
863
864 if(!filtered)
865 {
866 /* Copy packet into opener's buffer and reply packet */
867 D(bug("%s: CopyPacket: opener recieve packet .. ", unit->pcnu_name));
868 if(!opener->rx_function(request->ios2_Data, ptr, packet_size))
869 {
870 D(bug("ERROR occured!!\n"));
871 request->ios2_Req.io_Error = S2ERR_NO_RESOURCES;
872 request->ios2_WireError = S2WERR_BUFF_ERROR;
873 ReportEvents(LIBBASE, unit, S2EVENT_ERROR | S2EVENT_SOFTWARE | S2EVENT_BUFF | S2EVENT_RX);
874 }
875 else
876 {
877 D(bug("SUCCESS!!\n"));
878 }
879 Disable();
880 Remove((APTR)request);
881 Enable();
882 ReplyMsg((APTR)request);
883 D(bug("%s: CopyPacket: opener notified.\n", unit->pcnu_name));
884 }
885 }
886
887 BOOL AddressFilter(struct PCN32Base *PCNet32Base, struct PCN32Unit *unit, UBYTE *address)
888 {
889 struct AddressRange *range, *tail;
890 BOOL accept = TRUE;
891 ULONG address_left;
892 UWORD address_right;
893
894 /* Check whether address is unicast/broadcast or multicast */
895
896 address_left = AROS_BE2LONG(*((ULONG *)address));
897 address_right = AROS_BE2WORD(*((UWORD *)(address + 4)));
898
899 if((address_left & 0x01000000) != 0 &&
900 !(address_left == 0xffffffff && address_right == 0xffff))
901 {
902 /* Check if this multicast address is wanted */
903
904 range = (APTR)unit->pcnu_multicast_ranges.mlh_Head;
905 tail = (APTR)&unit->pcnu_multicast_ranges.mlh_Tail;
906 accept = FALSE;
907
908 while((range != tail) && !accept)
909 {
910 if((address_left > range->lower_bound_left ||
911 (address_left == range->lower_bound_left &&
912 address_right >= range->lower_bound_right)) &&
913 (address_left < range->upper_bound_left ||
914 (address_left == range->upper_bound_left &&
915 address_right <= range->upper_bound_right)))
916 accept = TRUE;
917 range = (APTR)range->node.mln_Succ;
918 }
919
920 if(!accept)
921 unit->pcnu_special_stats[S2SS_ETHERNET_BADMULTICAST & 0xffff]++;
922 }
923 return accept;
924 }
925
926 /*
927 * Unit process
928 */
929 AROS_UFH3(void, PCN32_Schedular,
930 AROS_UFHA(STRPTR, argPtr, A0),
931 AROS_UFHA(ULONG, argSize, D0),
932 AROS_UFHA(struct ExecBase *, SysBase, A6))
933 {
934 AROS_USERFUNC_INIT
935
936 struct PCN32Unit *dev = FindTask(NULL)->tc_UserData;
937 LIBBASETYPEPTR LIBBASE = dev->pcnu_device;
938 struct MsgPort *reply_port, *input;
939
940 D(bug("[pcnet32] PCN32_Schedular()\n"));
941 D(bug("[pcnet32] PCN32_Schedular: Setting device up\n"));
942
943 reply_port = CreateMsgPort();
944 input = CreateMsgPort();
945
946 dev->pcnu_input_port = input;
947
948 dev->pcnu_TimerSlowPort = CreateMsgPort();
949
950 if (dev->pcnu_TimerSlowPort)
951 {
952 dev->pcnu_TimerSlowReq = (struct timerequest *)
953 CreateIORequest((struct MsgPort *)dev->pcnu_TimerSlowPort, sizeof(struct timerequest));
954
955 if (dev->pcnu_TimerSlowReq)
956 {
957 if (!OpenDevice("timer.device", UNIT_VBLANK,
958 (struct IORequest *)dev->pcnu_TimerSlowReq, 0))
959 {
960 struct Message *msg = AllocVec(sizeof(struct Message), MEMF_PUBLIC|MEMF_CLEAR);
961 ULONG sigset;
962
963 D(bug("[pcnet32] PCN32_Schedular: Got VBLANK unit of timer.device\n"));
964
965 dev->initialize(dev);
966
967 msg->mn_ReplyPort = reply_port;
968 msg->mn_Length = sizeof(struct Message);
969
970 D(bug("[pcnet32] PCN32_Schedular: Setup complete. Sending handshake\n"));
971 PutMsg(LIBBASE->pcnb_syncport, msg);
972 WaitPort(reply_port);
973 GetMsg(reply_port);
974
975 FreeVec(msg);
976
977 D(bug("[pcnet32] PCN32_Schedular: entering forever loop ... \n"));
978
979 dev->pcnu_signal_0 = AllocSignal(-1);
980 dev->pcnu_signal_1 = AllocSignal(-1);
981 dev->pcnu_signal_2 = AllocSignal(-1);
982 dev->pcnu_signal_3 = AllocSignal(-1);
983
984 sigset = 1 << input->mp_SigBit |
985 1 << dev->pcnu_signal_0 |
986 1 << dev->pcnu_signal_1 |
987 1 << dev->pcnu_signal_2 |
988 1 << dev->pcnu_signal_3;
989 for(;;)
990 {
991 ULONG recvd = Wait(sigset);
992 if (recvd & 1 << dev->pcnu_signal_0)
993 {
994 /*
995 * Shutdown process. Driver should close everything
996 * already and waits for our process to complete. Free
997 * memory allocared here and kindly return.
998 */
999 dev->deinitialize(dev);
1000 CloseDevice((struct IORequest *)dev->pcnu_TimerSlowReq);
1001 DeleteIORequest((struct IORequest *)dev->pcnu_TimerSlowReq);
1002 DeleteMsgPort(dev->pcnu_TimerSlowPort);
1003 DeleteMsgPort(input);
1004 DeleteMsgPort(reply_port);
1005
1006 D(bug("[pcnet32] PCN32_Schedular: Process shutdown.\n"));
1007 return;
1008 }
1009 else if (recvd & (1 << input->mp_SigBit))
1010 {
1011 struct IOSana2Req *io;
1012
1013 /* Handle incoming transactions */
1014 while ((io = (struct IOSana2Req *)GetMsg(input))!= NULL)
1015 {
1016 D(bug("[pcnet32] PCN32_Schedular: Handle incomming transaction.\n"));
1017 ObtainSemaphore(&dev->pcnu_unit_lock);
1018 handle_request(LIBBASE, io);
1019 }
1020 }
1021 else
1022 {
1023 D(bug("[pcnet32] PCN32_Schedular: Handle incomming signal.\n"));
1024 /* Handle incoming signals */
1025 }
1026 }
1027 }
1028 }
1029 }
1030
1031 AROS_USERFUNC_EXIT
1032 }
1033
1034 /*
1035 * Create new pcnet32 ethernet device unit
1036 */
1037 struct PCN32Unit *CreateUnit(struct PCN32Base *PCNet32Base, OOP_Object *pciDevice)
1038 {
1039 struct PCN32Unit *unit = AllocMem(sizeof(struct PCN32Unit), MEMF_PUBLIC | MEMF_CLEAR);
1040 BOOL success = TRUE;
1041 int i;
1042
1043 D(bug("[pcnet32] CreateUnit()\n"));
1044
1045 if (unit != NULL)
1046 {
1047 IPTR DeviceID, base, len;
1048 OOP_Object *driver;
1049
1050 OOP_GetAttr(pciDevice, aHidd_PCIDevice_ProductID, &DeviceID);
1051 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Driver, (APTR)&driver);
1052
1053 unit->pcnu_device = PCNet32Base;
1054 unit->pcnu_DeviceID = DeviceID;
1055 unit->pcnu_mtu = ETH_MTU;
1056 unit->pcnu_PCIDevice = pciDevice;
1057 unit->pcnu_PCIDriver = driver;
1058
1059 InitSemaphore(&unit->pcnu_unit_lock);
1060 NEWLIST(&unit->pcnu_Openers);
1061 NEWLIST(&unit->pcnu_multicast_ranges);
1062 NEWLIST(&unit->pcnu_type_trackers);
1063
1064 OOP_GetAttr(pciDevice, aHidd_PCIDevice_INTLine, &unit->pcnu_IRQ);
1065 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Base1, &unit->pcnu_BaseIO);
1066 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Base0, &base);
1067 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Size0, &len);
1068
1069 unit->pcnu_BaseMem = HIDD_PCIDriver_MapPCI(driver, (APTR)base, len);
1070 unit->pcnu_SizeMem = len;
1071
1072 if (unit->pcnu_BaseMem)
1073 {
1074 struct TagItem attrs[] = {
1075 { aHidd_PCIDevice_isIO, TRUE },
1076 { aHidd_PCIDevice_isMEM, TRUE },
1077 { aHidd_PCIDevice_isMaster, TRUE },
1078 { TAG_DONE, 0 },
1079 };
1080 OOP_SetAttrs(pciDevice, (struct TagItem *)&attrs);
1081
1082 unit->pcnu_name = "[pcnet32.0]";
1083
1084 unit->pcnu_fe_priv = AllocMem(sizeof(struct fe_priv), MEMF_PUBLIC|MEMF_CLEAR);
1085
1086 unit->pcnu_fe_priv->fep_pcnet_init_block = HIDD_PCIDriver_AllocPCIMem(
1087 driver,
1088 sizeof(struct pcnet32_init_block));
1089
1090 unit->pcnu_UnitNum = 0;
1091
1092 pcn32_get_functions(unit);
1093
1094 if (unit->pcnu_fe_priv)
1095 {
1096 unit->pcnu_fe_priv->pci_dev = unit;
1097 InitSemaphore(&unit->pcnu_fe_priv->lock);
1098
1099 {
1100 struct Message *msg;
1101
1102 unit->pcnu_irqhandler.is_Node.ln_Type = NT_INTERRUPT;
1103 unit->pcnu_irqhandler.is_Node.ln_Pri = 100;
1104 unit->pcnu_irqhandler.is_Node.ln_Name = LIBBASE->pcnb_Device.dd_Library.lib_Node.ln_Name;
1105 unit->pcnu_irqhandler.is_Code = (VOID_FUNC)PCN32_IntHandler;
1106 unit->pcnu_irqhandler.is_Data = unit;
1107
1108 unit->pcnu_touthandler.is_Node.ln_Type = NT_INTERRUPT;
1109 unit->pcnu_touthandler.is_Node.ln_Pri = 100;
1110 unit->pcnu_touthandler.is_Node.ln_Name = LIBBASE->pcnb_Device.dd_Library.lib_Node.ln_Name;
1111 unit->pcnu_touthandler.is_Code = (VOID_FUNC)PCN32_TimeoutHandler;
1112 unit->pcnu_touthandler.is_Data = unit;
1113
1114 unit->pcnu_rx_int.is_Node.ln_Type = NT_INTERRUPT;
1115 unit->pcnu_rx_int.is_Node.ln_Name = unit->pcnu_name;
1116 unit->pcnu_rx_int.is_Code = (VOID_FUNC)PCN32_RX_Int;
1117 unit->pcnu_rx_int.is_Data = unit;
1118
1119 unit->pcnu_tx_int.is_Node.ln_Type = NT_INTERRUPT;
1120 unit->pcnu_tx_int.is_Node.ln_Name = unit->pcnu_name;
1121 unit->pcnu_tx_int.is_Code = (VOID_FUNC)PCN32_TX_Int;
1122 unit->pcnu_tx_int.is_Data = unit;
1123
1124 unit->pcnu_tx_end_int.is_Node.ln_Name = unit->pcnu_name;
1125 unit->pcnu_tx_end_int.is_Code = (VOID_FUNC)PCN32_TX_End_Int;
1126 unit->pcnu_tx_end_int.is_Data = unit;
1127
1128 for (i=0; i < REQUEST_QUEUE_COUNT; i++)
1129 {
1130 struct MsgPort *port = AllocMem(sizeof(struct MsgPort), MEMF_PUBLIC | MEMF_CLEAR);
1131 unit->pcnu_request_ports[i] = port;
1132
1133 if (port == NULL) success = FALSE;
1134
1135 if (success)
1136 {
1137 NEWLIST(&port->mp_MsgList);
1138 port->mp_Flags = PA_IGNORE;
1139 port->mp_SigTask = &unit->pcnu_tx_int;
1140 }
1141 }
1142
1143 unit->pcnu_request_ports[WRITE_QUEUE]->mp_Flags = PA_SOFTINT;
1144
1145 if (success)
1146 {
1147 D(bug("%s: Initialise Dev @ %x, IOBase @ %x\n", unit->pcnu_name, unit, unit->pcnu_BaseMem));
1148
1149 pcnet32_reset_16(unit->pcnu_BaseMem);
1150
1151 D(bug("%s: Chipset RESET\n", unit->pcnu_name));
1152
1153 i = pcnet32_readcsr_16(unit->pcnu_BaseMem, 0); // Check for 16bit/32bit chip IO
1154 BOOL check = pcnet32_check_16(unit->pcnu_BaseMem);
1155
1156 if ((i == 4)&&(check))
1157 {
1158 D(bug("%s: Using 16bit I/O Funcs\n", unit->pcnu_name));
1159 unit->read_csr = pcnet32_readcsr_16;
1160 unit->write_csr = pcnet32_writecsr_16;
1161 unit->read_bcr = pcnet32_readbcr_16;
1162 unit->write_bcr = pcnet32_writebcr_16;
1163 unit->read_rap = pcnet32_readrap_16;
1164 unit->write_rap = pcnet32_writerap_16;
1165 unit->reset = pcnet32_reset_16;
1166 }
1167 else
1168 {
1169 pcnet32_reset_32(unit->pcnu_BaseMem); // 32bit reset..
1170
1171 i = pcnet32_readcsr_32(unit->pcnu_BaseMem, 0);
1172 check = pcnet32_check_32(unit->pcnu_BaseMem);
1173
1174 if ((i == 4)&&(check))
1175 {
1176 D(bug("%s: Using 32bit I/O Funcs\n", unit->pcnu_name));
1177 unit->read_csr = pcnet32_readcsr_32;
1178 unit->write_csr = pcnet32_writecsr_32;
1179 unit->read_bcr = pcnet32_readbcr_32;
1180 unit->write_bcr = pcnet32_writebcr_32;
1181 unit->read_rap = pcnet32_readrap_32;
1182 unit->write_rap = pcnet32_writerap_32;
1183 unit->reset = pcnet32_reset_32;
1184 }
1185 else
1186 {
1187 D(bug("%s: Error - Unsupported chipset .. (unknown data size)\n", unit->pcnu_name));
1188 success = FALSE;
1189 }
1190 }
1191
1192 if (success)
1193 {
1194 i = (unit->read_csr(unit->pcnu_BaseMem, 88) | ( unit->read_csr(unit->pcnu_BaseMem, 89) << 16));
1195
1196 unit->pcnu_pcnet_chiprevision = (i >> 12) & 0xffff;
1197
1198 D(bug("%s: PCnet chip version %x [%x]\n", unit->pcnu_name, i, unit->pcnu_pcnet_chiprevision));
1199
1200 unit->pcnu_pcnet_supported = 0;
1201
1202 switch (unit->pcnu_pcnet_chiprevision)
1203 {
1204 case 0x2420:
1205 case 0x2430:
1206 unit->pcnu_pcnet_chipname = "PCnet/PCI 79c970";
1207 break;
1208
1209 case 0x2621:
1210 unit->pcnu_pcnet_chipname = "PCnet/PCI II 79c970A";
1211 unit->pcnu_pcnet_supported |= support_fdx;
1212 break;
1213
1214 case 0x2623:
1215 unit->pcnu_pcnet_chipname = "PCnet/FAST 79c971";
1216 unit->pcnu_pcnet_supported |= (support_fdx | support_mii | support_fset | support_ltint );
1217 break;
1218
1219 case 0x2624:
1220 unit->pcnu_pcnet_chipname = "PCnet/FAST+ 79c972";
1221 unit->pcnu_pcnet_supported |= (support_fdx | support_mii | support_fset );
1222 break;
1223
1224 case 0x2625:
1225 unit->pcnu_pcnet_chipname = "PCnet/FAST III 79c973";
1226 unit->pcnu_pcnet_supported |= (support_fdx | support_mii );
1227 break;
1228
1229 case 0x2627:
1230 unit->pcnu_pcnet_chipname = "PCnet/FAST III 79c975";
1231 unit->pcnu_pcnet_supported |= (support_fdx | support_mii );
1232 break;
1233
1234 case 0x2626:
1235 unit->pcnu_pcnet_chipname = "PCnet/Home 79c978";
1236 unit->pcnu_pcnet_supported |= support_fdx;
1237
1238 /* TODO: PCnet/Home needs extra set up .. */
1239 break;
1240 default:
1241 D(bug("%s: ERROR - Unsupported Chipset (unknown revision)\n", unit->pcnu_name));
1242 success = FALSE;
1243 }
1244 #if defined(DEBUG)
1245 D(bug("%s: Found %s chipset based NIC\n", unit->pcnu_name, unit->pcnu_pcnet_chipname));
1246 if (unit->pcnu_pcnet_supported & support_fdx)
1247 D(bug("%s: Chip Supports Full Duplex\n", unit->pcnu_name));
1248 if (unit->pcnu_pcnet_supported & support_mii)
1249 D(bug("%s: Chip Supports MII\n", unit->pcnu_name));
1250 if (unit->pcnu_pcnet_supported & support_fset)
1251 D(bug("%s: Chip Supports FSET\n", unit->pcnu_name));
1252 if (unit->pcnu_pcnet_supported & support_ltint)
1253 D(bug("%s: Chip Supports LTINT\n", unit->pcnu_name));
1254 #endif
1255
1256 if (((unit->pcnu_pcnet_chiprevision +1) & 0xfffe) == 0x2624)
1257 {
1258 i = unit->read_csr(unit->pcnu_BaseMem, 80) & 0x0c00; /* Check tx_start_pt */
1259 #if defined(DEBUG)
1260 D(bug("%s: tx_start_pt(0x%hX):", unit->pcnu_name, i));
1261 switch(i >> 10)
1262 {
1263 case 0:
1264 D(bug(" 20 bytes,"));
1265 break;
1266 case 1:
1267 D(bug(" 64 bytes,"));
1268 break;
1269 case 2:
1270 D(bug(" 128 bytes,"));
1271 break;
1272 case 3:
1273 D(bug("~220 bytes,"));
1274 break;
1275 }
1276 #endif
1277 i = unit->read_bcr(unit->pcnu_BaseMem, 18); /* Check burst/bus control */
1278 #if defined(DEBUG)
1279 D(bug(" BCR18(%hX):", i & 0xffff));
1280 if (i & (1 << 5))
1281 D(bug("BurstWrEn "));
1282 if (i & (1 << 6))
1283 D(bug("BurstRdEn "));
1284 if (i & (1 << 7))
1285 D(bug("32bitIO "));
1286 if (i & (1 << 11))
1287 D(bug("NoUFlow "));
1288 #endif
1289 i = unit->read_bcr(unit->pcnu_BaseMem, 25);
1290 D(bug(" SRAMSIZE=0x%hX,", i << 8));
1291 i = unit->read_bcr(unit->pcnu_BaseMem, 26);
1292 D(bug(" SRAM_BND=0x%hX,", i << 8));
1293 i = unit->read_bcr(unit->pcnu_BaseMem, 27);
1294 #if defined(DEBUG)
1295 if (i & (1 << 14))
1296 D(bug("LowLatRx"));
1297 #endif
1298 D(bug("\n"));
1299 }
1300 }
1301 }
1302
1303 if (success)
1304 {
1305 LIBBASE->pcnb_syncport = CreateMsgPort();
1306
1307 unit->pcnu_Process = CreateNewProcTags(
1308 NP_Entry, (IPTR)PCN32_Schedular,
1309 NP_Name, PCNET32_TASK_NAME,
1310 NP_Priority, 0,
1311 NP_UserData, (IPTR)unit,
1312 NP_StackSize, 140960,
1313 TAG_DONE);
1314
1315 WaitPort(LIBBASE->pcnb_syncport);
1316 msg = GetMsg(LIBBASE->pcnb_syncport);
1317 ReplyMsg(msg);
1318 DeleteMsgPort(LIBBASE->pcnb_syncport);
1319
1320 D(bug("[pcnet32] Unit up and running\n"));
1321
1322 return unit;
1323 }
1324 else
1325 {
1326 D(bug("%s: ERRORS occured during Device setup - ABORTING\n", unit->pcnu_name));
1327 }
1328 }
1329 }
1330 }
1331 else
1332 {
1333 D(bug("[pcnet32] PANIC! Couldn't get MMIO area. Aborting\n"));
1334 }
1335 }
1336 DeleteUnit(PCNet32Base, unit);
1337 return NULL;
1338 }
1339
1340 /*
1341 * DeleteUnit - removes selected unit. Frees all resources and structures.
1342 *
1343 * The caller should be sure, that given unit is really ready to be freed.
1344 */
1345
1346 void DeleteUnit(struct PCN32Base *PCNet32Base, struct PCN32Unit *Unit)
1347 {
1348 int i;
1349 if (Unit)
1350 {
1351 if (Unit->pcnu_Process)
1352 {
1353 /* Tell our process to quit, and wait until it does so */
1354 Signal(&Unit->pcnu_Process->pr_Task, 1 << Unit->pcnu_signal_0);
1355 while (FindTask(PCNET32_TASK_NAME) != NULL)
1356 Delay(5);
1357 }
1358
1359 for (i=0; i < REQUEST_QUEUE_COUNT; i++)
1360 {
1361 if (Unit->pcnu_request_ports[i] != NULL)
1362 FreeMem(Unit->pcnu_request_ports[i], sizeof(struct MsgPort));
1363
1364 Unit->pcnu_request_ports[i] = NULL;
1365 }
1366
1367 if (Unit->pcnu_fe_priv)
1368 {
1369 FreeMem(Unit->pcnu_fe_priv, sizeof(struct fe_priv));
1370 Unit->pcnu_fe_priv = NULL;
1371 }
1372
1373 if (Unit->pcnu_BaseMem)
1374 {
1375 HIDD_PCIDriver_UnmapPCI(Unit->pcnu_PCIDriver,
1376 (APTR)Unit->pcnu_BaseMem,
1377 Unit->pcnu_SizeMem);
1378 }
1379
1380 FreeMem(Unit, sizeof(struct PCN32Unit));
1381 }
1382 }
1383
1384 static struct AddressRange *FindMulticastRange(LIBBASETYPEPTR LIBBASE, struct PCN32Unit *unit,
1385 ULONG lower_bound_left, UWORD lower_bound_right, ULONG upper_bound_left, UWORD upper_bound_right)
1386 {
1387 struct AddressRange *range, *tail;
1388 BOOL found = FALSE;
1389
1390 range = (APTR)unit->pcnu_multicast_ranges.mlh_Head;
1391 tail = (APTR)&unit->pcnu_multicast_ranges.mlh_Tail;
1392
1393 while((range != tail) && !found)
1394 {
1395 if((lower_bound_left == range->lower_bound_left) &&
1396 (lower_bound_right == range->lower_bound_right) &&
1397 (upper_bound_left == range->upper_bound_left) &&
1398 (upper_bound_right == range->upper_bound_right))
1399 found = TRUE;
1400 else
1401 range = (APTR)range->node.mln_Succ;
1402 }
1403
1404 if(!found)
1405 range = NULL;
1406
1407 return range;
1408 }
1409
1410 BOOL AddMulticastRange(LIBBASETYPEPTR LIBBASE, struct PCN32Unit *unit, const UBYTE *lower_bound,
1411 const UBYTE *upper_bound)
1412 {
1413 struct AddressRange *range;
1414 ULONG lower_bound_left, upper_bound_left;
1415 UWORD lower_bound_right, upper_bound_right;
1416
1417 lower_bound_left = AROS_BE2LONG(*((ULONG *)lower_bound));
1418 lower_bound_right = AROS_BE2WORD(*((UWORD *)(lower_bound + 4)));
1419 upper_bound_left = AROS_BE2LONG(*((ULONG *)upper_bound));
1420 upper_bound_right = AROS_BE2WORD(*((UWORD *)(upper_bound + 4)));
1421
1422 range = FindMulticastRange(LIBBASE, unit, lower_bound_left, lower_bound_right,
1423 upper_bound_left, upper_bound_right);
1424
1425 if(range != NULL)
1426 range->add_count++;
1427 else
1428 {
1429 range = AllocMem(sizeof(struct AddressRange), MEMF_PUBLIC);
1430 if(range != NULL)
1431 {
1432 range->lower_bound_left = lower_bound_left;
1433 range->lower_bound_right = lower_bound_right;
1434 range->upper_bound_left = upper_bound_left;
1435 range->upper_bound_right = upper_bound_right;
1436 range->add_count = 1;
1437
1438 Disable();
1439 AddTail((APTR)&unit->pcnu_multicast_ranges, (APTR)range);
1440 Enable();
1441
1442 if (unit->pcnu_range_count++ == 0)
1443 {
1444 unit->pcnu_flags |= IFF_ALLMULTI;
1445 unit->set_multicast(unit);
1446 }
1447 }
1448 }
1449
1450 return range != NULL;
1451 }
1452
1453 BOOL RemMulticastRange(LIBBASETYPEPTR LIBBASE, struct PCN32Unit *unit, const UBYTE *lower_bound, const UBYTE *upper_bound)
1454 {
1455 struct AddressRange *range;
1456 ULONG lower_bound_left, upper_bound_left;
1457 UWORD lower_bound_right, upper_bound_right;
1458
1459 lower_bound_left = AROS_BE2LONG(*((ULONG *)lower_bound));
1460 lower_bound_right = AROS_BE2WORD(*((UWORD *)(lower_bound + 4)));
1461 upper_bound_left = AROS_BE2LONG(*((ULONG *)upper_bound));
1462 upper_bound_right = AROS_BE2WORD(*((UWORD *)(upper_bound + 4)));
1463
1464 range = FindMulticastRange(LIBBASE, unit, lower_bound_left, lower_bound_right,
1465 upper_bound_left, upper_bound_right);
1466
1467 if(range != NULL)
1468 {
1469 if(--range->add_count == 0)
1470 {
1471 Disable();
1472 Remove((APTR)range);
1473 Enable();
1474 FreeMem(range, sizeof(struct AddressRange));
1475
1476 if (--unit->pcnu_range_count == 0)
1477 {
1478 unit->pcnu_flags &= ~IFF_ALLMULTI;
1479 unit->set_multicast(unit);
1480 }
1481 }
1482 }
1483 return range != NULL;
1484 }
1485
Mirror of AROS' svn.