workbench/devs/networks/realtek8180/realtek8187.h

   1 /*
   2
   3 Copyright (C) 2011 Neil Cafferkey
   4
   5 This program is free software; you can redistribute it and/or modify
   6 it under the terms of the GNU General Public License as published by
   7 the Free Software Foundation; either version 2 of the License, or
   8 (at your option) any later version.
   9
  10 This program is distributed in the hope that it will be useful, but
  11 WITHOUT ANY WARRANTY; without even the implied warranty of
  12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13 General Public License for more details.
  14
  15 You should have received a copy of the GNU General Public License
  16 along with this program; if not, write to the Free Software
  17 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18 MA 02111-1307, USA.
  19
  20 */
  21
  22 #ifndef REALTEK8187_H
  23 #define REALTEK8187_H
  24
  25
  26 /* General */
  27 /* ======= */
  28
  29 #define R8180_MAXDESCSIZE 0x20
  30
  31
  32 /* Registers */
  33 /* ========= */
  34
  35 #define R8180REG_ADDRESS           0x00
  36 #define R8180REG_MAR               0x08
  37 #define R8180REG_RXFIFOCOUNT       0x10
  38 #define R8180REG_TXFIFOCOUNT       0x12
  39 #define R8180REG_BQREQ             0x13
  40 #define R8180REG_TSFT              0x18
  41 #define R8180REG_TLPDA             0x20
  42 #define R8180REG_TNPDA             0x24
  43 #define R8180REG_THPDA             0x28
  44 #define R8180REG_BRSR              0x2c
  45 #define R8180REG_BSSID             0x2e
  46 #define R8180REG_RESPRATE          0x34
  47 #define R8180REG_EIFS              0x35
  48 #define R8180REG_COMMAND           0x37
  49 #define R8180REG_INTMASK           0x3c
  50 #define R8180REG_INTSTATUS         0x3e
  51 #define R8180REG_TXCONF            0x40
  52 #define R8180REG_RXCONF            0x44
  53 #define R8180REG_INTTIMEOUT        0x48
  54 #define R8180REG_TBDA              0x4c
  55 #define R8180REG_EEPROM            0x50
  56 #define R8180REG_CONFIG0           0x51
  57 #define R8180REG_CONFIG1           0x52
  58 #define R8180REG_CONFIG2           0x53
  59 #define R8180REG_ANAPARAM1         0x54
  60 #define R8180REG_MSR               0x58
  61 #define R8180REG_CONFIG3           0x59
  62 #define R8180REG_CONFIG4           0x5a
  63 #define R8180REG_TESTR             0x5b
  64 #define R8180REG_PGSELECT          0x5e
  65 #define R8180REG_SECURITY          0x5f
  66 #define R8180REG_ANAPARAM2         0x60
  67 #define R8180REG_BEACONINTERVAL    0x70
  68 #define R8180REG_ATIMWINDOW        0x72
  69 #define R8180REG_BEACONINTERVAL2   0x74
  70 #define R8180REG_ATIMTRINTERVAL    0x76
  71 #define R8180REG_PHYDELAY          0x78
  72 #define R8180REG_SENSECOUNT        0x79
  73 #define R8180REG_PHY               0x7c
  74 #define R8180REG_RFPINSOUTPUT      0x80
  75 #define R8180REG_RFPINSENABLE      0x82
  76 #define R8180REG_RFPINSSELECT      0x84
  77 #define R8180REG_RFPINSINPUT       0x86
  78 #define R8180REG_RFPARA            0x88
  79 #define R8180REG_RFTIMING          0x8c
  80 #define R8180REG_GPENABLE          0x90
  81 #define R8180REG_GPIO0             0x91
  82 #define R8180REG_GPIO1             0x92
  83 #define R8180REG_HSSIPARA          0x94
  84 #define R8180REG_TXAGCCTL          0x9c
  85 #define R8180REG_TXGAINCCK         0x9d
  86 #define R8180REG_TXGAINOFDM        0x9e
  87 #define R8180REG_TXANTENNA         0x9f
  88 #define R8180REG_WPACONF           0xb0
  89 #define R8180REG_SIFS              0xb4
  90 #define R8180REG_DIFS              0xb5
  91 #define R8180REG_SLOT              0xb6
  92 #define R8180REG_CWCONF            0xbc
  93 #define R8180REG_CWVAL             0xbd
  94 #define R8180REG_RATEFALLBACK      0xbe
  95 #define R8180REG_ACMCONTROL        0xbf
  96 #define R8180REG_CONFIG5           0xd8
  97 #define R8180REG_TXDMAPOLLING      0xd9
  98 #define R8180REG_CWR               0xdc
  99 #define R8180REG_RETRYCOUNT        0xde
 100 #define R8180REG_INTMIG            0xe2
 101 #define R8180REG_RDSAR             0xe4
 102 #define R8180REG_TIDACMAP          0xe8
 103 #define R8180REG_ANAPARAM3         0xee
 104 #define R8180REG_FEMR              0xf4
 105 #define R8180REG_TALLYCOUNT        0xfa
 106 #define R8180REG_TALLYSELECT       0xfc
 107 #define R8180REG_REVISION          0xfe   /* Page 1 */
 108
 109 /* RTL8187B */
 110
 111 #define R8180REG_ACVO              0xf0
 112 #define R8180REG_ACVI              0xf4
 113 #define R8180REG_ACBE              0xf8
 114 #define R8180REG_ACBK              0xfc
 115
 116
 117 /* EEPROM Data Offsets */
 118 /* =================== */
 119
 120 #define R8180ROM_BASEPOWER  0x5
 121 #define R8180ROM_RFCHIPID   0x6
 122 #define R8180ROM_ADDRESS0   0x7
 123 #define R8180ROM_ADDRESS1   0x8
 124 #define R8180ROM_ADDRESS2   0x9
 125 #define R8180ROM_POWER0    0x16
 126 #define R8180ROM_POWER2    0x1b
 127 #define R8180ROM_POWER1    0x3d
 128 #define R8180ROM_SWREV     0x3f
 129
 130
 131 /* Commands */
 132 /* ======== */
 133
 134 /* USB Control Pipe Commands */
 135
 136 #define R8180UCMD_REG 0x5
 137
 138 /* EEPROM Commands */
 139
 140 #define R8180ECMD_LOAD    (1 << 6)
 141 #define R8180ECMD_PROGRAM (2 << 6)
 142 #define R8180ECMD_CONFIG  (3 << 6)
 143
 144
 145 /* Register Details */
 146 /* ================ */
 147
 148 /* Command Register */
 149
 150 #define R8180REG_COMMANDB_RESET    4
 151 #define R8180REG_COMMANDB_RXENABLE 3
 152 #define R8180REG_COMMANDB_TXENABLE 2
 153
 154 #define R8180REG_COMMANDF_RESET    (1 << R8180REG_COMMANDB_RESET)
 155 #define R8180REG_COMMANDF_RXENABLE (1 << R8180REG_COMMANDB_RXENABLE)
 156 #define R8180REG_COMMANDF_TXENABLE (1 << R8180REG_COMMANDB_TXENABLE)
 157
 158 /* TX Configuration Register */
 159
 160 #define R8180REG_TXCONFB_HWSEQNUM    30
 161 #define R8180REG_TXCONFB_DISREQQSIZE 28
 162 #define R8180REG_TXCONFB_HWVER       25
 163 #define R8180REG_TXCONFB_MAXDMA      21
 164 #define R8180REG_TXCONFB_LOOPBACK    17
 165 #define R8180REG_TXCONFB_HWCRC       16
 166 #define R8180REG_TXCONFB_SHORTTRIES   8
 167 #define R8180REG_TXCONFB_LONGTRIES    0
 168
 169 #define R8180REG_TXCONFF_HWSEQNUM    (1 << R8180REG_TXCONFB_HWSEQNUM)
 170 #define R8180REG_TXCONFF_DISREQQSIZE (1 << R8180REG_TXCONFB_DISREQQSIZE)
 171 #define R8180REG_TXCONFF_HWVER       (7 << R8180REG_TXCONFB_HWVER)
 172 #define R8180REG_TXCONFF_MAXDMA      (7 << R8180REG_TXCONFB_MAXDMA)
 173 #define R8180REG_TXCONFF_LOOPBACK    (3 << R8180REG_TXCONFB_LOOPBACK)
 174 #define R8180REG_TXCONFF_SHORTTRIES  (0xff << R8180REG_TXCONFB_SHORTTRIES)
 175 #define R8180REG_TXCONFF_LONGTRIES   (0xff << R8180REG_TXCONFB_LONGTRIES)
 176
 177 /* RX Configuration Register */
 178
 179 #define R8180REG_RXCONFB_EARLYTHRESH  31
 180 #define R8180REG_RXCONFB_AUTORESETPHY 28
 181 #define R8180REG_RXCONFB_CHECKBSSID   23
 182 #define R8180REG_RXCONFB_MGMT         20
 183 #define R8180REG_RXCONFB_CTRL         19
 184 #define R8180REG_RXCONFB_DATA         18
 185 #define R8180REG_RXCONFB_FIFOTHRESH   13
 186 #define R8180REG_RXCONFB_MAXDMA        8
 187 #define R8180REG_RXCONFB_BCAST         3
 188 #define R8180REG_RXCONFB_MCAST         2
 189 #define R8180REG_RXCONFB_UCAST         1
 190
 191 #define R8180REG_RXCONFF_EARLYTHRESH  (1 << R8180REG_RXCONFB_EARLYTHRESH)
 192 #define R8180REG_RXCONFF_AUTORESETPHY (1 << R8180REG_RXCONFB_AUTORESETPHY)
 193 #define R8180REG_RXCONFF_CHECKBSSID   (1 << R8180REG_RXCONFB_CHECKBSSID)
 194 #define R8180REG_RXCONFF_MGMT         (1 << R8180REG_RXCONFB_MGMT)
 195 #define R8180REG_RXCONFF_CTRL         (1 << R8180REG_RXCONFB_CTRL)
 196 #define R8180REG_RXCONFF_DATA         (1 << R8180REG_RXCONFB_DATA)
 197 #define R8180REG_RXCONFF_FIFOTHRESH   (7 << R8180REG_RXCONFB_FIFOTHRESH)
 198 #define R8180REG_RXCONFF_MAXDMA       (7 << R8180REG_RXCONFB_MAXDMA)
 199 #define R8180REG_RXCONFF_BCAST        (1 << R8180REG_RXCONFB_BCAST)
 200 #define R8180REG_RXCONFF_MCAST        (1 << R8180REG_RXCONFB_MCAST)
 201 #define R8180REG_RXCONFF_UCAST        (1 << R8180REG_RXCONFB_UCAST)
 202
 203 /* EEPROM Command Register */
 204
 205 #define R8180REG_EEPROMB_COMMAND 6
 206 #define R8180REG_EEPROMB_SELECT  3
 207 #define R8180REG_EEPROMB_CLK     2
 208 #define R8180REG_EEPROMB_DATAOUT 1
 209 #define R8180REG_EEPROMB_DATAIN  0
 210
 211 #define R8180REG_EEPROMF_COMMAND (0x3 << R8180REG_EEPROMB_COMMAND)
 212 #define R8180REG_EEPROMF_SELECT  (1 << R8180REG_EEPROMB_SELECT)
 213 #define R8180REG_EEPROMF_CLK     (1 << R8180REG_EEPROMB_CLK)
 214 #define R8180REG_EEPROMF_DATAOUT (1 << R8180REG_EEPROMB_DATAOUT)
 215 #define R8180REG_EEPROMF_DATAIN  (1 << R8180REG_EEPROMB_DATAIN)
 216
 217 /* MSR Register */
 218
 219 #define R8180REG_MSRB_ENEDCA     4
 220 #define R8180REG_MSRB_LINK       2
 221
 222 #define R8180REG_MSRF_ENEDCA     (1 << R8180REG_MSRB_ENEDCA)
 223 #define R8180REG_MSRF_LINK       (0x3 << R8180REG_MSRB_LINK)
 224
 225 /* Configuration Register 3 */
 226
 227 #define R8180REG_CONFIG3B_GNTSELECT     7
 228 #define R8180REG_CONFIG3B_ANAPARAMWRITE 6
 229
 230 #define R8180REG_CONFIG3F_GNTSELECT     (1 << R8180REG_CONFIG3B_GNTSELECT)
 231 #define R8180REG_CONFIG3F_ANAPARAMWRITE (1 << R8180REG_CONFIG3B_ANAPARAMWRITE)
 232
 233 /* TX AGC Control Register */
 234
 235 #define R8180REG_TXAGCCTLB_PPGAINSHIFT   0
 236 #define R8180REG_TXAGCCTLB_PPANTSELSHIFT 1
 237 #define R8180REG_TXAGCCTLB_FEEDBACKANT   2
 238
 239 #define R8180REG_TXAGCCTLF_PPGAINSHIFT   (1 << R8180REG_TXAGCCTLB_PPGAINSHIFT)
 240 #define R8180REG_TXAGCCTLF_PPANTSELSHIFT (1 << R8180REG_TXAGCCTLB_PPANTSELSHIFT)
 241 #define R8180REG_TXAGCCTLF_FEEDBACKANT   (1 << R8180REG_TXAGCCTLB_FEEDBACKANT)
 242
 243 /* CW Configuration Register */
 244
 245 #define R8180REG_CWCONFB_PPRETRYSHIFT 1
 246 #define R8180REG_CWCONFB_PPCWSHIFT    0
 247
 248 #define R8180REG_CWCONFF_PPRETRYSHIFT (1 << R8180REG_CWCONFB_PPRETRYSHIFT)
 249 #define R8180REG_CWCONFF_PPCWSHIFT    (1 << R8180REG_CWCONFB_PPCWSHIFT)
 250
 251 /* Rate Fallback Register */
 252
 253 #define R8180REG_RATEFALLBACKB_ENABLE 7
 254
 255 #define R8180REG_RATEFALLBACKF_ENABLE (1 << R8180REG_RATEFALLBACKB_ENABLE)
 256
 257
 258 /* Frame descriptor */
 259 /* ================ */
 260
 261 #define R8180FRM_TXCONTROL 0x0
 262 #define R8180FRM_RTSDUR    0x4
 263 #define R8180FRM_TXDUR     0xe
 264 #define R8180FRM_RETRY     0x14
 265 #define R8180FRM_HEADER    0x20
 266
 267 #define R8180FRM_RXSTATUS  0x0
 268
 269 /* TX Control field */
 270
 271 #define R8180FRM_TXCONTROLB_FIRSTFRAG 29
 272 #define R8180FRM_TXCONTROLB_LASTFRAG  28
 273 #define R8180FRM_TXCONTROLB_RATE      24
 274 #define R8180FRM_TXCONTROLB_RTSRATE   19
 275 #define R8180FRM_TXCONTROLB_NOENC     15
 276
 277 #define R8180FRM_TXCONTROLF_FIRSTFRAG (1 << R8180FRM_TXCONTROLB_FIRSTFRAG)
 278 #define R8180FRM_TXCONTROLF_LASTFRAG  (1 << R8180FRM_TXCONTROLB_LASTFRAG)
 279 #define R8180FRM_TXCONTROLF_RATE      (0xf << R8180FRM_TXCONTROLB_RATE)
 280 #define R8180FRM_TXCONTROLF_RTSRATE   (0xf << R8180FRM_TXCONTROLB_RTSRATE)
 281 #define R8180FRM_TXCONTROLF_NOENC     (1 << R8180FRM_TXCONTROLB_NOENC)
 282
 283 /* RX Status field */
 284
 285 #define R8180FRM_RXSTATUSB_DMAERR   27
 286 #define R8180FRM_RXSTATUSB_OVERFLOW 26
 287 #define R8180FRM_RXSTATUSB_RXERR    15
 288 #define R8180FRM_RXSTATUSB_BADCRC   13
 289 #define R8180FRM_RXSTATUSB_BADICV   12
 290 #define R8180FRM_RXSTATUSB_LENGTH    0
 291
 292 #define R8180FRM_RXSTATUSF_DMAERR   (1 << R8180FRM_RXSTATUSB_DMAERR)
 293 #define R8180FRM_RXSTATUSF_OVERFLOW (1 << R8180FRM_RXSTATUSB_OVERFLOW)
 294 #define R8180FRM_RXSTATUSF_RXERR    (1 << R8180FRM_RXSTATUSB_RXERR)
 295 #define R8180FRM_RXSTATUSF_BADCRC   (1 << R8180FRM_RXSTATUSB_BADCRC)
 296 #define R8180FRM_RXSTATUSF_BADICV   (1 << R8180FRM_RXSTATUSB_BADICV)
 297 #define R8180FRM_RXSTATUSF_LENGTH   (0xfff << R8180FRM_RXSTATUSB_LENGTH)
 298
 299 #endif