workbench/devs/networks/rhine/rhine.h

   1 /*
   2
   3 Copyright (C) 2011-2012 Neil Cafferkey
   4
   5 This program is free software; you can redistribute it and/or modify
   6 it under the terms of the GNU General Public License as published by
   7 the Free Software Foundation; either version 2 of the License, or
   8 (at your option) any later version.
   9
  10 This program is distributed in the hope that it will be useful, but
  11 WITHOUT ANY WARRANTY; without even the implied warranty of
  12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13 General Public License for more details.
  14
  15 You should have received a copy of the GNU General Public License
  16 along with this program; if not, write to the Free Software
  17 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18 MA 02111-1307, USA.
  19
  20 */
  21
  22 #ifndef RHINE_H
  23 #define RHINE_H
  24
  25
  26 /* General */
  27 /* ======= */
  28
  29 #define RH_DESCSIZE 0x10
  30
  31
  32 /* Registers */
  33 /* ========= */
  34
  35 #define RH_REG_ADDRESS       0x0
  36 #define RH_REG_RXCONFIG      0x6
  37 #define RH_REG_TXCONFIG      0x7
  38 #define RH_REG_CONTROL       0x8
  39 #define RH_REG_CONTROL1      0x9
  40 #define RH_REG_INTSTATUS     0xc
  41 #define RH_REG_INTMASK       0xe
  42 #define RH_REG_MCASTFILTER  0x10
  43 #define RH_REG_RXLIST       0x18
  44 #define RH_REG_TXLIST       0x1c
  45 #define RH_REG_MIICONFIG    0x6c
  46 #define RH_REG_PCIBUSCONFIG 0x6e
  47 #define RH_REG_MIICTRL      0x70
  48 #define RH_REG_MIIREGNO     0x71
  49 #define RH_REG_MIIDATA      0x72
  50 #define RH_REG_EEPROM       0x74
  51 #define RH_REG_MIIINTMASK   0x86
  52
  53
  54 /* Interrupts */
  55 /* ========== */
  56
  57 #define RH_INTB_TXERR  3
  58 #define RH_INTB_RXERR  2
  59 #define RH_INTB_TXOK   1
  60 #define RH_INTB_RXOK   0
  61
  62 #define RH_INTF_TXERR (1 << RH_INTB_TXERR)
  63 #define RH_INTF_RXERR (1 << RH_INTB_RXERR)
  64 #define RH_INTF_TXOK  (1 << RH_INTB_TXOK)
  65 #define RH_INTF_RXOK  (1 << RH_INTB_RXOK)
  66
  67
  68 /* Register Details */
  69 /* ================ */
  70
  71 /* RX Configuration Register */
  72
  73 #define RH_REG_RXCONFIGB_ALLUCAST 4
  74 #define RH_REG_RXCONFIGB_BCAST    3
  75 #define RH_REG_RXCONFIGB_MCAST    2
  76
  77 #define RH_REG_RXCONFIGF_ALLUCAST (1 << RH_REG_RXCONFIGB_ALLUCAST)
  78 #define RH_REG_RXCONFIGF_BCAST    (1 << RH_REG_RXCONFIGB_BCAST)
  79 #define RH_REG_RXCONFIGF_MCAST    (1 << RH_REG_RXCONFIGB_MCAST)
  80
  81 /* Control Register (0) */
  82
  83 #define RH_REG_CONTROLB_NOTXPOLL 11
  84 #define RH_REG_CONTROLB_RXPOLL    6
  85 #define RH_REG_CONTROLB_TXPOLL    5
  86 #define RH_REG_CONTROLB_TXENABLE  4
  87 #define RH_REG_CONTROLB_RXENABLE  3
  88 #define RH_REG_CONTROLB_STOP      2
  89 #define RH_REG_CONTROLB_START     1
  90
  91 #define RH_REG_CONTROLF_NOTXPOLL (1 << RH_REG_CONTROLB_NOTXPOLL)
  92 #define RH_REG_CONTROLF_RXPOLL   (1 << RH_REG_CONTROLB_RXPOLL)
  93 #define RH_REG_CONTROLF_TXPOLL   (1 << RH_REG_CONTROLB_TXPOLL)
  94 #define RH_REG_CONTROLF_RXENABLE (1 << RH_REG_CONTROLB_RXENABLE)
  95 #define RH_REG_CONTROLF_TXENABLE (1 << RH_REG_CONTROLB_TXENABLE)
  96 #define RH_REG_CONTROLF_STOP     (1 << RH_REG_CONTROLB_STOP)
  97 #define RH_REG_CONTROLF_START    (1 << RH_REG_CONTROLB_START)
  98
  99 /* Control Register 1 */
 100
 101 #define RH_REG_CONTROL1B_RESET    7
 102
 103 #define RH_REG_CONTROL1F_RESET    (1 << RH_REG_CONTROL1B_RESET)
 104
 105 /* MII Configuration Register */
 106
 107 #define RH_REG_MIICONFIGB_PHYADDR  0
 108
 109 #define RH_REG_MIICONFIGF_PHYADDR  (0x1f << RH_REG_MIICONFIGB_PHYADDR)
 110
 111 /* MII Control Register */
 112
 113 #define RH_REG_MIICTRLB_AUTOPOLL  7
 114 #define RH_REG_MIICTRLB_READ      6
 115 #define RH_REG_MIICTRLB_WRITE     5
 116 #define RH_REG_MIICTRLB_NOPROGRAM 4
 117 #define RH_REG_MIICTRLB_DIRECTION 3
 118 #define RH_REG_MIICTRLB_DATAIN    2
 119 #define RH_REG_MIICTRLB_DATAOUT   1
 120 #define RH_REG_MIICTRLB_CLK       0
 121
 122 #define RH_REG_MIICTRLF_AUTOPOLL  (1 << RH_REG_MIICTRLB_AUTOPOLL)
 123 #define RH_REG_MIICTRLF_READ      (1 << RH_REG_MIICTRLB_READ)
 124 #define RH_REG_MIICTRLF_WRITE     (1 << RH_REG_MIICTRLB_WRITE)
 125 #define RH_REG_MIICTRLF_NOPROGRAM (1 << RH_REG_MIICTRLB_PROGRAM)
 126 #define RH_REG_MIICTRLF_DIRECTION (1 << RH_REG_MIICTRLB_DIRECTION)
 127 #define RH_REG_MIICTRLF_DATAIN    (1 << RH_REG_MIICTRLB_DATAIN)
 128 #define RH_REG_MIICTRLF_DATAOUT   (1 << RH_REG_MIICTRLB_DATAOUT)
 129 #define RH_REG_MIICTRLF_CLK       (1 << RH_REG_MIICTRLB_CLK)
 130
 131 /* EEPROM Register */
 132
 133 #define RH_REG_EEPROMB_READY   7
 134 #define RH_REG_EEPROMB_LOAD    5
 135 #define RH_REG_EEPROMB_PROGRAM 4
 136 #define RH_REG_EEPROMB_SELECT  3
 137 #define RH_REG_EEPROMB_CLK     2
 138 #define RH_REG_EEPROMB_DATAOUT 1
 139 #define RH_REG_EEPROMB_DATAIN  0
 140
 141 #define RH_REG_EEPROMF_READY   (1 << RH_REG_EEPROMB_READY)
 142 #define RH_REG_EEPROMF_LOAD    (1 << RH_REG_EEPROMB_LOAD)
 143 #define RH_REG_EEPROMF_PROGRAM (1 << RH_REG_EEPROMB_PROGRAM)
 144 #define RH_REG_EEPROMF_SELECT  (1 << RH_REG_EEPROMB_SELECT)
 145 #define RH_REG_EEPROMF_CLK     (1 << RH_REG_EEPROMB_CLK)
 146 #define RH_REG_EEPROMF_DATAOUT (1 << RH_REG_EEPROMB_DATAOUT)
 147 #define RH_REG_EEPROMF_DATAIN  (1 << RH_REG_EEPROMB_DATAIN)
 148
 149
 150 /* Frame descriptor */
 151 /* ================ */
 152
 153 #define RH_DESC_TXSTATUS  0
 154 #define RH_DESC_RXSTATUS  0
 155 #define RH_DESC_TXCONTROL 1
 156 #define RH_DESC_RXCONTROL 1
 157 #define RH_DESC_DATA      2
 158 #define RH_DESC_NEXT      3
 159
 160 /* TX Status field */
 161
 162 #define RH_DESC_TXSTATUSB_INUSE     31
 163 #define RH_DESC_TXSTATUSB_TXERR     15
 164 #define RH_DESC_TXSTATUSB_UNDERFLOW 11
 165
 166 #define RH_DESC_TXSTATUSF_INUSE     (1 << RH_DESC_TXSTATUSB_INUSE)
 167 #define RH_DESC_TXSTATUSF_TXERR     (1 << RH_DESC_TXSTATUSB_TXERR)
 168 #define RH_DESC_TXSTATUSF_UNDERFLOW (1 << RH_DESC_TXSTATUSB_UNDERFLOW)
 169
 170 /* RX Status field */
 171
 172 #define RH_DESC_RXSTATUSB_INUSE     31
 173 #define RH_DESC_RXSTATUSB_LENGTH    16
 174 #define RH_DESC_RXSTATUSB_OK        15
 175 #define RH_DESC_RXSTATUSB_MCAST     13
 176 #define RH_DESC_RXSTATUSB_BCAST     12
 177 #define RH_DESC_RXSTATUSB_UCAST     11
 178 #define RH_DESC_RXSTATUSB_CHAIN     10
 179 #define RH_DESC_RXSTATUSB_FIRSTFRAG  9
 180 #define RH_DESC_RXSTATUSB_LASTFRAG   8
 181 #define RH_DESC_RXSTATUSB_BADRING    7
 182 #define RH_DESC_RXSTATUSB_RUNT       5
 183 #define RH_DESC_RXSTATUSB_LONG       4
 184 #define RH_DESC_RXSTATUSB_OVERFLOW   3
 185 #define RH_DESC_RXSTATUSB_BADALIGN   2
 186 #define RH_DESC_RXSTATUSB_BADCRC     1
 187 #define RH_DESC_RXSTATUSB_RXERR      0
 188
 189 #define RH_DESC_RXSTATUSF_INUSE     (1 << RH_DESC_RXSTATUSB_INUSE)
 190 #define RH_DESC_RXSTATUSF_LENGTH    (0x7fff << RH_DESC_RXSTATUSB_LENGTH)
 191 #define RH_DESC_RXSTATUSF_OK        (1 << RH_DESC_RXSTATUSB_OK)
 192 #define RH_DESC_RXSTATUSF_MCAST     (1 << RH_DESC_RXSTATUSB_MCAST)
 193 #define RH_DESC_RXSTATUSF_BCAST     (1 << RH_DESC_RXSTATUSB_BCAST)
 194 #define RH_DESC_RXSTATUSF_UCAST     (1 << RH_DESC_RXSTATUSB_UCAST)
 195 #define RH_DESC_RXSTATUSF_CHAIN     (1 << RH_DESC_RXSTATUSB_CHAIN)
 196 #define RH_DESC_RXSTATUSF_FIRSTFRAG (1 << RH_DESC_RXSTATUSB_FIRSTFRAG)
 197 #define RH_DESC_RXSTATUSF_LASTFRAG  (1 << RH_DESC_RXSTATUSB_LASTFRAG)
 198 #define RH_DESC_RXSTATUSF_BADRING   (1 << RH_DESC_RXSTATUSB_BADRING)
 199 #define RH_DESC_RXSTATUSF_RUNT      (1 << RH_DESC_RXSTATUSB_RUNT)
 200 #define RH_DESC_RXSTATUSF_LONG      (1 << RH_DESC_RXSTATUSB_LONG)
 201 #define RH_DESC_RXSTATUSF_OVERFLOW  (1 << RH_DESC_RXSTATUSB_OVERFLOW)
 202 #define RH_DESC_RXSTATUSF_BADALIGN  (1 << RH_DESC_RXSTATUSB_BADALIGN)
 203 #define RH_DESC_RXSTATUSF_BADCRC    (1 << RH_DESC_RXSTATUSB_BADCRC)
 204 #define RH_DESC_RXSTATUSF_RXERR     (1 << RH_DESC_RXSTATUSB_RXERR)
 205
 206 /* TX Control field */
 207
 208 #define RH_DESC_TXCONTROLB_INT       23
 209 #define RH_DESC_TXCONTROLB_LASTFRAG  22
 210 #define RH_DESC_TXCONTROLB_FIRSTFRAG 21
 211 #define RH_DESC_TXCONTROLB_NOCRC     16
 212 #define RH_DESC_TXCONTROLB_CHAIN     15
 213 #define RH_DESC_TXCONTROLB_LENGTH     0
 214
 215 #define RH_DESC_TXCONTROLF_INT       (1 << RH_DESC_TXCONTROLB_INT)
 216 #define RH_DESC_TXCONTROLF_LASTFRAG  (1 << RH_DESC_TXCONTROLB_LASTFRAG)
 217 #define RH_DESC_TXCONTROLF_FIRSTFRAG (1 << RH_DESC_TXCONTROLB_FIRSTFRAG)
 218 #define RH_DESC_TXCONTROLF_NOCRC     (1 << RH_DESC_TXCONTROLB_NOCRC)
 219 #define RH_DESC_TXCONTROLF_CHAIN     (1 << RH_DESC_TXCONTROLB_CHAIN)
 220 #define RH_DESC_TXCONTROLF_LENGTH    (0x7fff << RH_DESC_TXCONTROLB_LENGTH)
 221
 222 #endif