workbench/libs/mesa/src/gallium/drivers/nvc0/nvc0_tex.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "nvc0_context.h"
  24 #include "nvc0_resource.h"
  25 #include "nv50/nv50_texture.xml.h"
  26
  27 #include "util/u_format.h"
  28
  29 #define NV50_TIC_0_SWIZZLE__MASK                      \
  30    (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK |   \
  31     NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK)
  32
  33 static INLINE uint32_t
  34 nv50_tic_swizzle(uint32_t tc, unsigned swz, boolean tex_int)
  35 {
  36    switch (swz) {
  37    case PIPE_SWIZZLE_RED:
  38       return (tc & NV50_TIC_0_MAPR__MASK) >> NV50_TIC_0_MAPR__SHIFT;
  39    case PIPE_SWIZZLE_GREEN:
  40       return (tc & NV50_TIC_0_MAPG__MASK) >> NV50_TIC_0_MAPG__SHIFT;
  41    case PIPE_SWIZZLE_BLUE:
  42       return (tc & NV50_TIC_0_MAPB__MASK) >> NV50_TIC_0_MAPB__SHIFT;
  43    case PIPE_SWIZZLE_ALPHA:
  44       return (tc & NV50_TIC_0_MAPA__MASK) >> NV50_TIC_0_MAPA__SHIFT;
  45    case PIPE_SWIZZLE_ONE:
  46       return tex_int ? NV50_TIC_MAP_ONE_INT : NV50_TIC_MAP_ONE_FLOAT;
  47    case PIPE_SWIZZLE_ZERO:
  48    default:
  49       return NV50_TIC_MAP_ZERO;
  50    }
  51 }
  52
  53 struct pipe_sampler_view *
  54 nvc0_create_sampler_view(struct pipe_context *pipe,
  55                          struct pipe_resource *texture,
  56                          const struct pipe_sampler_view *templ)
  57 {
  58    const struct util_format_description *desc;
  59    uint32_t *tic;
  60    uint32_t swz[4];
  61    uint32_t depth;
  62    struct nv50_tic_entry *view;
  63    struct nvc0_miptree *mt = nvc0_miptree(texture);
  64    boolean tex_int;
  65
  66    view = MALLOC_STRUCT(nv50_tic_entry);
  67    if (!view)
  68       return NULL;
  69
  70    view->pipe = *templ;
  71    view->pipe.reference.count = 1;
  72    view->pipe.texture = NULL;
  73    view->pipe.context = pipe;
  74
  75    view->id = -1;
  76
  77    pipe_resource_reference(&view->pipe.texture, texture);
  78
  79    tic = &view->tic[0];
  80
  81    desc = util_format_description(view->pipe.format);
  82
  83    /* TIC[0] */
  84
  85    tic[0] = nvc0_format_table[view->pipe.format].tic;
  86
  87    tex_int = FALSE; /* XXX: integer textures */
  88
  89    swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r, tex_int);
  90    swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
  91    swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
  92    swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
  93    tic[0] = (tic[0] & ~NV50_TIC_0_SWIZZLE__MASK) |
  94       (swz[0] << NV50_TIC_0_MAPR__SHIFT) |
  95       (swz[1] << NV50_TIC_0_MAPG__SHIFT) |
  96       (swz[2] << NV50_TIC_0_MAPB__SHIFT) |
  97       (swz[3] << NV50_TIC_0_MAPA__SHIFT);
  98
  99    tic[1] = /* mt->base.bo->offset; */ 0;
 100    tic[2] = /* mt->base.bo->offset >> 32 */ 0;
 101
 102    tic[2] |= 0x10001000 | NV50_TIC_2_NO_BORDER;
 103
 104    if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
 105       tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
 106
 107    if (mt->base.base.target != PIPE_TEXTURE_RECT)
 108       tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
 109
 110    tic[2] |=
 111       ((mt->base.bo->tile_mode & 0x0f0) << (22 - 4)) |
 112       ((mt->base.bo->tile_mode & 0xf00) << (25 - 8));
 113
 114    depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
 115
 116    if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY ||
 117        mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) {
 118       /* there doesn't seem to be a base layer field in TIC */
 119       tic[1] = view->pipe.u.tex.first_layer * mt->layer_stride;
 120       depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
 121    }
 122
 123    switch (mt->base.base.target) {
 124    case PIPE_TEXTURE_1D:
 125       tic[2] |= NV50_TIC_2_TARGET_1D;
 126       break;
 127    case PIPE_TEXTURE_2D:
 128       tic[2] |= NV50_TIC_2_TARGET_2D;
 129       break;
 130    case PIPE_TEXTURE_RECT:
 131       tic[2] |= NV50_TIC_2_TARGET_RECT;
 132       break;
 133    case PIPE_TEXTURE_3D:
 134       tic[2] |= NV50_TIC_2_TARGET_3D;
 135       break;
 136    case PIPE_TEXTURE_CUBE:
 137       depth /= 6;
 138       if (depth > 1)
 139          tic[2] |= NV50_TIC_2_TARGET_CUBE_ARRAY;
 140       else
 141          tic[2] |= NV50_TIC_2_TARGET_CUBE;
 142       break;
 143    case PIPE_TEXTURE_1D_ARRAY:
 144       tic[2] |= NV50_TIC_2_TARGET_1D_ARRAY;
 145       break;
 146    case PIPE_TEXTURE_2D_ARRAY:
 147       tic[2] |= NV50_TIC_2_TARGET_2D_ARRAY;
 148       break;
 149    case PIPE_BUFFER:
 150       tic[2] |= NV50_TIC_2_TARGET_BUFFER | NV50_TIC_2_LINEAR;
 151       break;
 152    default:
 153       NOUVEAU_ERR("invalid texture target: %d\n", mt->base.base.target);
 154       return FALSE;
 155    }
 156
 157    if (mt->base.base.target == PIPE_BUFFER)
 158       tic[3] = mt->base.base.width0;
 159    else
 160       tic[3] = 0x00300000;
 161
 162    tic[4] = (1 << 31) | mt->base.base.width0;
 163
 164    tic[5] = mt->base.base.height0 & 0xffff;
 165    tic[5] |= depth << 16;
 166    tic[5] |= mt->base.base.last_level << 28;
 167
 168    tic[6] = 0x03000000;
 169
 170    tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
 171
 172    return &view->pipe;
 173 }
 174
 175 static boolean
 176 nvc0_validate_tic(struct nvc0_context *nvc0, int s)
 177 {
 178    struct nouveau_channel *chan = nvc0->screen->base.channel;
 179    struct nouveau_bo *txc = nvc0->screen->txc;
 180    unsigned i;
 181    boolean need_flush = FALSE;
 182
 183    for (i = 0; i < nvc0->num_textures[s]; ++i) {
 184       struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
 185       struct nv04_resource *res;
 186
 187       if (!tic) {
 188          BEGIN_RING(chan, RING_3D(BIND_TIC(s)), 1);
 189          OUT_RING  (chan, (i << 1) | 0);
 190          continue;
 191       }
 192       res = &nvc0_miptree(tic->pipe.texture)->base;
 193
 194       if (tic->id < 0) {
 195          uint32_t offset = tic->tic[1];
 196
 197          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 198
 199          MARK_RING (chan, 9 + 8, 4);
 200          BEGIN_RING(chan, RING_MF(OFFSET_OUT_HIGH), 2);
 201          OUT_RELOCh(chan, txc, tic->id * 32, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 202          OUT_RELOCl(chan, txc, tic->id * 32, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 203          BEGIN_RING(chan, RING_MF(LINE_LENGTH_IN), 2);
 204          OUT_RING  (chan, 32);
 205          OUT_RING  (chan, 1);
 206          BEGIN_RING(chan, RING_MF(EXEC), 1);
 207          OUT_RING  (chan, 0x100111);
 208          BEGIN_RING_NI(chan, RING_MF(DATA), 8);
 209          OUT_RING  (chan, tic->tic[0]);
 210          OUT_RELOCl(chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 211          OUT_RELOC (chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
 212                     NOUVEAU_BO_HIGH | NOUVEAU_BO_OR, tic->tic[2], tic->tic[2]);
 213          OUT_RINGp (chan, &tic->tic[3], 5);
 214
 215          need_flush = TRUE;
 216       } else
 217       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 218          BEGIN_RING(chan, RING_3D(TEX_CACHE_CTL), 1);
 219          OUT_RING  (chan, (tic->id << 4) | 1);
 220       }
 221       nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
 222
 223       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 224       res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
 225
 226       nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_TEXTURES, res,
 227                                NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 228
 229       BEGIN_RING(chan, RING_3D(BIND_TIC(s)), 1);
 230       OUT_RING  (chan, (tic->id << 9) | (i << 1) | 1);
 231    }
 232    for (; i < nvc0->state.num_textures[s]; ++i) {
 233       BEGIN_RING(chan, RING_3D(BIND_TIC(s)), 1);
 234       OUT_RING  (chan, (i << 1) | 0);
 235    }
 236    nvc0->state.num_textures[s] = nvc0->num_textures[s];
 237
 238    return need_flush;
 239 }
 240
 241 void nvc0_validate_textures(struct nvc0_context *nvc0)
 242 {
 243    boolean need_flush;
 244
 245    need_flush  = nvc0_validate_tic(nvc0, 0);
 246    need_flush |= nvc0_validate_tic(nvc0, 4);
 247
 248    if (need_flush) {
 249       BEGIN_RING(nvc0->screen->base.channel, RING_3D(TIC_FLUSH), 1);
 250       OUT_RING  (nvc0->screen->base.channel, 0);
 251    }
 252 }
 253
 254 static boolean
 255 nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
 256 {
 257    struct nouveau_channel *chan = nvc0->screen->base.channel;
 258    unsigned i;
 259    boolean need_flush = FALSE;
 260
 261    for (i = 0; i < nvc0->num_samplers[s]; ++i) {
 262       struct nv50_tsc_entry *tsc = nv50_tsc_entry(nvc0->samplers[s][i]);
 263
 264       if (!tsc) {
 265          BEGIN_RING(chan, RING_3D(BIND_TSC(s)), 1);
 266          OUT_RING  (chan, (i << 4) | 0);
 267          continue;
 268       }
 269       if (tsc->id < 0) {
 270          tsc->id = nvc0_screen_tsc_alloc(nvc0->screen, tsc);
 271
 272          nvc0_m2mf_push_linear(&nvc0->base, nvc0->screen->txc,
 273                                65536 + tsc->id * 32, NOUVEAU_BO_VRAM,
 274                                32, tsc->tsc);
 275          need_flush = TRUE;
 276       }
 277       nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
 278
 279       BEGIN_RING(chan, RING_3D(BIND_TSC(s)), 1);
 280       OUT_RING  (chan, (tsc->id << 12) | (i << 4) | 1);
 281    }
 282    for (; i < nvc0->state.num_samplers[s]; ++i) {
 283       BEGIN_RING(chan, RING_3D(BIND_TSC(s)), 1);
 284       OUT_RING  (chan, (i << 4) | 0);
 285    }
 286    nvc0->state.num_samplers[s] = nvc0->num_samplers[s];
 287
 288    return need_flush;
 289 }
 290
 291 void nvc0_validate_samplers(struct nvc0_context *nvc0)
 292 {
 293    boolean need_flush;
 294
 295    need_flush  = nvc0_validate_tsc(nvc0, 0);
 296    need_flush |= nvc0_validate_tsc(nvc0, 4);
 297
 298    if (need_flush) {
 299       BEGIN_RING(nvc0->screen->base.channel, RING_3D(TSC_FLUSH), 1);
 300       OUT_RING  (nvc0->screen->base.channel, 0);
 301    }
 302 }