| blob | f911889ae7ae1fca70230050760977178e609469 |
1 /*
2 * mx51_tzic.h
3 *
4 * Created on: Jun 6, 2013
5 * Author: michal
6 */
8 #ifndef MX51_TZIC_H_
9 #define MX51_TZIC_H_
11 #define MX51_IRQ_ESDHC1 1
12 #define MX51_IRQ_ESDHC2 2
13 #define MX51_IRQ_ESDHC3 3
14 #define MX51_IRQ_ESDHC4 4
15 #define MX51_IRQ_DAP 5
16 #define MX51_IRQ_SDMA 6
17 #define MX51_IRQ_IOMUX 7
18 #define MX51_IRQ_NFC 8
19 #define MX51_IRQ_VPU 9
20 #define MX51_IRQ_IPUEX_ERR 10
21 #define MX51_IRQ_IPUEX_SYNC 11
22 #define MX51_IRQ_GPU3D 12
23 #define MX51_IRQ_USBOH3_HOST1 14
24 #define MX51_IRQ_EMI 15
25 #define MX51_IRQ_USBOH3_HOST2 16
26 #define MX51_IRQ_USBOH3_HOST3 17
27 #define MX51_IRQ_USBOH3_OTG 18
28 #define MX51_IRQ_SAHARA_TZ 19
29 #define MX51_IRQ_SAHARA 20
30 #define MX51_IRQ_SCC_HI_PRI 21
31 #define MX51_IRQ_SCC_TZ 22
32 #define MX51_IRQ_SCC 23
33 #define MX51_IRQ_SRTC 24
34 #define MX51_IRQ_SRTC_TZ 25
35 #define MX51_IRQ_RTIC_TZ 26
36 #define MX51_IRQ_CSU 27
37 #define MX51_IRQ_SSI1 29
38 #define MX51_IRQ_SSI2 30
39 #define MX51_IRQ_UART_1 31
40 #define MX51_IRQ_UART_2 32
41 #define MX51_IRQ_UART_3 33
42 #define MX51_IRQ_ECSPI_1 36
43 #define MX51_IRQ_ECSPI_2 37
44 #define MX51_IRQ_CSPI 38
45 #define MX51_IRQ_GPT 39
46 #define MX51_IRQ_EPIT_1 40
47 #define MX51_IRQ_EPIT_2 41
48 #define MX51_IRQ_GPIO1_INT7 42
49 #define MX51_IRQ_GPIO1_INT6 43
50 #define MX51_IRQ_GPIO1_INT5 44
51 #define MX51_IRQ_GPIO1_INT4 45
52 #define MX51_IRQ_GPIO1_INT3 46
53 #define MX51_IRQ_GPIO1_INT2 47
54 #define MX51_IRQ_GPIO1_INT1 48
55 #define MX51_IRQ_GPIO1_INT0 49
56 #define MX51_IRQ_GPIO1_INT0_15 50
57 #define MX51_IRQ_GPIO1_INT16_31 51
58 #define MX51_IRQ_GPIO2_INT0_15 52
59 #define MX51_IRQ_GPIO2_INT16_31 53
60 #define MX51_IRQ_GPIO3_INT0_15 54
61 #define MX51_IRQ_GPIO3_INT16_31 55
62 #define MX51_IRQ_GPIO4_INT0_15 56
63 #define MX51_IRQ_GPIO4_INT16_31 57
64 #define MX51_IRQ_WDOG1 58
65 #define MX51_IRQ_WDOG2 59
66 #define MX51_IRQ_KPP 60
67 #define MX51_IRQ_PWM1 61
68 #define MX51_IRQ_I2C1 62
69 #define MX51_IRQ_I2C2 63
70 #define MX51_IRQ_HS_I2C 64
71 #define MX51_IRQ_SIM_1 67
72 #define MX51_IRQ_SIM_2 68
73 #define MX51_IRQ_IIM 69
74 #define MX51_IRQ_PATA 70
75 #define MX51_IRQ_CCM_1 71
76 #define MX51_IRQ_CCM_2 72
77 #define MX51_IRQ_GPC_1 73
78 #define MX51_IRQ_GPC_2 74
79 #define MX51_IRQ_SRC 75
80 #define MX51_IRQ_TIGERP_1 76
81 #define MX51_IRQ_TIGERP_2 77
82 #define MX51_IRQ_TIGERP_3 78
83 #define MX51_IRQ_TIGERP_4 79
84 #define MX51_IRQ_TIGERP_5 80
85 #define MX51_IRQ_GPU2D 84
86 #define MX51_IRQ_GPU2D_BUSY 85
87 #define MX51_IRQ_FEC 87
88 #define MX51_IRQ_OWIRE 88
89 #define MX51_IRQ_TIGERP_6 89
90 #define MX51_IRQ_SJC 90
91 #define MX51_IRQ_SPDIF 91
92 #define MX51_IRQ_TVE 92
93 #define MX51_IRQ_FIRI 93
94 #define MX51_IRQ_PWM2 94
95 #define MX51_IRQ_SSI3 96
96 #define MX51_IRQ_EMI_BOOT 97
97 #define MX51_IRQ_TIGERP_7 98
98 #define MX51_IRQ_VPU 100
99 #define MX51_IRQ_EMI_COMPLETE 101
100 #define MX51_IRQ_GPU3D 102