arch/arm-native/kernel/platform_bcm2708.c

   1 /*
   2     Copyright © 2015, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <aros/types/spinlock_s.h>
   7 #include <aros/kernel.h>
   8 #include <aros/symbolsets.h>
   9
  10 #include "kernel_base.h"
  11
  12 #include <proto/kernel.h>
  13 #include <proto/exec.h>
  14
  15 #include <inttypes.h>
  16 #include <hardware/intbits.h>
  17
  18 #include <strings.h>
  19
  20 #include "kernel_intern.h"
  21 #include "kernel_debug.h"
  22 #include "kernel_cpu.h"
  23 #include "kernel_interrupts.h"
  24 #include "kernel_intr.h"
  25 #include "kernel_fb.h"
  26
  27 #include "exec_platform.h"
  28
  29 #define ARM_PERIIOBASE __arm_arosintern.ARMI_PeripheralBase
  30 #include <hardware/bcm2708.h>
  31 #include <hardware/bcm2708_boot.h>
  32 #include <hardware/pl011uart.h>
  33
  34 #define IRQBANK_POINTER(bank)   ((bank == 0) ? GPUIRQ_ENBL0 : (bank == 1) ? GPUIRQ_ENBL1 : ARMIRQ_ENBL)
  35
  36 #define IRQ_BANK1       0x00000100
  37 #define IRQ_BANK2       0x00000200
  38
  39 #define D(x) x
  40 #define DIRQ(x)
  41 #define DFIQ(x)
  42 #define DTIMER(x)
  43
  44 extern void mpcore_trampoline();
  45 extern uint32_t mpcore_end;
  46 extern uint32_t mpcore_pde;
  47 extern spinlock_t startup_lock;
  48
  49 extern void cpu_Register(void);
  50 extern void arm_flush_cache(uint32_t, uint32_t);
  51 #if defined(__AROSEXEC_SMP__)
  52 extern void handle_ipi(uint32_t, uint32_t);
  53
  54 struct cpu_ipidata
  55 {
  56     uint32_t    ipi_data[4];
  57 };
  58
  59 struct cpu_ipidata *bcm2708_cpuipid[4] = { 0, 0, 0, 0};
  60 #endif
  61
  62 static void bcm2708_init(APTR _kernelBase, APTR _sysBase)
  63 {
  64     struct ExecBase *SysBase = (struct ExecBase *)_sysBase;
  65     struct KernelBase *KernelBase = (struct KernelBase *)_kernelBase;
  66
  67     KrnSpinInit(&startup_lock);
  68
  69     D(bug("[Kernel:BCM2708] %s()\n", __PRETTY_FUNCTION__));
  70
  71     if (__arm_arosintern.ARMI_PeripheralBase == (APTR)BCM2836_PERIPHYSBASE)
  72     {
  73         void *trampoline_src = mpcore_trampoline;
  74         void *trampoline_dst = (void *)BOOTMEMADDR(bm_mctrampoline);
  75         uint32_t trampoline_length = (uintptr_t)&mpcore_end - (uintptr_t)mpcore_trampoline;
  76         uint32_t trampoline_data_offset = (uintptr_t)&mpcore_pde - (uintptr_t)mpcore_trampoline;
  77         int cpu;
  78         uint32_t *cpu_stack;
  79         uint32_t *cpu_fiq_stack;
  80         uint32_t tmp;
  81         tls_t   *__tls;
  82
  83         bug("[Kernel:BCM2708] Initialising Multicore System\n");
  84         D(bug("[Kernel:BCM2708] %s: Copy SMP trampoline from %p to %p (%d bytes)\n", __PRETTY_FUNCTION__, trampoline_src, trampoline_dst, trampoline_length));
  85
  86         bcopy(trampoline_src, trampoline_dst, trampoline_length);
  87
  88         D(bug("[Kernel:BCM2708] %s: Patching data for trampoline at offset %d\n", __PRETTY_FUNCTION__, trampoline_data_offset));
  89
  90         asm volatile ("mrc p15, 0, %0, c2, c0, 0":"=r"(tmp));
  91         ((uint32_t *)(trampoline_dst + trampoline_data_offset))[0] = tmp; // pde
  92         ((uint32_t *)(trampoline_dst + trampoline_data_offset))[1] = (uint32_t)cpu_Register;
  93
  94         for (cpu = 1; cpu < 4; cpu ++)
  95         {
  96             cpu_stack = (uint32_t *)AllocMem(AROS_STACKSIZE*sizeof(uint32_t), MEMF_CLEAR); /* MEMF_PRIVATE */
  97             ((uint32_t *)(trampoline_dst + trampoline_data_offset))[2] = (uint32_t)&cpu_stack[AROS_STACKSIZE-sizeof(IPTR)];
  98
  99             cpu_fiq_stack = (uint32_t *)AllocMem(1024*sizeof(uint32_t), MEMF_CLEAR); /* MEMF_PRIVATE */
 100             ((uint32_t *)(trampoline_dst + trampoline_data_offset))[4] = (uint32_t)&cpu_fiq_stack[1024-sizeof(IPTR)];
 101
 102
 103 #if defined(__AROSEXEC_SMP)
 104             __tls =  (tls_t *)AllocMem(sizeof(tls_t) + sizeof(struct cpu_ipidata),  MEMF_CLEAR); /* MEMF_PRIVATE */
 105 #else
 106             __tls =  (tls_t *)AllocMem(sizeof(tls_t),  MEMF_CLEAR); /* MEMF_PRIVATE */
 107 #endif
 108             __tls->SysBase = _sysBase;
 109             __tls->KernelBase = _kernelBase;
 110             __tls->ThisTask = NULL;
 111             arm_flush_cache(((uint32_t)__tls) & ~63, 512);
 112             ((uint32_t *)(trampoline_dst + trampoline_data_offset))[3] = (uint32_t)__tls;
 113
 114             D(bug("[Kernel:BCM2708] %s: Attempting to wake CPU #%02d\n", __PRETTY_FUNCTION__, cpu));
 115             D(bug("[Kernel:BCM2708] %s: CPU #%02d Stack @ 0x%p (sp=0x%p)\n", __PRETTY_FUNCTION__, cpu, cpu_stack, ((uint32_t *)(trampoline_dst + trampoline_data_offset))[2]));
 116             D(bug("[Kernel:BCM2708] %s: CPU #%02d FIQ Stack @ 0x%p (sp=0x%p)\n", __PRETTY_FUNCTION__, cpu, cpu_fiq_stack, ((uint32_t *)(trampoline_dst + trampoline_data_offset))[4]));
 117             D(bug("[Kernel:BCM2708] %s: CPU #%02d TLS @ 0x%p\n", __PRETTY_FUNCTION__, cpu, ((uint32_t *)(trampoline_dst + trampoline_data_offset))[3]));
 118
 119             arm_flush_cache((uint32_t)trampoline_dst, 512);
 120
 121             /* Lock the startup spinlock */
 122             KrnSpinLock(&startup_lock, NULL, SPINLOCK_MODE_WRITE);
 123
 124             /* Wake up the cpu */
 125             *((uint32_t *)(BCM2836_MAILBOX3_SET0 + (0x10 * cpu))) = (uint32_t)trampoline_dst;
 126
 127             /*
 128                  * Try to obtain spinlock again.
 129                  * This should put this cpu to sleep since the locked was already obtained. Once the cpu startup
 130                  * is ready, it will call KrnSpinUnLock too
 131                  */
 132                 KrnSpinLock(&startup_lock, NULL, SPINLOCK_MODE_WRITE);
 133                 KrnSpinUnLock(&startup_lock);
 134         }
 135     }
 136 }
 137
 138 static void bcm2708_init_cpu(APTR _kernelBase, APTR _sysBase)
 139 {
 140     struct ExecBase *SysBase = (struct ExecBase *)_sysBase;
 141     struct KernelBase *KernelBase = (struct KernelBase *)_kernelBase;
 142 #if defined(__AROSEXEC_SMP__)
 143     tls_t   *__tls = TLS_PTR_GET();
 144 #endif
 145     int cpunum = GetCPUNumber();
 146
 147     D(bug("[Kernel:BCM2708] %s(#%02d)\n", __PRETTY_FUNCTION__, cpunum));
 148
 149     /* Clear all pending FIQ sources on mailboxes */
 150     *((uint32_t *)(BCM2836_MAILBOX0_CLR0 + (16 * cpunum))) = 0xffffffff;
 151     *((uint32_t *)(BCM2836_MAILBOX1_CLR0 + (16 * cpunum))) = 0xffffffff;
 152     *((uint32_t *)(BCM2836_MAILBOX2_CLR0 + (16 * cpunum))) = 0xffffffff;
 153     *((uint32_t *)(BCM2836_MAILBOX3_CLR0 + (16 * cpunum))) = 0xffffffff;
 154
 155 #if defined(__AROSEXEC_SMP__)
 156     bcm2708_cpuipid[cpunum] = (unsigned int)__tls + sizeof(tls_t);
 157     D(bug("[Kernel:BCM2708] %s: CPU #%02d IPI data @ 0x%p\n", __PRETTY_FUNCTION__, cpunum, bcm2708_cpuipid[cpunum]));
 158
 159     // enable FIQ mailbox interupt
 160     *((uint32_t *)(BCM2836_MAILBOX_INT_CTRL0 + (0x4 * cpunum))) = 0x10;
 161 #endif
 162 }
 163
 164 static unsigned int bcm2708_get_time(void)
 165 {
 166     return *((volatile unsigned int *)(SYSTIMER_CLO));
 167 }
 168
 169 static void bcm2708_irq_init(void)
 170 {
 171     // disable IRQ's
 172 //    *(volatile unsigned int *)ARMFIQ_CTRL = 0;
 173
 174     *(volatile unsigned int *)ARMIRQ_DIBL = ~0;
 175     *(volatile unsigned int *)GPUIRQ_DIBL0 = ~0;
 176     *(volatile unsigned int *)GPUIRQ_DIBL1 = ~0;
 177 }
 178
 179 static void bcm2708_send_ipi(uint32_t ipi, uint32_t ipi_data, uint32_t cpumask)
 180 {
 181     int cpu, mbno = 0;
 182
 183     for (cpu = 0; cpu < 4; cpu++)
 184     {
 185 #if defined(__AROSEXEC_SMP__)
 186         if ((cpumask & (1 << cpu)) && bcm2708_cpuipid[cpu])
 187         {
 188             /* TODO:  check which mailbox is available and use it */
 189             bcm2708_cpuipid[cpu]->ipi_data[mbno] = ipi_data;
 190             *((uint32_t *)(BCM2836_MAILBOX0_SET0 + 4 * mbno + (0x10 * cpu))) = ipi;
 191         }
 192 #endif
 193     }
 194 }
 195
 196 static void bcm2708_irq_enable(int irq)
 197 {
 198     int bank = IRQ_BANK(irq);
 199     unsigned int reg;
 200
 201     reg = (unsigned int)IRQBANK_POINTER(bank);
 202
 203     DIRQ(bug("[Kernel:BCM2708] Enabling irq %d [bank %d, reg 0x%p]\n", irq, bank, reg));
 204
 205     *((volatile unsigned int *)reg) = IRQ_MASK(irq);
 206
 207     DIRQ(bug("[Kernel:BCM2708] irqmask=%08x\n", *((volatile unsigned int *)reg)));
 208 }
 209
 210 static void bcm2708_irq_disable(int irq)
 211 {
 212     int bank = IRQ_BANK(irq);
 213     unsigned int reg;
 214
 215     reg = (unsigned int)IRQBANK_POINTER(bank) + 0x0c;
 216
 217     DIRQ(bug("[Kernel:BCM2708] Disabling irq %d [bank %d, reg 0x%p]\n", irq, bank, reg));
 218
 219     *((volatile unsigned int *)reg) = IRQ_MASK(irq);
 220
 221     DIRQ(bug("[Kernel:BCM2708] irqmask=%08x\n", *((volatile unsigned int *)reg)));
 222 }
 223
 224 static void bcm2708_irq_process()
 225 {
 226     unsigned int pendingarm, pending0, pending1, irq;
 227
 228     for(;;)
 229     {
 230         pendingarm = *((volatile unsigned int *)(ARMIRQ_PEND));
 231         pending0 = *((volatile unsigned int *)(GPUIRQ_PEND0));
 232         pending1 = *((volatile unsigned int *)(GPUIRQ_PEND1));
 233
 234         if (!(pendingarm || pending0 || pending1))
 235             break;
 236
 237         DIRQ(bug("[Kernel:BCM2708] PendingARM %08x\n", pendingarm));
 238         DIRQ(bug("[Kernel:BCM2708] Pending0 %08x\n", pending0));
 239         DIRQ(bug("[Kernel:BCM2708] Pending1 %08x\n", pending1));
 240
 241         if (pendingarm & ~(IRQ_BANK1 | IRQ_BANK2))
 242         {
 243             for (irq = (2 << 5); irq < ((2 << 5) + 8); irq++)
 244             {
 245                 if (pendingarm & (1 << (irq - (2 << 5))))
 246                 {
 247                     DIRQ(bug("[Kernel:BCM2708] Handling IRQ %d ..\n", irq));
 248                     krnRunIRQHandlers(KernelBase, irq);
 249                 }
 250             }
 251         }
 252
 253         if (pending0)
 254         {
 255             for (irq = (0 << 5); irq < ((0 << 5) + 32); irq++)
 256             {
 257                 if (pending0 & (1 << (irq - (0 << 5))))
 258                 {
 259                     DIRQ(bug("[Kernel:BCM2708] Handling IRQ %d ..\n", irq));
 260                     krnRunIRQHandlers(KernelBase, irq);
 261                 }
 262             }
 263         }
 264
 265         if (pending1)
 266         {
 267             for (irq = (1 << 5); irq < ((1 << 5) + 32); irq++)
 268             {
 269                 if (pending1 & (1 << (irq - (1 << 5))))
 270                 {
 271                     DIRQ(bug("[Kernel:BCM2708] Handling IRQ %d ..\n", irq));
 272                     krnRunIRQHandlers(KernelBase, irq);
 273                 }
 274             }
 275         }
 276     }
 277 }
 278
 279 static void bcm2708_fiq_process()
 280 {
 281     int cpunum = GetCPUNumber();
 282     uint32_t fiq, fiq_data;
 283     int mbno;
 284
 285     DFIQ(bug("[Kernel:BCM2708] %s(%d)\n", __PRETTY_FUNCTION__, cpunum));
 286
 287     fiq = *((uint32_t *)(BCM2836_FIQ_PEND0 + (0x4 * cpunum)));
 288
 289     DFIQ(bug("[Kernel:BCM2708] %s: CPU #%02d FIQ %x\n", __PRETTY_FUNCTION__, cpunum, fiq));
 290
 291     if (fiq)
 292     {
 293         for (mbno=0; mbno < 4; mbno++)
 294         {
 295             if (fiq & (0x10 << mbno))
 296             {
 297                 fiq_data = *((uint32_t *)(BCM2836_MAILBOX0_CLR0 + 4 * mbno + (16 * cpunum)));
 298                 DFIQ(bug("[Kernel:BCM2708] %s: Mailbox%d: FIQ Data %08x\n", __PRETTY_FUNCTION__, mbno, fiq_data));
 299 #if defined(__AROSEXEC_SMP__)
 300                 if (bcm2708_cpuipid[cpunum])
 301                     handle_ipi(fiq_data, bcm2708_cpuipid[cpunum]->ipi_data[0]);
 302 #endif
 303                 *((uint32_t *)(BCM2836_MAILBOX0_CLR0 + 4 * mbno + (16 * cpunum))) = 0xffffffff;
 304             }
 305         }
 306     }
 307 }
 308
 309 static void bcm2708_toggle_led(int LED, int state)
 310 {
 311     if (__arm_arosintern.ARMI_PeripheralBase == (APTR)BCM2836_PERIPHYSBASE)
 312     {
 313         int pin = 35;
 314         APTR gpiofunc = GPCLR1;
 315
 316         if (LED == ARM_LED_ACTIVITY)
 317             pin = 47;
 318
 319         if (state == ARM_LED_ON)
 320             gpiofunc = GPSET1;
 321
 322         *(volatile unsigned int *)gpiofunc = (1 << (pin-32));
 323     }
 324     else
 325     {
 326         // RasPi 1 only allows us to toggle the activity LED
 327         if (state)
 328             *(volatile unsigned int *)GPCLR0 = (1 << 16);
 329         else
 330             *(volatile unsigned int *)GPSET0 = (1 << 16);
 331     }
 332 }
 333
 334 /* Use system timer 3 for our scheduling heartbeat */
 335 #define VBLANK_TIMER            3
 336 #define VBLANK_INTERVAL         (1000000 / 50)
 337
 338 static void bcm2708_gputimer_handler(unsigned int timerno, void *unused1)
 339 {
 340     unsigned int stc;
 341
 342     DTIMER(bug("[Kernel:BCM2708] %s(%d)\n", __PRETTY_FUNCTION__, timerno));
 343
 344     /* Aknowledge our timer interrupt */
 345     *((volatile unsigned int *)(SYSTIMER_CS)) = 1 << timerno;
 346
 347     /* Signal the Exec VBlankServer */
 348     if (SysBase && (IDNESTCOUNT_GET /*SysBase->IDNestCnt*/ < 0)) {
 349         core_Cause(INTB_VERTB, 1L << INTB_VERTB);
 350     }
 351
 352     /* Refresh our timer interrupt */
 353     stc = *((volatile unsigned int *)(SYSTIMER_CLO));
 354     stc += VBLANK_INTERVAL;
 355     *((volatile unsigned int *)(SYSTIMER_C0 + (timerno * 4))) = stc;
 356
 357     DTIMER(bug("[BCM2708] %s: Done..\n", __PRETTY_FUNCTION__));
 358 }
 359
 360 static APTR bcm2708_init_gputimer(APTR _kernelBase)
 361 {
 362     struct KernelBase *KernelBase = (struct KernelBase *)_kernelBase;
 363     struct IntrNode *GPUTimerHandle;
 364     unsigned int stc;
 365
 366     DTIMER(bug("[Kernel:BCM2708] %s(%012p)\n", __PRETTY_FUNCTION__, KernelBase));
 367
 368     if ((GPUTimerHandle = AllocMem(sizeof(struct IntrNode), MEMF_PUBLIC|MEMF_CLEAR)) != NULL)
 369     {
 370         DTIMER(bug("[Kernel:BCM2708] %s: IntrNode @ 0x%p:\n", __PRETTY_FUNCTION__, GPUTimerHandle));
 371         DTIMER(bug("[Kernel:BCM2708] %s: Using GPUTimer %d for VBlank\n", __PRETTY_FUNCTION__, VBLANK_TIMER));
 372
 373         GPUTimerHandle->in_Handler = bcm2708_gputimer_handler;
 374         GPUTimerHandle->in_HandlerData = (void *)VBLANK_TIMER;
 375         GPUTimerHandle->in_HandlerData2 = KernelBase;
 376         GPUTimerHandle->in_type = it_interrupt;
 377         GPUTimerHandle->in_nr = IRQ_TIMER0 + VBLANK_TIMER;
 378
 379         ADDHEAD(&KernelBase->kb_Interrupts[IRQ_TIMER0 + VBLANK_TIMER], &GPUTimerHandle->in_Node);
 380
 381         DTIMER(bug("[Kernel:BCM2708] %s: Enabling Hardware IRQ.. \n", __PRETTY_FUNCTION__));
 382
 383         stc = *((volatile unsigned int *)(SYSTIMER_CLO));
 384         stc += VBLANK_INTERVAL;
 385         *((volatile unsigned int *)(SYSTIMER_CS)) = (1 << VBLANK_TIMER);
 386         *((volatile unsigned int *)(SYSTIMER_C0 + (VBLANK_TIMER * 4))) = stc;
 387
 388         ictl_enable_irq(IRQ_TIMER0 + VBLANK_TIMER, KernelBase);
 389     }
 390
 391     DTIMER(bug("[Kernel:BCM2708] %s: Done.. \n", __PRETTY_FUNCTION__));
 392
 393     return GPUTimerHandle;
 394 }
 395
 396 static inline void bcm2708_ser_waitout()
 397 {
 398     while(1)
 399     {
 400        if ((*(volatile uint32_t *)(PL011_0_BASE + PL011_FR) & PL011_FR_TXFF) == 0) break;
 401     }
 402 }
 403
 404 static void bcm2708_ser_putc(uint8_t chr)
 405 {
 406     bcm2708_ser_waitout();
 407
 408     if (chr == '\n')
 409     {
 410         *(volatile uint32_t *)(PL011_0_BASE + PL011_DR) = '\r';
 411         bcm2708_ser_waitout();
 412     }
 413     *(volatile uint32_t *)(PL011_0_BASE + PL011_DR) = chr;
 414 }
 415
 416 static int bcm2708_ser_getc(void)
 417 {
 418     if ((*(volatile uint32_t *)(PL011_0_BASE + PL011_FR) & PL011_FR_RXFE) == 0)
 419         return (int)*(volatile uint32_t *)(PL011_0_BASE + PL011_DR);
 420
 421     return -1;
 422 }
 423
 424 static IPTR bcm2708_probe(struct ARM_Implementation *krnARMImpl, struct TagItem *msg)
 425 {
 426     void *bootPutC = NULL;
 427
 428     while(msg->ti_Tag != TAG_DONE)
 429     {
 430         switch (msg->ti_Tag)
 431         {
 432         case KRN_FuncPutC:
 433             bootPutC = (void *)msg->ti_Data;
 434             break;
 435         }
 436         msg++;
 437     }
 438
 439     if (krnARMImpl->ARMI_Platform != 0xc42)
 440         return FALSE;
 441
 442     if (krnARMImpl->ARMI_Family == 7)
 443     {
 444         /*  bcm2836 uses armv7 */
 445         krnARMImpl->ARMI_PeripheralBase = (APTR)BCM2836_PERIPHYSBASE;
 446         krnARMImpl->ARMI_InitCore = &bcm2708_init_cpu;
 447         krnARMImpl->ARMI_FIQProcess = &bcm2708_fiq_process;
 448         krnARMImpl->ARMI_SendIPI = &bcm2708_send_ipi;
 449     }
 450     else
 451         krnARMImpl->ARMI_PeripheralBase = (APTR)BCM2835_PERIPHYSBASE;
 452
 453     krnARMImpl->ARMI_GetTime = &bcm2708_get_time;
 454     krnARMImpl->ARMI_InitTimer = &bcm2708_init_gputimer;
 455     krnARMImpl->ARMI_LED_Toggle = &bcm2708_toggle_led;
 456
 457     krnARMImpl->ARMI_SerPutChar = &bcm2708_ser_putc;
 458     krnARMImpl->ARMI_SerGetChar = &bcm2708_ser_getc;
 459     if ((krnARMImpl->ARMI_PutChar = bootPutC) != NULL)
 460             krnARMImpl->ARMI_PutChar(0xFF); // Clear the display
 461
 462     krnARMImpl->ARMI_IRQInit = &bcm2708_irq_init;
 463     krnARMImpl->ARMI_IRQEnable = &bcm2708_irq_enable;
 464     krnARMImpl->ARMI_IRQDisable = &bcm2708_irq_disable;
 465     krnARMImpl->ARMI_IRQProcess = &bcm2708_irq_process;
 466
 467     krnARMImpl->ARMI_Init = &bcm2708_init;
 468
 469     return TRUE;
 470 }
 471
 472 ADD2SET(bcm2708_probe, ARMPLATFORMS, 0);