| blob | af9e83ca681b3b506185df5ace6bbb9116b8c3eb |
1 #
2 # $NetBSD: pfpsp.s,v 1.4 2005/12/11 12:17:52 christos Exp $
3 #
5 #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
6 # MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
7 # M68000 Hi-Performance Microprocessor Division
8 # M68060 Software Package Production Release
9 #
10 # M68060 Software Package Copyright (C) 1993, 1994, 1995, 1996 Motorola Inc.
11 # All rights reserved.
12 #
13 # THE SOFTWARE is provided on an "AS IS" basis and without warranty.
14 # To the maximum extent permitted by applicable law,
15 # MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
16 # INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
17 # FOR A PARTICULAR PURPOSE and any warranty against infringement with
18 # regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
19 # and any accompanying written materials.
20 #
21 # To the maximum extent permitted by applicable law,
22 # IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
23 # (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
24 # BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
25 # ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
26 #
27 # Motorola assumes no responsibility for the maintenance and support
28 # of the SOFTWARE.
29 #
30 # You are hereby granted a copyright license to use, modify, and distribute the
31 # SOFTWARE so long as this entire notice is retained without alteration
32 # in any modified and/or redistributed versions, and that such modified
33 # versions are clearly identified as such.
34 # No licenses are granted by implication, estoppel or otherwise under any
35 # patents or trademarks of Motorola, Inc.
36 #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
38 #
39 # freal.s:
40 # This file is appended to the top of the 060FPSP package
41 # and contains the entry points into the package. The user, in
42 # effect, branches to one of the branch table entries located
43 # after _060FPSP_TABLE.
44 # Also, subroutine stubs exist in this file (_fpsp_done for
45 # example) that are referenced by the FPSP package itself in order
46 # to call a given routine. The stub routine actually performs the
47 # callout. The FPSP code does a "bsr" to the stub routine. This
48 # extra layer of hierarchy adds a slight performance penalty but
49 # it makes the FPSP code easier to read and more mainatinable.
50 #
78 _060FPSP_TABLE:
80 ###############################################################
82 # Here's the table of ENTRY POINTS for those linking the package.
83 bra.l _fpsp_snan
84 short 0x0000
85 bra.l _fpsp_operr
86 short 0x0000
87 bra.l _fpsp_ovfl
88 short 0x0000
89 bra.l _fpsp_unfl
90 short 0x0000
91 bra.l _fpsp_dz
92 short 0x0000
93 bra.l _fpsp_inex
94 short 0x0000
95 bra.l _fpsp_fline
96 short 0x0000
97 bra.l _fpsp_unsupp
98 short 0x0000
99 bra.l _fpsp_effadd
100 short 0x0000
102 space 56
104 ###############################################################
105 global _fpsp_done
106 _fpsp_done:
113 global _real_ovfl
114 _real_ovfl:
121 global _real_unfl
122 _real_unfl:
129 global _real_inex
130 _real_inex:
137 global _real_bsun
138 _real_bsun:
145 global _real_operr
146 _real_operr:
153 global _real_snan
154 _real_snan:
161 global _real_dz
162 _real_dz:
169 global _real_fline
170 _real_fline:
177 global _real_fpu_disabled
178 _real_fpu_disabled:
185 global _real_trap
186 _real_trap:
193 global _real_trace
194 _real_trace:
201 global _real_access
202 _real_access:
209 #######################################
211 global _imem_read
212 _imem_read:
219 global _dmem_read
220 _dmem_read:
227 global _dmem_write
228 _dmem_write:
235 global _imem_read_word
236 _imem_read_word:
243 global _imem_read_long
244 _imem_read_long:
251 global _dmem_read_byte
252 _dmem_read_byte:
259 global _dmem_read_word
260 _dmem_read_word:
267 global _dmem_read_long
268 _dmem_read_long:
275 global _dmem_write_byte
276 _dmem_write_byte:
283 global _dmem_write_word
284 _dmem_write_word:
291 global _dmem_write_long
292 _dmem_write_long:
299 #
300 # This file contains a set of define statements for constants
301 # in order to promote readability within the corecode itself.
302 #
396 ################################
398 # Helpful macros
443 ##################
444 # FPSR/FPCR bits #
445 ##################
468 #############################
469 # FPSR individual bit masks #
470 #############################
496 ######################################
497 # FPSR combinations used in the FPSP #
498 ######################################
499 set dzinf_mask, inf_mask+dz_mask+adz_mask
500 set opnan_mask, nan_mask+operr_mask+aiop_mask
502 set unfinx_mask, unfl_mask+inex2_mask+aunfl_mask+ainex_mask
503 set unf2inx_mask, unfl_mask+inex2_mask+ainex_mask
504 set ovfinx_mask, ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
505 set inx1a_mask, inex1_mask+ainex_mask
506 set inx2a_mask, inex2_mask+ainex_mask
507 set snaniop_mask, nan_mask+snan_mask+aiop_mask
508 set snaniop2_mask, snan_mask+aiop_mask
509 set naniop_mask, nan_mask+aiop_mask
510 set neginf_mask, neg_mask+inf_mask
511 set infaiop_mask, inf_mask+aiop_mask
512 set negz_mask, neg_mask+z_mask
513 set opaop_mask, operr_mask+aiop_mask
514 set unfl_inx_mask, unfl_mask+aunfl_mask+ainex_mask
515 set ovfl_inx_mask, ovfl_mask+aovfl_mask+ainex_mask
517 #########
518 # misc. #
519 #########
551 ###########################
552 # SPecial CONDition FLaGs #
553 ###########################
567 ##################################
568 # TRANSCENDENTAL "LAST-OP" FLAGS #
569 ##################################
575 #############
576 # CONSTANTS #
577 #############
584 TWOBYPI:
587 #########################################################################
588 # XDEF **************************************************************** #
589 # _fpsp_ovfl(): 060FPSP entry point for FP Overflow exception. #
590 # #
591 # This handler should be the first code executed upon taking the #
592 # FP Overflow exception in an operating system. #
593 # #
594 # XREF **************************************************************** #
595 # _imem_read_long() - read instruction longword #
596 # fix_skewed_ops() - adjust src operand in fsave frame #
597 # set_tag_x() - determine optype of src/dst operands #
598 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
599 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
600 # load_fpn2() - load dst operand from FP regfile #
601 # fout() - emulate an opclass 3 instruction #
602 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
603 # _fpsp_done() - "callout" for 060FPSP exit (all work done!) #
604 # _real_ovfl() - "callout" for Overflow exception enabled code #
605 # _real_inex() - "callout" for Inexact exception enabled code #
606 # _real_trace() - "callout" for Trace exception code #
607 # #
608 # INPUT *************************************************************** #
609 # - The system stack contains the FP Ovfl exception stack frame #
610 # - The fsave frame contains the source operand #
611 # #
612 # OUTPUT ************************************************************** #
613 # Overflow Exception enabled: #
614 # - The system stack is unchanged #
615 # - The fsave frame contains the adjusted src op for opclass 0,2 #
616 # Overflow Exception disabled: #
617 # - The system stack is unchanged #
618 # - The "exception present" flag in the fsave frame is cleared #
619 # #
620 # ALGORITHM *********************************************************** #
621 # On the 060, if an FP overflow is present as the result of any #
622 # instruction, the 060 will take an overflow exception whether the #
623 # exception is enabled or disabled in the FPCR. For the disabled case, #
624 # This handler emulates the instruction to determine what the correct #
625 # default result should be for the operation. This default result is #
626 # then stored in either the FP regfile, data regfile, or memory. #
627 # Finally, the handler exits through the "callout" _fpsp_done() #
628 # denoting that no exceptional conditions exist within the machine. #
629 # If the exception is enabled, then this handler must create the #
630 # exceptional operand and plave it in the fsave state frame, and store #
631 # the default result (only if the instruction is opclass 3). For #
632 # exceptions enabled, this handler must exit through the "callout" #
633 # _real_ovfl() so that the operating system enabled overflow handler #
634 # can handle this case. #
635 # Two other conditions exist. First, if overflow was disabled #
636 # but the inexact exception was enabled, this handler must exit #
637 # through the "callout" _real_inex() regardless of whether the result #
638 # was inexact. #
639 # Also, in the case of an opclass three instruction where #
640 # overflow was disabled and the trace exception was enabled, this #
641 # handler must exit through the "callout" _real_trace(). #
642 # #
643 #########################################################################
645 global _fpsp_ovfl
646 _fpsp_ovfl:
648 #$# sub.l &24,%sp # make room for src/dst
658 # the FPIAR holds the "current PC" of the faulting instruction
665 ##############################################################################
668 bne.w fovfl_out
674 # since, I believe, only NORMs and DENORMs can come through here,
675 # maybe we can avoid the subroutine call.
680 # bit five of the fp extension word separates the monadic and dyadic operations
681 # that can pass through fpsp_ovfl(). remember that fcmp, ftst, and fsincos
682 # will never take this exception.
694 fovfl_op2_done:
697 fovfl_extract:
699 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
700 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
701 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
702 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6)
703 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6)
704 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6)
720 # maybe we can make these entry points ONLY the OVFL entry points of each routine.
724 # the operation has been emulated. the result is in fp0.
725 # the EXOP, if an exception occurred, is in fp1.
726 # we must save the default result regardless of whether
727 # traps are enabled or disabled.
729 bsr.l store_fpreg
731 # the exceptional possibilities we have left ourselves with are ONLY overflow
732 # and inexact. and, the inexact is such that overflow occurred and was disabled
733 # but inexact was enabled.
735 bne.b fovfl_ovfl_on
738 bne.b fovfl_inex_on
744 unlk %a6
745 #$# add.l &24,%sp
746 bra.l _fpsp_done
748 # overflow is enabled AND overflow, of course, occurred. so, we have the EXOP
749 # in fp1. now, simply jump to _real_ovfl()!
750 fovfl_ovfl_on:
761 unlk %a6
763 bra.l _real_ovfl
765 # overflow occurred but is disabled. meanwhile, inexact is enabled. therefore,
766 # we must jump to real_inex().
767 fovfl_inex_on:
780 unlk %a6
782 bra.l _real_inex
784 ########################################################################
785 fovfl_out:
788 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
789 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
790 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
792 # the src operand is definitely a NORM(!), so tag it as such
805 bsr.l fout
808 bne.w fovfl_ovfl_on
811 bne.w fovfl_inex_on
817 unlk %a6
818 #$# add.l &24,%sp
825 bra.l _real_trace
827 #########################################################################
828 # XDEF **************************************************************** #
829 # _fpsp_unfl(): 060FPSP entry point for FP Underflow exception. #
830 # #
831 # This handler should be the first code executed upon taking the #
832 # FP Underflow exception in an operating system. #
833 # #
834 # XREF **************************************************************** #
835 # _imem_read_long() - read instruction longword #
836 # fix_skewed_ops() - adjust src operand in fsave frame #
837 # set_tag_x() - determine optype of src/dst operands #
838 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
839 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
840 # load_fpn2() - load dst operand from FP regfile #
841 # fout() - emulate an opclass 3 instruction #
842 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
843 # _fpsp_done() - "callout" for 060FPSP exit (all work done!) #
844 # _real_ovfl() - "callout" for Overflow exception enabled code #
845 # _real_inex() - "callout" for Inexact exception enabled code #
846 # _real_trace() - "callout" for Trace exception code #
847 # #
848 # INPUT *************************************************************** #
849 # - The system stack contains the FP Unfl exception stack frame #
850 # - The fsave frame contains the source operand #
851 # #
852 # OUTPUT ************************************************************** #
853 # Underflow Exception enabled: #
854 # - The system stack is unchanged #
855 # - The fsave frame contains the adjusted src op for opclass 0,2 #
856 # Underflow Exception disabled: #
857 # - The system stack is unchanged #
858 # - The "exception present" flag in the fsave frame is cleared #
859 # #
860 # ALGORITHM *********************************************************** #
861 # On the 060, if an FP underflow is present as the result of any #
862 # instruction, the 060 will take an underflow exception whether the #
863 # exception is enabled or disabled in the FPCR. For the disabled case, #
864 # This handler emulates the instruction to determine what the correct #
865 # default result should be for the operation. This default result is #
866 # then stored in either the FP regfile, data regfile, or memory. #
867 # Finally, the handler exits through the "callout" _fpsp_done() #
868 # denoting that no exceptional conditions exist within the machine. #
869 # If the exception is enabled, then this handler must create the #
870 # exceptional operand and plave it in the fsave state frame, and store #
871 # the default result (only if the instruction is opclass 3). For #
872 # exceptions enabled, this handler must exit through the "callout" #
873 # _real_unfl() so that the operating system enabled overflow handler #
874 # can handle this case. #
875 # Two other conditions exist. First, if underflow was disabled #
876 # but the inexact exception was enabled and the result was inexact, #
877 # this handler must exit through the "callout" _real_inex(). #
878 # was inexact. #
879 # Also, in the case of an opclass three instruction where #
880 # underflow was disabled and the trace exception was enabled, this #
881 # handler must exit through the "callout" _real_trace(). #
882 # #
883 #########################################################################
885 global _fpsp_unfl
886 _fpsp_unfl:
888 #$# sub.l &24,%sp # make room for src/dst
898 # the FPIAR holds the "current PC" of the faulting instruction
905 ##############################################################################
908 bne.w funfl_out
918 # bit five of the fp ext word separates the monadic and dyadic operations
919 # that can pass through fpsp_unfl(). remember that fcmp, and ftst
920 # will never take this exception.
924 # now, what's left that's not dyadic is fsincos. we can distinguish it
925 # from all dyadics by the '0110xxx pattern
937 funfl_op2_done:
940 funfl_extract:
942 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
943 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
944 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
945 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6)
946 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6)
947 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6)
963 # maybe we can make these entry points ONLY the OVFL entry points of each routine.
968 bsr.l store_fpreg
970 # The `060 FPU multiplier hardware is such that if the result of a
971 # multiply operation is the smallest possible normalized number
972 # (0x00000000_80000000_00000000), then the machine will take an
973 # underflow exception. Since this is incorrect, we need to check
974 # if our emulation, after re-doing the operation, decided that
975 # no underflow was called for. We do these checks only in
976 # funfl_{unfl,inex}_on() because w/ both exceptions disabled, this
977 # special case will simply exit gracefully with the correct result.
979 # the exceptional possibilities we have left ourselves with are ONLY overflow
980 # and inexact. and, the inexact is such that overflow occurred and was disabled
981 # but inexact was enabled.
983 bne.b funfl_unfl_on
985 funfl_chkinex:
987 bne.b funfl_inex_on
989 funfl_exit:
994 unlk %a6
995 #$# add.l &24,%sp
996 bra.l _fpsp_done
998 # overflow is enabled AND overflow, of course, occurred. so, we have the EXOP
999 # in fp1 (don't forget to save fp0). what to do now?
1000 # well, we simply have to get to go to _real_unfl()!
1001 funfl_unfl_on:
1003 # The `060 FPU multiplier hardware is such that if the result of a
1004 # multiply operation is the smallest possible normalized number
1005 # (0x00000000_80000000_00000000), then the machine will take an
1006 # underflow exception. Since this is incorrect, we check here to see
1007 # if our emulation, after re-doing the operation, decided that
1008 # no underflow was called for.
1010 beq.w funfl_chkinex
1012 funfl_unfl_on2:
1023 unlk %a6
1025 bra.l _real_unfl
1027 # undeflow occurred but is disabled. meanwhile, inexact is enabled. therefore,
1028 # we must jump to real_inex().
1029 funfl_inex_on:
1031 # The `060 FPU multiplier hardware is such that if the result of a
1032 # multiply operation is the smallest possible normalized number
1033 # (0x00000000_80000000_00000000), then the machine will take an
1034 # underflow exception.
1035 # But, whether bogus or not, if inexact is enabled AND it occurred,
1036 # then we have to branch to real_inex.
1039 beq.w funfl_exit
1041 funfl_inex_on2:
1054 unlk %a6
1056 bra.l _real_inex
1058 #######################################################################
1059 funfl_out:
1062 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
1063 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
1064 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
1066 # the src operand is definitely a NORM(!), so tag it as such
1079 bsr.l fout
1082 bne.w funfl_unfl_on2
1085 bne.w funfl_inex_on2
1091 unlk %a6
1092 #$# add.l &24,%sp
1099 bra.l _real_trace
1101 #########################################################################
1102 # XDEF **************************************************************** #
1103 # _fpsp_unsupp(): 060FPSP entry point for FP "Unimplemented #
1104 # Data Type" exception. #
1105 # #
1106 # This handler should be the first code executed upon taking the #
1107 # FP Unimplemented Data Type exception in an operating system. #
1108 # #
1109 # XREF **************************************************************** #
1110 # _imem_read_{word,long}() - read instruction word/longword #
1111 # fix_skewed_ops() - adjust src operand in fsave frame #
1112 # set_tag_x() - determine optype of src/dst operands #
1113 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
1114 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
1115 # load_fpn2() - load dst operand from FP regfile #
1116 # load_fpn1() - load src operand from FP regfile #
1117 # fout() - emulate an opclass 3 instruction #
1118 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
1119 # _real_inex() - "callout" to operating system inexact handler #
1120 # _fpsp_done() - "callout" for exit; work all done #
1121 # _real_trace() - "callout" for Trace enabled exception #
1122 # funimp_skew() - adjust fsave src ops to "incorrect" value #
1123 # _real_snan() - "callout" for SNAN exception #
1124 # _real_operr() - "callout" for OPERR exception #
1125 # _real_ovfl() - "callout" for OVFL exception #
1126 # _real_unfl() - "callout" for UNFL exception #
1127 # get_packed() - fetch packed operand from memory #
1128 # #
1129 # INPUT *************************************************************** #
1130 # - The system stack contains the "Unimp Data Type" stk frame #
1131 # - The fsave frame contains the ssrc op (for UNNORM/DENORM) #
1132 # #
1133 # OUTPUT ************************************************************** #
1134 # If Inexact exception (opclass 3): #
1135 # - The system stack is changed to an Inexact exception stk frame #
1136 # If SNAN exception (opclass 3): #
1137 # - The system stack is changed to an SNAN exception stk frame #
1138 # If OPERR exception (opclass 3): #
1139 # - The system stack is changed to an OPERR exception stk frame #
1140 # If OVFL exception (opclass 3): #
1141 # - The system stack is changed to an OVFL exception stk frame #
1142 # If UNFL exception (opclass 3): #
1143 # - The system stack is changed to an UNFL exception stack frame #
1144 # If Trace exception enabled: #
1145 # - The system stack is changed to a Trace exception stack frame #
1146 # Else: (normal case) #
1147 # - Correct result has been stored as appropriate #
1148 # #
1149 # ALGORITHM *********************************************************** #
1150 # Two main instruction types can enter here: (1) DENORM or UNNORM #
1151 # unimplemented data types. These can be either opclass 0,2 or 3 #
1152 # instructions, and (2) PACKED unimplemented data format instructions #
1153 # also of opclasses 0,2, or 3. #
1154 # For UNNORM/DENORM opclass 0 and 2, the handler fetches the src #
1155 # operand from the fsave state frame and the dst operand (if dyadic) #
1156 # from the FP register file. The instruction is then emulated by #
1157 # choosing an emulation routine from a table of routines indexed by #
1158 # instruction type. Once the instruction has been emulated and result #
1159 # saved, then we check to see if any enabled exceptions resulted from #
1160 # instruction emulation. If none, then we exit through the "callout" #
1161 # _fpsp_done(). If there is an enabled FP exception, then we insert #
1162 # this exception into the FPU in the fsave state frame and then exit #
1163 # through _fpsp_done(). #
1164 # PACKED opclass 0 and 2 is similar in how the instruction is #
1165 # emulated and exceptions handled. The differences occur in how the #
1166 # handler loads the packed op (by calling get_packed() routine) and #
1167 # by the fact that a Trace exception could be pending for PACKED ops. #
1168 # If a Trace exception is pending, then the current exception stack #
1169 # frame is changed to a Trace exception stack frame and an exit is #
1170 # made through _real_trace(). #
1171 # For UNNORM/DENORM opclass 3, the actual move out to memory is #
1172 # performed by calling the routine fout(). If no exception should occur #
1173 # as the result of emulation, then an exit either occurs through #
1174 # _fpsp_done() or through _real_trace() if a Trace exception is pending #
1175 # (a Trace stack frame must be created here, too). If an FP exception #
1176 # should occur, then we must create an exception stack frame of that #
1177 # type and jump to either _real_snan(), _real_operr(), _real_inex(), #
1178 # _real_unfl(), or _real_ovfl() as appropriate. PACKED opclass 3 #
1179 # emulation is performed in a similar manner. #
1180 # #
1181 #########################################################################
1183 #
1184 # (1) DENORM and UNNORM (unimplemented) data types:
1185 #
1186 # post-instruction
1187 # *****************
1188 # * EA *
1189 # pre-instruction * *
1190 # ***************** *****************
1191 # * 0x0 * 0x0dc * * 0x3 * 0x0dc *
1192 # ***************** *****************
1193 # * Next * * Next *
1194 # * PC * * PC *
1195 # ***************** *****************
1196 # * SR * * SR *
1197 # ***************** *****************
1198 #
1199 # (2) PACKED format (unsupported) opclasses two and three:
1200 # *****************
1201 # * EA *
1202 # * *
1203 # *****************
1204 # * 0x2 * 0x0dc *
1205 # *****************
1206 # * Next *
1207 # * PC *
1208 # *****************
1209 # * SR *
1210 # *****************
1211 #
1212 global _fpsp_unsupp
1213 _fpsp_unsupp:
1224 bne.b fu_s
1225 fu_u:
1228 bra.b fu_cont
1229 # if the exception is an opclass zero or two unimplemented data type
1230 # exception, then the a7' calculated here is wrong since it doesn't
1231 # stack an ea. however, we don't need an a7' for this case anyways.
1232 fu_s:
1236 fu_cont:
1238 # the FPIAR holds the "current PC" of the faulting instruction
1239 # the FPIAR should be set correctly for ALL exceptions passing through
1240 # this point.
1247 ############################
1251 # Separate opclass three (fpn-to-mem) ops since they have a different
1252 # stack frame and protocol.
1254 bne.w fu_out # yes
1256 # Separate packed opclass two instructions.
1259 beq.w fu_in_pack
1262 # I'm not sure at this point what FPSR bits are valid for this instruction.
1263 # so, since the emulation routines re-create them anyways, zero exception field
1269 # Opclass two w/ memory-to-fpn operation will have an incorrect extended
1270 # precision format if the src format was single or double and the
1271 # source data type was an INF, NAN, DENORM, or UNNORM
1273 bsr.l fix_skewed_ops
1275 # we don't know whether the src operand or the dst operand (or both) is the
1276 # UNNORM or DENORM. call the function that tags the operand type. if the
1277 # input is an UNNORM, then convert it to a NORM, DENORM, or ZERO.
1284 fu_op2:
1289 # bit five of the fp extension word separates the monadic and dyadic operations
1290 # at this point
1303 fu_op2_done:
1306 fu_extract:
1318 #
1319 # Exceptions in order of precedence:
1320 # BSUN : none
1321 # SNAN : all dyadic ops
1322 # OPERR : fsqrt(-NORM)
1323 # OVFL : all except ftst,fcmp
1324 # UNFL : all except ftst,fcmp
1325 # DZ : fdiv
1326 # INEX2 : all except ftst,fcmp
1327 # INEX1 : none (packed doesn't go through here)
1328 #
1330 # we determine the highest priority exception(if any) set by the
1331 # emulation routine that has also been enabled by the user.
1335 fu_in_cont:
1336 # fcmp and ftst do not store any result.
1345 fu_in_exit:
1351 unlk %a6
1353 bra.l _fpsp_done
1355 fu_in_ena:
1360 #
1361 # No exceptions occurred that were also enabled. Now:
1362 #
1363 # if (OVFL && ovfl_disabled && inexact_enabled) {
1364 # branch to _real_inex() (even if the result was exact!);
1365 # } else {
1366 # save the result in the proper fp reg (unless the op is fcmp or ftst);
1367 # return;
1368 # }
1369 #
1373 fu_in_ovflchk:
1376 bra.w fu_in_exc_ovfl # go insert overflow frame
1378 #
1379 # An exception occurred and that exception was enabled:
1380 #
1381 # shift enabled exception field into lo byte of d0;
1382 # if (((INEX2 || INEX1) && inex_enabled && OVFL && ovfl_disabled) ||
1383 # ((INEX2 || INEX1) && inex_enabled && UNFL && unfl_disabled)) {
1384 # /*
1385 # * this is the case where we must call _real_inex() now or else
1386 # * there will be no other way to pass it the exceptional operand
1387 # */
1388 # call _real_inex();
1389 # } else {
1390 # restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU;
1391 # }
1392 #
1393 fu_in_exc:
1398 # the enabled exception was inexact
1400 bne.w fu_in_exc_unfl # yes
1402 bne.w fu_in_exc_ovfl # yes
1404 # here, we insert the correct fsave status value into the fsave frame for the
1405 # corresponding exception. the operand in the fsave frame should be the original
1406 # src operand.
1407 fu_in_exc_exit:
1420 unlk %a6
1422 bra.l _fpsp_done
1424 tbl_except:
1428 fu_in_exc_unfl:
1430 bra.b fu_in_exc_exit
1431 fu_in_exc_ovfl:
1433 bra.b fu_in_exc_exit
1435 # If the input operand to this operation was opclass two and a single
1436 # or double precision denorm, inf, or nan, the operand needs to be
1437 # "corrected" in order to have the proper equivalent extended precision
1438 # number.
1439 global fix_skewed_ops
1440 fix_skewed_ops:
1446 rts # no
1448 fso_sgl:
1455 rts # no
1457 fso_sgl_dnrm_zero:
1460 fso_sgl_dnrm:
1461 # here, we count on norm not to alter a0...
1467 rts
1469 fso_zero:
1471 rts
1473 fso_infnan:
1476 rts
1478 fso_dbl:
1485 rts # no
1487 fso_dbl_dnrm_zero:
1492 fso_dbl_dnrm:
1493 # here, we count on norm not to alter a0...
1499 rts
1501 #################################################################
1503 # fmove out took an unimplemented data type exception.
1504 # the src operand is in FP_SRC. Call _fout() to write out the result and
1505 # to determine which exceptions, if any, to take.
1506 fu_out:
1508 # Separate packed move outs from the UNNORM and DENORM move outs.
1511 beq.w fu_out_pack
1513 beq.w fu_out_pack
1516 # I'm not sure at this point what FPSR bits are valid for this instruction.
1517 # so, since the emulation routines re-create them anyways, zero exception field.
1518 # fmove out doesn't affect ccodes.
1524 # the src can ONLY be a DENORM or an UNNORM! so, don't make any big subroutine
1525 # call here. just figure out what it is...
1535 bra.b fu_out_cont
1536 fu_out_denorm:
1538 fu_out_cont:
1548 # Exceptions in order of precedence:
1549 # BSUN : none
1550 # SNAN : none
1551 # OPERR : fmove.{b,w,l} out of large UNNORM
1552 # OVFL : fmove.{s,d}
1553 # UNFL : fmove.{s,d,x}
1554 # DZ : none
1555 # INEX2 : all
1556 # INEX1 : none (packed doesn't travel through here)
1558 # determine the highest priority exception(if any) set by the
1559 # emulation routine that has also been enabled by the user.
1561 bne.w fu_out_ena # some are enabled
1563 fu_out_done:
1567 # on extended precision opclass three instructions using pre-decrement or
1568 # post-increment addressing mode, the address register is not updated. is the
1569 # address register was the stack pointer used from user mode, then let's update
1570 # it here. if it was used from supervisor mode, then we have to handle this
1571 # as a special case.
1573 bne.b fu_out_done_s
1578 fu_out_done_cont:
1583 unlk %a6
1588 bra.l _fpsp_done
1590 # is the ea mode pre-decrement of the stack pointer from supervisor mode?
1591 # ("fmov.x fpm,-(a7)") if so,
1592 fu_out_done_s:
1594 bne.b fu_out_done_cont
1596 # the extended precision result is still in fp0. but, we need to save it
1597 # somewhere on the stack until we can copy it to its final resting place.
1598 # here, we're counting on the top of the stack to be the old place-holders
1599 # for fp0/fp1 which have already been restored. that way, we can write
1600 # over those destinations with the shifted stack frame.
1612 # now, copy the result to the proper place on the stack
1620 bne.b fu_out_trace
1622 bra.l _fpsp_done
1624 fu_out_ena:
1629 # no exceptions were set.
1630 # if a disabled overflow occurred and inexact was enabled but the result
1631 # was exact, then a branch to _real_inex() is made.
1633 beq.w fu_out_done # no
1635 fu_out_ovflchk:
1637 beq.w fu_out_done # no
1638 bra.w fu_inex # yes
1640 #
1641 # The fp move out that took the "Unimplemented Data Type" exception was
1642 # being traced. Since the stack frames are similar, get the "current" PC
1643 # from FPIAR and put it in the trace stack frame then jump to _real_trace().
1644 #
1645 # UNSUPP FRAME TRACE FRAME
1646 # ***************** *****************
1647 # * EA * * Current *
1648 # * * * PC *
1649 # ***************** *****************
1650 # * 0x3 * 0x0dc * * 0x2 * 0x024 *
1651 # ***************** *****************
1652 # * Next * * Next *
1653 # * PC * * PC *
1654 # ***************** *****************
1655 # * SR * * SR *
1656 # ***************** *****************
1657 #
1658 fu_out_trace:
1661 bra.l _real_trace
1663 # an exception occurred and that exception was enabled.
1664 fu_out_exc:
1667 # we don't mess with the existing fsave frame. just re-insert it and
1668 # jump to the "_real_{}()" handler...
1673 tbl_fu_out:
1683 # for snan,operr,ovfl,unfl, src op is still in FP_SRC so just
1684 # frestore it.
1685 fu_snan:
1695 unlk %a6
1698 bra.l _real_snan
1700 fu_operr:
1710 unlk %a6
1713 bra.l _real_operr
1715 fu_ovfl:
1727 unlk %a6
1729 bra.l _real_ovfl
1731 # underflow can happen for extended precision. extended precision opclass
1732 # three instruction exceptions don't update the stack pointer. so, if the
1733 # exception occurred from user mode, then simply update a7 and exit normally.
1734 # if the exception occurred from supervisor mode, check if
1735 fu_unfl:
1739 bne.w fu_unfl_s
1744 fu_unfl_cont:
1756 unlk %a6
1758 bra.l _real_unfl
1760 fu_unfl_s:
1762 bne.b fu_unfl_cont
1764 # the extended precision result is still in fp0. but, we need to save it
1765 # somewhere on the stack until we can copy it to its final resting place
1766 # (where the exc frame is currently). make sure it's not at the top of the
1767 # frame or it will get overwritten when the exc stack frame is shifted "down".
1786 # now, copy the result to the proper place on the stack
1793 bra.l _real_unfl
1795 # fmove in and out enter here.
1796 fu_inex:
1808 unlk %a6
1811 bra.l _real_inex
1813 #########################################################################
1814 #########################################################################
1815 fu_in_pack:
1818 # I'm not sure at this point what FPSR bits are valid for this instruction.
1819 # so, since the emulation routines re-create them anyways, zero exception field
1834 # bit five of the fp extension word separates the monadic and dyadic operations
1835 # at this point
1848 fu_op2_done_p:
1851 fu_extract_p:
1863 #
1864 # Exceptions in order of precedence:
1865 # BSUN : none
1866 # SNAN : all dyadic ops
1867 # OPERR : fsqrt(-NORM)
1868 # OVFL : all except ftst,fcmp
1869 # UNFL : all except ftst,fcmp
1870 # DZ : fdiv
1871 # INEX2 : all except ftst,fcmp
1872 # INEX1 : all
1873 #
1875 # we determine the highest priority exception(if any) set by the
1876 # emulation routine that has also been enabled by the user.
1878 bne.w fu_in_ena_p # some are enabled
1880 fu_in_cont_p:
1881 # fcmp and ftst do not store any result.
1890 fu_in_exit_p:
1893 bne.w fu_in_exit_s_p # supervisor
1898 fu_in_exit_cont_p:
1906 bne.w fu_trace_p # yes
1910 # the exception occurred in supervisor mode. check to see if the
1911 # addressing mode was (a7)+. if so, we'll need to shift the
1912 # stack frame "up".
1913 fu_in_exit_s_p:
1923 # shift the stack frame "up". we don't really care about the <ea> field.
1929 bne.w fu_trace_p # yes
1933 fu_in_ena_p:
1938 #
1939 # No exceptions occurred that were also enabled. Now:
1940 #
1941 # if (OVFL && ovfl_disabled && inexact_enabled) {
1942 # branch to _real_inex() (even if the result was exact!);
1943 # } else {
1944 # save the result in the proper fp reg (unless the op is fcmp or ftst);
1945 # return;
1946 # }
1947 #
1949 beq.w fu_in_cont_p # no
1951 fu_in_ovflchk_p:
1953 beq.w fu_in_cont_p # no
1954 bra.w fu_in_exc_ovfl_p # do _real_inex() now
1956 #
1957 # An exception occurred and that exception was enabled:
1958 #
1959 # shift enabled exception field into lo byte of d0;
1960 # if (((INEX2 || INEX1) && inex_enabled && OVFL && ovfl_disabled) ||
1961 # ((INEX2 || INEX1) && inex_enabled && UNFL && unfl_disabled)) {
1962 # /*
1963 # * this is the case where we must call _real_inex() now or else
1964 # * there will be no other way to pass it the exceptional operand
1965 # */
1966 # call _real_inex();
1967 # } else {
1968 # restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU;
1969 # }
1970 #
1971 fu_in_exc_p:
1976 # the enabled exception was inexact
1978 bne.w fu_in_exc_unfl_p # yes
1980 bne.w fu_in_exc_ovfl_p # yes
1982 # here, we insert the correct fsave status value into the fsave frame for the
1983 # corresponding exception. the operand in the fsave frame should be the original
1984 # src operand.
1985 # as a reminder for future predicted pain and agony, we are passing in fsave the
1986 # "non-skewed" operand for cases of sgl and dbl src INFs,NANs, and DENORMs.
1987 # this is INCORRECT for enabled SNAN which would give to the user the skewed SNAN!!!
1988 fu_in_exc_exit_p:
1990 bne.w fu_in_exc_exit_s_p # supervisor
1995 fu_in_exc_exit_cont_p:
2004 unlk %a6
2007 bne.w fu_trace_p # yes
2009 bra.l _fpsp_done
2011 tbl_except_p:
2015 fu_in_exc_ovfl_p:
2017 bra.w fu_in_exc_exit_p
2019 fu_in_exc_unfl_p:
2021 bra.w fu_in_exc_exit_p
2023 fu_in_exc_exit_s_p:
2025 beq.b fu_in_exc_exit_cont_p
2037 # shift stack frame "up". who cares about <ea> field.
2047 #
2048 # The opclass two PACKED instruction that took an "Unimplemented Data Type"
2049 # exception was being traced. Make the "current" PC the FPIAR and put it in the
2050 # trace stack frame then jump to _real_trace().
2051 #
2052 # UNSUPP FRAME TRACE FRAME
2053 # ***************** *****************
2054 # * EA * * Current *
2055 # * * * PC *
2056 # ***************** *****************
2057 # * 0x2 * 0x0dc * * 0x2 * 0x024 *
2058 # ***************** *****************
2059 # * Next * * Next *
2060 # * PC * * PC *
2061 # ***************** *****************
2062 # * SR * * SR *
2063 # ***************** *****************
2064 fu_trace_p:
2068 bra.l _real_trace
2070 #########################################################
2071 #########################################################
2072 fu_out_pack:
2075 # I'm not sure at this point what FPSR bits are valid for this instruction.
2076 # so, since the emulation routines re-create them anyways, zero exception field.
2077 # fmove out doesn't affect ccodes.
2084 bsr.l load_fpn1
2086 # unlike other opclass 3, unimplemented data type exceptions, packed must be
2087 # able to detect all operand types.
2094 fu_op2_p:
2105 # Exceptions in order of precedence:
2106 # BSUN : no
2107 # SNAN : yes
2108 # OPERR : if ((k_factor > +17) || (dec. exp exceeds 3 digits))
2109 # OVFL : no
2110 # UNFL : no
2111 # DZ : no
2112 # INEX2 : yes
2113 # INEX1 : no
2115 # determine the highest priority exception(if any) set by the
2116 # emulation routine that has also been enabled by the user.
2118 bne.w fu_out_ena_p # some are enabled
2120 fu_out_exit_p:
2129 fu_out_exit_cont_p:
2137 bne.w fu_trace_p # yes
2141 # the exception occurred in supervisor mode. check to see if the
2142 # addressing mode was -(a7). if so, we'll need to shift the
2143 # stack frame "down".
2144 fu_out_exit_s_p:
2157 # now, copy the result to the proper place on the stack
2165 bne.w fu_trace_p
2167 bra.l _fpsp_done
2169 fu_out_ena_p:
2172 beq.w fu_out_exit_p
2176 # an exception occurred and that exception was enabled.
2177 # the only exception possible on packed move out are INEX, OPERR, and SNAN.
2178 fu_out_exc_p:
2180 bgt.w fu_inex_p2
2181 beq.w fu_operr_p
2183 fu_snan_p:
2185 bne.b fu_snan_s_p
2189 bra.w fu_snan
2191 fu_snan_s_p:
2193 bne.w fu_snan
2195 # the instruction was "fmove.p fpn,-(a7)" from supervisor mode.
2196 # the strategy is to move the exception frame "down" 12 bytes. then, we
2197 # can store the default result where the exception frame was.
2213 # now, we copy the default result to it's proper location
2221 bra.l _real_snan
2223 fu_operr_p:
2225 bne.w fu_operr_p_s
2229 bra.w fu_operr
2231 fu_operr_p_s:
2233 bne.w fu_operr
2235 # the instruction was "fmove.p fpn,-(a7)" from supervisor mode.
2236 # the strategy is to move the exception frame "down" 12 bytes. then, we
2237 # can store the default result where the exception frame was.
2253 # now, we copy the default result to it's proper location
2261 bra.l _real_operr
2263 fu_inex_p2:
2265 bne.w fu_inex_s_p2
2269 bra.w fu_inex
2271 fu_inex_s_p2:
2273 bne.w fu_inex
2275 # the instruction was "fmove.p fpn,-(a7)" from supervisor mode.
2276 # the strategy is to move the exception frame "down" 12 bytes. then, we
2277 # can store the default result where the exception frame was.
2293 # now, we copy the default result to it's proper location
2301 bra.l _real_inex
2303 #########################################################################
2305 #
2306 # if we're stuffing a source operand back into an fsave frame then we
2307 # have to make sure that for single or double source operands that the
2308 # format stuffed is as weird as the hardware usually makes it.
2309 #
2310 global funimp_skew
2311 funimp_skew:
2317 rts
2319 funimp_skew_sgl:
2322 beq.b funimp_skew_sgl_not
2324 bgt.b funimp_skew_sgl_not
2333 funimp_skew_sgl_not:
2334 rts
2336 funimp_skew_dbl:
2339 beq.b funimp_skew_dbl_not
2341 bgt.b funimp_skew_dbl_not
2354 fss_dbl_denorm_done:
2357 funimp_skew_dbl_not:
2358 rts
2360 #########################################################################
2361 global _mem_write2
2362 _mem_write2:
2364 beq.l _dmem_write
2369 rts
2371 #########################################################################
2372 # XDEF **************************************************************** #
2373 # _fpsp_effadd(): 060FPSP entry point for FP "Unimplemented #
2374 # effective address" exception. #
2375 # #
2376 # This handler should be the first code executed upon taking the #
2377 # FP Unimplemented Effective Address exception in an operating #
2378 # system. #
2379 # #
2380 # XREF **************************************************************** #
2381 # _imem_read_long() - read instruction longword #
2382 # fix_skewed_ops() - adjust src operand in fsave frame #
2383 # set_tag_x() - determine optype of src/dst operands #
2384 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
2385 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
2386 # load_fpn2() - load dst operand from FP regfile #
2387 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
2388 # decbin() - convert packed data to FP binary data #
2389 # _real_fpu_disabled() - "callout" for "FPU disabled" exception #
2390 # _real_access() - "callout" for access error exception #
2391 # _mem_read() - read extended immediate operand from memory #
2392 # _fpsp_done() - "callout" for exit; work all done #
2393 # _real_trace() - "callout" for Trace enabled exception #
2394 # fmovm_dynamic() - emulate dynamic fmovm instruction #
2395 # fmovm_ctrl() - emulate fmovm control instruction #
2396 # #
2397 # INPUT *************************************************************** #
2398 # - The system stack contains the "Unimplemented <ea>" stk frame #
2399 # #
2400 # OUTPUT ************************************************************** #
2401 # If access error: #
2402 # - The system stack is changed to an access error stack frame #
2403 # If FPU disabled: #
2404 # - The system stack is changed to an FPU disabled stack frame #
2405 # If Trace exception enabled: #
2406 # - The system stack is changed to a Trace exception stack frame #
2407 # Else: (normal case) #
2408 # - None (correct result has been stored as appropriate) #
2409 # #
2410 # ALGORITHM *********************************************************** #
2411 # This exception handles 3 types of operations: #
2412 # (1) FP Instructions using extended precision or packed immediate #
2413 # addressing mode. #
2414 # (2) The "fmovm.x" instruction w/ dynamic register specification. #
2415 # (3) The "fmovm.l" instruction w/ 2 or 3 control registers. #
2416 # #
2417 # For immediate data operations, the data is read in w/ a #
2418 # _mem_read() "callout", converted to FP binary (if packed), and used #
2419 # as the source operand to the instruction specified by the instruction #
2420 # word. If no FP exception should be reported ads a result of the #
2421 # emulation, then the result is stored to the destination register and #
2422 # the handler exits through _fpsp_done(). If an enabled exc has been #
2423 # signalled as a result of emulation, then an fsave state frame #
2424 # corresponding to the FP exception type must be entered into the 060 #
2425 # FPU before exiting. In either the enabled or disabled cases, we #
2426 # must also check if a Trace exception is pending, in which case, we #
2427 # must create a Trace exception stack frame from the current exception #
2428 # stack frame. If no Trace is pending, we simply exit through #
2429 # _fpsp_done(). #
2430 # For "fmovm.x", call the routine fmovm_dynamic() which will #
2431 # decode and emulate the instruction. No FP exceptions can be pending #
2432 # as a result of this operation emulation. A Trace exception can be #
2433 # pending, though, which means the current stack frame must be changed #
2434 # to a Trace stack frame and an exit made through _real_trace(). #
2435 # For the case of "fmovm.x Dn,-(a7)", where the offending instruction #
2436 # was executed from supervisor mode, this handler must store the FP #
2437 # register file values to the system stack by itself since #
2438 # fmovm_dynamic() can't handle this. A normal exit is made through #
2439 # fpsp_done(). #
2440 # For "fmovm.l", fmovm_ctrl() is used to emulate the instruction. #
2441 # Again, a Trace exception may be pending and an exit made through #
2442 # _real_trace(). Else, a normal exit is made through _fpsp_done(). #
2443 # #
2444 # Before any of the above is attempted, it must be checked to #
2445 # see if the FPU is disabled. Since the "Unimp <ea>" exception is taken #
2446 # before the "FPU disabled" exception, but the "FPU disabled" exception #
2447 # has higher priority, we check the disabled bit in the PCR. If set, #
2448 # then we must create an 8 word "FPU disabled" exception stack frame #
2449 # from the current 4 word exception stack frame. This includes #
2450 # reproducing the effective address of the instruction to put on the #
2451 # new stack frame. #
2452 # #
2453 # In the process of all emulation work, if a _mem_read() #
2454 # "callout" returns a failing result indicating an access error, then #
2455 # we must create an access error stack frame from the current stack #
2456 # frame. This information includes a faulting address and a fault- #
2457 # status-longword. These are created within this handler. #
2458 # #
2459 #########################################################################
2461 global _fpsp_effadd
2462 _fpsp_effadd:
2464 # This exception type takes priority over the "Line F Emulator"
2465 # exception. Therefore, the FPU could be disabled when entering here.
2466 # So, we must check to see if it's disabled and handle that case separately.
2470 bne.w iea_disabled # yes
2479 # PC of instruction that took the exception is the PC in the frame
2487 #########################################################################
2490 bmi.w iea_fmovm # yes
2492 #
2493 # here, we will have:
2494 # fabs fdabs fsabs facos fmod
2495 # fadd fdadd fsadd fasin frem
2496 # fcmp fatan fscale
2497 # fdiv fddiv fsdiv fatanh fsin
2498 # fint fcos fsincos
2499 # fintrz fcosh fsinh
2500 # fmove fdmove fsmove fetox ftan
2501 # fmul fdmul fsmul fetoxm1 ftanh
2502 # fneg fdneg fsneg fgetexp ftentox
2503 # fsgldiv fgetman ftwotox
2504 # fsglmul flog10
2505 # fsqrt flog2
2506 # fsub fdsub fssub flogn
2507 # ftst flognp1
2508 # which can all use f<op>.{x,p}
2509 # so, now it's immediate data extended precision AND PACKED FORMAT!
2510 #
2511 iea_op:
2524 bne.w iea_iacc # yes
2526 bra.b iea_op_setsrc
2528 iea_op_pack:
2536 bne.w iea_iacc # yes
2538 # The packed operand is an INF or a NAN if the exponent field is all ones.
2543 # The packed operand is a zero if the mantissa is all zero, else it's
2544 # a normal packed op.
2552 iea_op_gp_not_spec:
2557 iea_op_setsrc:
2560 # FP_SRC now holds the src operand.
2568 iea_op_getdst:
2576 iea_op_loaddst:
2587 bra.b iea_op_extract
2589 # the operation is fsincos, ftst, or fcmp. only fcmp is dyadic
2590 iea_op_spec:
2593 # now, we're left with ftst and fcmp. so, first let's tag them so that they don't
2594 # store a result. then, only fcmp will branch back and pick up a dst operand.
2599 iea_op_extract:
2615 #
2616 # Exceptions in order of precedence:
2617 # BSUN : none
2618 # SNAN : all operations
2619 # OPERR : all reg-reg or mem-reg operations that can normally operr
2620 # OVFL : same as OPERR
2621 # UNFL : same as OPERR
2622 # DZ : same as OPERR
2623 # INEX2 : same as OPERR
2624 # INEX1 : all packed immediate operations
2625 #
2627 # we determine the highest priority exception(if any) set by the
2628 # emulation routine that has also been enabled by the user.
2632 # now, we save the result, unless, of course, the operation was ftst or fcmp.
2633 # these don't save results.
2634 iea_op_save:
2638 iea_op_store:
2642 iea_op_exit1:
2653 bne.w iea_op_trace # yes
2657 iea_op_ena:
2662 # no exception occurred. now, did a disabled, exact overflow occur with inexact
2663 # enabled? if so, then we have to stuff an overflow frame into the FPU.
2665 beq.b iea_op_save
2667 iea_op_ovfl:
2672 # an enabled exception occurred. we have to insert the exception type back into
2673 # the machine.
2674 iea_op_exc:
2679 # the enabled exception was inexact. so, if it occurs with an overflow
2680 # or underflow that was disabled, then we have to force an overflow or
2681 # underflow frame.
2687 iea_op_exc_force:
2691 tbl_iea_except:
2695 iea_op_exc_ovfl:
2697 bra.b iea_op_exit2
2699 iea_op_exc_unfl:
2702 iea_op_exit2:
2719 #
2720 # The opclass two instruction that took an "Unimplemented Effective Address"
2721 # exception was being traced. Make the "current" PC the FPIAR and put it in
2722 # the trace stack frame then jump to _real_trace().
2723 #
2724 # UNIMP EA FRAME TRACE FRAME
2725 # ***************** *****************
2726 # * 0x0 * 0x0f0 * * Current *
2727 # ***************** * PC *
2728 # * Current * *****************
2729 # * PC * * 0x2 * 0x024 *
2730 # ***************** *****************
2731 # * SR * * Next *
2732 # ***************** * PC *
2733 # *****************
2734 # * SR *
2735 # *****************
2736 iea_op_trace:
2742 bra.l _real_trace
2744 #########################################################################
2745 iea_fmovm:
2747 beq.w iea_fmovm_ctrl
2749 iea_fmovm_data:
2752 bne.b iea_fmovm_data_s
2754 iea_fmovm_data_u:
2760 bra.w iea_fmovm_exit
2762 iea_fmovm_data_s:
2769 beq.w iea_fmovm_data_predec
2771 bne.w iea_fmovm_exit
2773 # right now, d0 = the size.
2774 # the data has been fetched from the supervisor stack, but we have not
2775 # incremented the stack pointer by the appropriate number of bytes.
2776 # do it here.
2777 iea_fmovm_data_postinc:
2779 bne.b iea_fmovm_data_pi_trace
2792 unlk %a6
2794 bra.l _fpsp_done
2796 iea_fmovm_data_pi_trace:
2809 unlk %a6
2811 bra.l _real_trace
2813 # right now, d1 = size and d0 = the strg.
2814 iea_fmovm_data_predec:
2832 beq.b iea_fmovm_data_p2
2840 bra.b iea_fmovm_data_p3
2842 iea_fmovm_data_p2:
2849 iea_fmovm_data_p3:
2854 bpl.b fm_1
2857 fm_1:
2859 bpl.b fm_2
2862 fm_2:
2864 bpl.b fm_3
2867 fm_3:
2869 bpl.b fm_4
2872 fm_4:
2874 bpl.b fm_5
2877 fm_5:
2879 bpl.b fm_6
2882 fm_6:
2884 bpl.b fm_7
2887 fm_7:
2889 bpl.b fm_end
2891 fm_end:
2898 beq.l _fpsp_done
2899 bra.l _real_trace
2901 #########################################################################
2902 iea_fmovm_ctrl:
2906 iea_fmovm_exit:
2920 #
2921 # The control reg instruction that took an "Unimplemented Effective Address"
2922 # exception was being traced. The "Current PC" for the trace frame is the
2923 # PC stacked for Unimp EA. The "Next PC" is in EXC_EXTWPTR.
2924 # After fixing the stack frame, jump to _real_trace().
2925 #
2926 # UNIMP EA FRAME TRACE FRAME
2927 # ***************** *****************
2928 # * 0x0 * 0x0f0 * * Current *
2929 # ***************** * PC *
2930 # * Current * *****************
2931 # * PC * * 0x2 * 0x024 *
2932 # ***************** *****************
2933 # * SR * * Next *
2934 # ***************** * PC *
2935 # *****************
2936 # * SR *
2937 # *****************
2938 # this ain't a pretty solution, but it works:
2939 # -restore a6 (not with unlk)
2940 # -shift stack frame down over where old a6 used to be
2941 # -add LOCAL_SIZE to stack pointer
2942 iea_fmovm_trace:
2950 bra.l _real_trace
2952 #########################################################################
2953 # The FPU is disabled and so we should really have taken the "Line
2954 # F Emulator" exception. So, here we create an 8-word stack frame
2955 # from our 4-word stack frame. This means we must calculate the length
2956 # of the faulting instruction to get the "next PC". This is trivial for
2957 # immediate operands but requires some extra work for fmovm dynamic
2958 # which can use most addressing modes.
2959 iea_disabled:
2966 # PC of instruction that took the exception is the PC in the frame
2975 # instruction is using an extended precision immediate operand. therefore,
2976 # the total instruction length is 16 bytes.
2977 iea_dis_immed:
2979 bra.b iea_dis_cont
2980 iea_dis_fmovm:
2983 # the instruction is a fmovm.l with 2 or 3 registers.
2987 bne.b iea_dis_cont
2989 bra.b iea_dis_cont
2990 # the instruction is an fmovm.x dynamic which can use many addressing
2991 # modes and thus can have several different total instruction lengths.
2992 # call fmovm_calc_ea which will go through the ea calc process and,
2993 # as a by-product, will tell us how long the instruction is.
2994 iea_dis_fmovm_data:
2996 bsr.l fmovm_calc_ea
2999 iea_dis_cont:
3004 unlk %a6
3006 # here, we actually create the 8-word frame from the 4-word frame,
3007 # with the "next PC" as additional info.
3008 # the <ea> field is let as undefined.
3020 bra.l _real_fpu_disabled
3022 ##########
3024 iea_iacc:
3027 bne.b iea_iacc_cont
3030 iea_iacc_cont:
3033 unlk %a6
3042 iea_acc_done:
3047 iea_acc_done2:
3048 bra.l _real_access
3050 iea_dacc:
3055 bne.b iea_dacc_cont
3058 iea_dacc_cont:
3071 bra.b iea_acc_done
3073 #########################################################################
3074 # XDEF **************************************************************** #
3075 # _fpsp_operr(): 060FPSP entry point for FP Operr exception. #
3076 # #
3077 # This handler should be the first code executed upon taking the #
3078 # FP Operand Error exception in an operating system. #
3079 # #
3080 # XREF **************************************************************** #
3081 # _imem_read_long() - read instruction longword #
3082 # fix_skewed_ops() - adjust src operand in fsave frame #
3083 # _real_operr() - "callout" to operating system operr handler #
3084 # _dmem_write_{byte,word,long}() - store data to mem (opclass 3) #
3085 # store_dreg_{b,w,l}() - store data to data regfile (opclass 3) #
3086 # facc_out_{b,w,l}() - store to memory took access error (opcl 3) #
3087 # #
3088 # INPUT *************************************************************** #
3089 # - The system stack contains the FP Operr exception frame #
3090 # - The fsave frame contains the source operand #
3091 # #
3092 # OUTPUT ************************************************************** #
3093 # No access error: #
3094 # - The system stack is unchanged #
3095 # - The fsave frame contains the adjusted src op for opclass 0,2 #
3096 # #
3097 # ALGORITHM *********************************************************** #
3098 # In a system where the FP Operr exception is enabled, the goal #
3099 # is to get to the handler specified at _real_operr(). But, on the 060, #
3100 # for opclass zero and two instruction taking this exception, the #
3101 # input operand in the fsave frame may be incorrect for some cases #
3102 # and needs to be corrected. This handler calls fix_skewed_ops() to #
3103 # do just this and then exits through _real_operr(). #
3104 # For opclass 3 instructions, the 060 doesn't store the default #
3105 # operr result out to memory or data register file as it should. #
3106 # This code must emulate the move out before finally exiting through #
3107 # _real_inex(). The move out, if to memory, is performed using #
3108 # _mem_write() "callout" routines that may return a failing result. #
3109 # In this special case, the handler must exit through facc_out() #
3110 # which creates an access error stack frame from the current operr #
3111 # stack frame. #
3112 # #
3113 #########################################################################
3115 global _fpsp_operr
3116 _fpsp_operr:
3126 # the FPIAR holds the "current PC" of the faulting instruction
3134 ##############################################################################
3140 # here, we simply see if the operand in the fsave frame needs to be "unskewed".
3141 # this would be the case for opclass two operations with a source infinity or
3142 # denorm operand in the sgl or dbl format. NANs also become skewed, but can't
3143 # cause an operr so we don't need to check for them here.
3147 foperr_exit:
3154 unlk %a6
3155 bra.l _real_operr
3157 ########################################################################
3159 #
3160 # the hardware does not save the default result to memory on enabled
3161 # operand error exceptions. we do this here before passing control to
3162 # the user operand error handler.
3163 #
3164 # byte, word, and long destination format operations can pass
3165 # through here. we simply need to test the sign of the src
3166 # operand and save the appropriate minimum or maximum integer value
3167 # to the effective address as pointed to by the stacked effective address.
3168 #
3169 # although packed opclass three operations can take operand error
3170 # exceptions, they won't pass through here since they are caught
3171 # first by the unsupported data format exception handler. that handler
3172 # sends them directly to _real_operr() if necessary.
3173 #
3174 foperr_out:
3179 bne.b foperr_out_not_qnan
3180 # the operand is either an infinity or a QNAN.
3182 bne.b foperr_out_qnan
3185 beq.b foperr_out_not_qnan
3186 foperr_out_qnan:
3188 bra.b foperr_out_jmp
3190 foperr_out_not_qnan:
3193 bpl.b foperr_out_not_qnan2
3195 foperr_out_not_qnan2:
3198 foperr_out_jmp:
3204 tbl_operr:
3214 foperr_out_b:
3224 bra.w foperr_exit
3225 foperr_out_b_save_dn:
3228 bra.w foperr_exit
3230 foperr_out_w:
3240 bra.w foperr_exit
3241 foperr_out_w_save_dn:
3244 bra.w foperr_exit
3246 foperr_out_l:
3256 bra.w foperr_exit
3257 foperr_out_l_save_dn:
3260 bra.w foperr_exit
3262 #########################################################################
3263 # XDEF **************************************************************** #
3264 # _fpsp_snan(): 060FPSP entry point for FP SNAN exception. #
3265 # #
3266 # This handler should be the first code executed upon taking the #
3267 # FP Signalling NAN exception in an operating system. #
3268 # #
3269 # XREF **************************************************************** #
3270 # _imem_read_long() - read instruction longword #
3271 # fix_skewed_ops() - adjust src operand in fsave frame #
3272 # _real_snan() - "callout" to operating system SNAN handler #
3273 # _dmem_write_{byte,word,long}() - store data to mem (opclass 3) #
3274 # store_dreg_{b,w,l}() - store data to data regfile (opclass 3) #
3275 # facc_out_{b,w,l,d,x}() - store to mem took acc error (opcl 3) #
3276 # _calc_ea_fout() - fix An if <ea> is -() or ()+; also get <ea> #
3277 # #
3278 # INPUT *************************************************************** #
3279 # - The system stack contains the FP SNAN exception frame #
3280 # - The fsave frame contains the source operand #
3281 # #
3282 # OUTPUT ************************************************************** #
3283 # No access error: #
3284 # - The system stack is unchanged #
3285 # - The fsave frame contains the adjusted src op for opclass 0,2 #
3286 # #
3287 # ALGORITHM *********************************************************** #
3288 # In a system where the FP SNAN exception is enabled, the goal #
3289 # is to get to the handler specified at _real_snan(). But, on the 060, #
3290 # for opclass zero and two instructions taking this exception, the #
3291 # input operand in the fsave frame may be incorrect for some cases #
3292 # and needs to be corrected. This handler calls fix_skewed_ops() to #
3293 # do just this and then exits through _real_snan(). #
3294 # For opclass 3 instructions, the 060 doesn't store the default #
3295 # SNAN result out to memory or data register file as it should. #
3296 # This code must emulate the move out before finally exiting through #
3297 # _real_snan(). The move out, if to memory, is performed using #
3298 # _mem_write() "callout" routines that may return a failing result. #
3299 # In this special case, the handler must exit through facc_out() #
3300 # which creates an access error stack frame from the current SNAN #
3301 # stack frame. #
3302 # For the case of an extended precision opclass 3 instruction, #
3303 # if the effective addressing mode was -() or ()+, then the address #
3304 # register must get updated by calling _calc_ea_fout(). If the <ea> #
3305 # was -(a7) from supervisor mode, then the exception frame currently #
3306 # on the system stack must be carefully moved "down" to make room #
3307 # for the operand being moved. #
3308 # #
3309 #########################################################################
3311 global _fpsp_snan
3312 _fpsp_snan:
3322 # the FPIAR holds the "current PC" of the faulting instruction
3330 ##############################################################################
3333 bne.w fsnan_out # fmove out
3336 # here, we simply see if the operand in the fsave frame needs to be "unskewed".
3337 # this would be the case for opclass two operations with a source infinity or
3338 # denorm operand in the sgl or dbl format. NANs also become skewed and must be
3339 # fixed here.
3343 fsnan_exit:
3350 unlk %a6
3351 bra.l _real_snan
3353 ########################################################################
3355 #
3356 # the hardware does not save the default result to memory on enabled
3357 # snan exceptions. we do this here before passing control to
3358 # the user snan handler.
3359 #
3360 # byte, word, long, and packed destination format operations can pass
3361 # through here. since packed format operations already were handled by
3362 # fpsp_unsupp(), then we need to do nothing else for them here.
3363 # for byte, word, and long, we simply need to test the sign of the src
3364 # operand and save the appropriate minimum or maximum integer value
3365 # to the effective address as pointed to by the stacked effective address.
3366 #
3367 fsnan_out:
3374 tbl_snan:
3384 fsnan_out_b:
3395 bra.w fsnan_exit
3396 fsnan_out_b_dn:
3399 bra.w fsnan_exit
3401 fsnan_out_w:
3412 bra.w fsnan_exit
3413 fsnan_out_w_dn:
3416 bra.w fsnan_exit
3418 fsnan_out_l:
3429 bra.w fsnan_exit
3430 fsnan_out_l_dn:
3433 bra.w fsnan_exit
3435 fsnan_out_s:
3450 bra.w fsnan_exit
3451 fsnan_out_d_dn:
3462 bra.w fsnan_exit
3464 fsnan_out_d:
3488 bra.w fsnan_exit
3490 # for extended precision, if the addressing mode is pre-decrement or
3491 # post-increment, then the address register did not get updated.
3492 # in addition, for pre-decrement, the stacked <ea> is incorrect.
3493 fsnan_out_x:
3518 fsnan_out_x_save:
3526 bra.w fsnan_exit
3528 fsnan_out_x_s:
3540 # the operation was "fmove.x SNAN,-(a7)" from supervisor mode.
3559 bra.l _real_snan
3561 #########################################################################
3562 # XDEF **************************************************************** #
3563 # _fpsp_inex(): 060FPSP entry point for FP Inexact exception. #
3564 # #
3565 # This handler should be the first code executed upon taking the #
3566 # FP Inexact exception in an operating system. #
3567 # #
3568 # XREF **************************************************************** #
3569 # _imem_read_long() - read instruction longword #
3570 # fix_skewed_ops() - adjust src operand in fsave frame #
3571 # set_tag_x() - determine optype of src/dst operands #
3572 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
3573 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
3574 # load_fpn2() - load dst operand from FP regfile #
3575 # smovcr() - emulate an "fmovcr" instruction #
3576 # fout() - emulate an opclass 3 instruction #
3577 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
3578 # _real_inex() - "callout" to operating system inexact handler #
3579 # #
3580 # INPUT *************************************************************** #
3581 # - The system stack contains the FP Inexact exception frame #
3582 # - The fsave frame contains the source operand #
3583 # #
3584 # OUTPUT ************************************************************** #
3585 # - The system stack is unchanged #
3586 # - The fsave frame contains the adjusted src op for opclass 0,2 #
3587 # #
3588 # ALGORITHM *********************************************************** #
3589 # In a system where the FP Inexact exception is enabled, the goal #
3590 # is to get to the handler specified at _real_inex(). But, on the 060, #
3591 # for opclass zero and two instruction taking this exception, the #
3592 # hardware doesn't store the correct result to the destination FP #
3593 # register as did the '040 and '881/2. This handler must emulate the #
3594 # instruction in order to get this value and then store it to the #
3595 # correct register before calling _real_inex(). #
3596 # For opclass 3 instructions, the 060 doesn't store the default #
3597 # inexact result out to memory or data register file as it should. #
3598 # This code must emulate the move out by calling fout() before finally #
3599 # exiting through _real_inex(). #
3600 # #
3601 #########################################################################
3603 global _fpsp_inex
3604 _fpsp_inex:
3614 # the FPIAR holds the "current PC" of the faulting instruction
3622 ##############################################################################
3625 bne.w finex_out # fmove out
3628 # the hardware, for "fabs" and "fneg" w/ a long source format, puts the
3629 # longword integer directly into the upper longword of the mantissa along
3630 # w/ an exponent value of 0x401e. we convert this to extended precision here.
3640 finex_cont:
3644 # Here, we zero the ccode and exception byte field since we're going to
3645 # emulate the whole instruction. Notice, though, that we don't kill the
3646 # INEX1 bit. This is because a packed op has long since been converted
3647 # to extended before arriving here. Therefore, we need to retain the
3648 # INEX1 bit from when the operand was first converted.
3656 beq.w finex_fmovcr # yes
3662 # bits four and five of the fp extension word separate the monadic and dyadic
3663 # operations that can pass through fpsp_inex(). remember that fcmp and ftst
3664 # will never take this exception, but fsincos will.
3679 finex_op2_done:
3682 finex_extract:
3695 # the operation has been emulated. the result is in fp0.
3696 finex_save:
3698 bsr.l store_fpreg
3700 finex_exit:
3707 unlk %a6
3708 bra.l _real_inex
3710 finex_fmovcr:
3715 bsr.l smovcr
3716 bra.b finex_save
3718 ########################################################################
3720 #
3721 # the hardware does not save the default result to memory on enabled
3722 # inexact exceptions. we do this here before passing control to
3723 # the user inexact handler.
3724 #
3725 # byte, word, and long destination format operations can pass
3726 # through here. so can double and single precision.
3727 # although packed opclass three operations can take inexact
3728 # exceptions, they won't pass through here since they are caught
3729 # first by the unsupported data format exception handler. that handler
3730 # sends them directly to _real_inex() if necessary.
3731 #
3732 finex_out:
3745 bra.b finex_exit
3747 #########################################################################
3748 # XDEF **************************************************************** #
3749 # _fpsp_dz(): 060FPSP entry point for FP DZ exception. #
3750 # #
3751 # This handler should be the first code executed upon taking #
3752 # the FP DZ exception in an operating system. #
3753 # #
3754 # XREF **************************************************************** #
3755 # _imem_read_long() - read instruction longword from memory #
3756 # fix_skewed_ops() - adjust fsave operand #
3757 # _real_dz() - "callout" exit point from FP DZ handler #
3758 # #
3759 # INPUT *************************************************************** #
3760 # - The system stack contains the FP DZ exception stack. #
3761 # - The fsave frame contains the source operand. #
3762 # #
3763 # OUTPUT ************************************************************** #
3764 # - The system stack contains the FP DZ exception stack. #
3765 # - The fsave frame contains the adjusted source operand. #
3766 # #
3767 # ALGORITHM *********************************************************** #
3768 # In a system where the DZ exception is enabled, the goal is to #
3769 # get to the handler specified at _real_dz(). But, on the 060, when the #
3770 # exception is taken, the input operand in the fsave state frame may #
3771 # be incorrect for some cases and need to be adjusted. So, this package #
3772 # adjusts the operand using fix_skewed_ops() and then branches to #
3773 # _real_dz(). #
3774 # #
3775 #########################################################################
3777 global _fpsp_dz
3778 _fpsp_dz:
3788 # the FPIAR holds the "current PC" of the faulting instruction
3796 ##############################################################################
3799 # here, we simply see if the operand in the fsave frame needs to be "unskewed".
3800 # this would be the case for opclass two operations with a source zero
3801 # in the sgl or dbl format.
3805 fdz_exit:
3812 unlk %a6
3813 bra.l _real_dz
3815 #########################################################################
3816 # XDEF **************************************************************** #
3817 # _fpsp_fline(): 060FPSP entry point for "Line F emulator" #
3818 # exception when the "reduced" version of the #
3819 # FPSP is implemented that does not emulate #
3820 # FP unimplemented instructions. #
3821 # #
3822 # This handler should be the first code executed upon taking a #
3823 # "Line F Emulator" exception in an operating system integrating #
3824 # the reduced version of 060FPSP. #
3825 # #
3826 # XREF **************************************************************** #
3827 # _real_fpu_disabled() - Handle "FPU disabled" exceptions #
3828 # _real_fline() - Handle all other cases (treated equally) #
3829 # #
3830 # INPUT *************************************************************** #
3831 # - The system stack contains a "Line F Emulator" exception #
3832 # stack frame. #
3833 # #
3834 # OUTPUT ************************************************************** #
3835 # - The system stack is unchanged. #
3836 # #
3837 # ALGORITHM *********************************************************** #
3838 # When a "Line F Emulator" exception occurs in a system where #
3839 # "FPU Unimplemented" instructions will not be emulated, the exception #
3840 # can occur because then FPU is disabled or the instruction is to be #
3841 # classifed as "Line F". This module determines which case exists and #
3842 # calls the appropriate "callout". #
3843 # #
3844 #########################################################################
3846 global _fpsp_fline
3847 _fpsp_fline:
3849 # check to see if the FPU is disabled. if so, jump to the OS entry
3850 # point for that condition.
3852 beq.l _real_fpu_disabled
3854 bra.l _real_fline
3856 #########################################################################
3857 # XDEF **************************************************************** #
3858 # _dcalc_ea(): calc correct <ea> from <ea> stacked on exception #
3859 # #
3860 # XREF **************************************************************** #
3861 # inc_areg() - increment an address register #
3862 # dec_areg() - decrement an address register #
3863 # #
3864 # INPUT *************************************************************** #
3865 # d0 = number of bytes to adjust <ea> by #
3866 # #
3867 # OUTPUT ************************************************************** #
3868 # None #
3869 # #
3870 # ALGORITHM *********************************************************** #
3871 # "Dummy" CALCulate Effective Address: #
3872 # The stacked <ea> for FP unimplemented instructions and opclass #
3873 # two packed instructions is correct with the exception of... #
3874 # #
3875 # 1) -(An) : The register is not updated regardless of size. #
3876 # Also, for extended precision and packed, the #
3877 # stacked <ea> value is 8 bytes too big #
3878 # 2) (An)+ : The register is not updated. #
3879 # 3) #<data> : The upper longword of the immediate operand is #
3880 # stacked b,w,l and s sizes are completely stacked. #
3881 # d,x, and p are not. #
3882 # #
3883 #########################################################################
3885 global _dcalc_ea
3886 _dcalc_ea:
3907 rts
3909 # need to set immediate data flag here since we'll need to do
3910 # an imem_read to fetch this later.
3911 dcea_imm:
3914 rts
3916 # here, the <ea> is stacked correctly. however, we must update the
3917 # address register...
3918 dcea_pi:
3923 rts
3925 # the <ea> is stacked correctly for all but extended and packed which
3926 # the <ea>s are 8 bytes too large.
3927 # it would make no sense to have a pre-decrement to a7 in supervisor
3928 # mode so we don't even worry about this tricky case here : )
3929 dcea_pd:
3937 rts
3938 dcea_pd2:
3941 rts
3943 #########################################################################
3944 # XDEF **************************************************************** #
3945 # _calc_ea_fout(): calculate correct stacked <ea> for extended #
3946 # and packed data opclass 3 operations. #
3947 # #
3948 # XREF **************************************************************** #
3949 # None #
3950 # #
3951 # INPUT *************************************************************** #
3952 # None #
3953 # #
3954 # OUTPUT ************************************************************** #
3955 # a0 = return correct effective address #
3956 # #
3957 # ALGORITHM *********************************************************** #
3958 # For opclass 3 extended and packed data operations, the <ea> #
3959 # stacked for the exception is incorrect for -(an) and (an)+ addressing #
3960 # modes. Also, while we're at it, the index register itself must get #
3961 # updated. #
3962 # So, for -(an), we must subtract 8 off of the stacked <ea> value #
3963 # and return that value as the correct <ea> and store that value in An. #
3964 # For (an)+, the stacked <ea> is correct but we must adjust An by +12. #
3965 # #
3966 #########################################################################
3968 # This calc_ea is currently used to retrieve the correct <ea>
3969 # for fmove outs of type extended and packed.
3970 global _calc_ea_fout
3971 _calc_ea_fout:
3982 beq.w ceaf_pd # yes
3985 rts
3987 # (An)+ : extended and packed fmove out
3988 # : stacked <ea> is correct
3989 # : "An" not updated
3990 ceaf_pi:
3996 tbl_ceaf_pi:
3997 short ceaf_pi0 - tbl_ceaf_pi
3998 short ceaf_pi1 - tbl_ceaf_pi
3999 short ceaf_pi2 - tbl_ceaf_pi
4000 short ceaf_pi3 - tbl_ceaf_pi
4001 short ceaf_pi4 - tbl_ceaf_pi
4002 short ceaf_pi5 - tbl_ceaf_pi
4003 short ceaf_pi6 - tbl_ceaf_pi
4004 short ceaf_pi7 - tbl_ceaf_pi
4006 ceaf_pi0:
4008 rts
4009 ceaf_pi1:
4011 rts
4012 ceaf_pi2:
4014 rts
4015 ceaf_pi3:
4017 rts
4018 ceaf_pi4:
4020 rts
4021 ceaf_pi5:
4023 rts
4024 ceaf_pi6:
4026 rts
4027 ceaf_pi7:
4030 rts
4032 # -(An) : extended and packed fmove out
4033 # : stacked <ea> = actual <ea> + 8
4034 # : "An" not updated
4035 ceaf_pd:
4043 tbl_ceaf_pd:
4044 short ceaf_pd0 - tbl_ceaf_pd
4045 short ceaf_pd1 - tbl_ceaf_pd
4046 short ceaf_pd2 - tbl_ceaf_pd
4047 short ceaf_pd3 - tbl_ceaf_pd
4048 short ceaf_pd4 - tbl_ceaf_pd
4049 short ceaf_pd5 - tbl_ceaf_pd
4050 short ceaf_pd6 - tbl_ceaf_pd
4051 short ceaf_pd7 - tbl_ceaf_pd
4053 ceaf_pd0:
4055 rts
4056 ceaf_pd1:
4058 rts
4059 ceaf_pd2:
4061 rts
4062 ceaf_pd3:
4064 rts
4065 ceaf_pd4:
4067 rts
4068 ceaf_pd5:
4070 rts
4071 ceaf_pd6:
4073 rts
4074 ceaf_pd7:
4077 rts
4079 #
4080 # This table holds the offsets of the emulation routines for each individual
4081 # math operation relative to the address of this table. Included are
4082 # routines like fadd/fmul/fabs. The transcendentals ARE NOT. This is because
4083 # this table is for the version if the 060FPSP without transcendentals.
4084 # The location within the table is determined by the extension bits of the
4085 # operation longword.
4086 #
4089 tbl_unsupp:
4095 long tbl_unsupp - tbl_unsupp
4097 long tbl_unsupp - tbl_unsupp
4101 long tbl_unsupp - tbl_unsupp
4109 long tbl_unsupp - tbl_unsupp
4113 long tbl_unsupp - tbl_unsupp
4117 long tbl_unsupp - tbl_unsupp
4131 long tbl_unsupp - tbl_unsupp
4132 long tbl_unsupp - tbl_unsupp
4133 long tbl_unsupp - tbl_unsupp
4134 long tbl_unsupp - tbl_unsupp
4135 long tbl_unsupp - tbl_unsupp
4136 long tbl_unsupp - tbl_unsupp
4137 long tbl_unsupp - tbl_unsupp
4147 long tbl_unsupp - tbl_unsupp
4149 long tbl_unsupp - tbl_unsupp
4150 long tbl_unsupp - tbl_unsupp
4151 long tbl_unsupp - tbl_unsupp
4152 long tbl_unsupp - tbl_unsupp
4153 long tbl_unsupp - tbl_unsupp
4156 long tbl_unsupp - tbl_unsupp
4157 long tbl_unsupp - tbl_unsupp
4160 long tbl_unsupp - tbl_unsupp
4161 long tbl_unsupp - tbl_unsupp
4162 long tbl_unsupp - tbl_unsupp
4163 long tbl_unsupp - tbl_unsupp
4164 long tbl_unsupp - tbl_unsupp
4165 long tbl_unsupp - tbl_unsupp
4166 long tbl_unsupp - tbl_unsupp
4167 long tbl_unsupp - tbl_unsupp
4168 long tbl_unsupp - tbl_unsupp
4169 long tbl_unsupp - tbl_unsupp
4170 long tbl_unsupp - tbl_unsupp
4171 long tbl_unsupp - tbl_unsupp
4172 long tbl_unsupp - tbl_unsupp
4173 long tbl_unsupp - tbl_unsupp
4174 long tbl_unsupp - tbl_unsupp
4175 long tbl_unsupp - tbl_unsupp
4176 long tbl_unsupp - tbl_unsupp
4177 long tbl_unsupp - tbl_unsupp
4179 long tbl_unsupp - tbl_unsupp
4181 long tbl_unsupp - tbl_unsupp
4183 long tbl_unsupp - tbl_unsupp
4185 long tbl_unsupp - tbl_unsupp
4187 long tbl_unsupp - tbl_unsupp
4191 long tbl_unsupp - tbl_unsupp
4195 long tbl_unsupp - tbl_unsupp
4196 long tbl_unsupp - tbl_unsupp
4197 long tbl_unsupp - tbl_unsupp
4200 #################################################
4201 # Add this here so non-fp modules can compile.
4202 # (smovcr is called from fpsp_inex.)
4203 global smovcr
4204 smovcr:
4205 bra.b smovcr
4207 #########################################################################
4208 # XDEF **************************************************************** #
4209 # fmovm_dynamic(): emulate "fmovm" dynamic instruction #
4210 # #
4211 # XREF **************************************************************** #
4212 # fetch_dreg() - fetch data register #
4213 # {i,d,}mem_read() - fetch data from memory #
4214 # _mem_write() - write data to memory #
4215 # iea_iacc() - instruction memory access error occurred #
4216 # iea_dacc() - data memory access error occurred #
4217 # restore() - restore An index regs if access error occurred #
4218 # #
4219 # INPUT *************************************************************** #
4220 # None #
4221 # #
4222 # OUTPUT ************************************************************** #
4223 # If instr is "fmovm Dn,-(A7)" from supervisor mode, #
4224 # d0 = size of dump #
4225 # d1 = Dn #
4226 # Else if instruction access error, #
4227 # d0 = FSLW #
4228 # Else if data access error, #
4229 # d0 = FSLW #
4230 # a0 = address of fault #
4231 # Else #
4232 # none. #
4233 # #
4234 # ALGORITHM *********************************************************** #
4235 # The effective address must be calculated since this is entered #
4236 # from an "Unimplemented Effective Address" exception handler. So, we #
4237 # have our own fcalc_ea() routine here. If an access error is flagged #
4238 # by a _{i,d,}mem_read() call, we must exit through the special #
4239 # handler. #
4240 # The data register is determined and its value loaded to get the #
4241 # string of FP registers affected. This value is used as an index into #
4242 # a lookup table such that we can determine the number of bytes #
4243 # involved. #
4244 # If the instruction is "fmovm.x <ea>,Dn", a _mem_read() is used #
4245 # to read in all FP values. Again, _mem_read() may fail and require a #
4246 # special exit. #
4247 # If the instruction is "fmovm.x DN,<ea>", a _mem_write() is used #
4248 # to write all FP values. _mem_write() may also fail. #
4249 # If the instruction is "fmovm.x DN,-(a7)" from supervisor mode, #
4250 # then we return the size of the dump and the string to the caller #
4251 # so that the move can occur outside of this routine. This special #
4252 # case is required so that moves to the system stack are handled #
4253 # correctly. #
4254 # #
4255 # DYNAMIC: #
4256 # fmovm.x dn, <ea> #
4257 # fmovm.x <ea>, dn #
4258 # #
4259 # <WORD 1> <WORD2> #
4260 # 1111 0010 00 |<ea>| 11@& 1000 0$$$ 0000 #
4261 # #
4262 # & = (0): predecrement addressing mode #
4263 # (1): postincrement or control addressing mode #
4264 # @ = (0): move listed regs from memory to the FPU #
4265 # (1): move listed regs from the FPU to memory #
4266 # $$$ : index of data register holding reg select mask #
4267 # #
4268 # NOTES: #
4269 # If the data register holds a zero, then the #
4270 # instruction is a nop. #
4271 # #
4272 #########################################################################
4274 global fmovm_dynamic
4275 fmovm_dynamic:
4277 # extract the data register in which the bit string resides...
4282 # fetch the bit string into d0...
4294 # if the bit string is a zero, then the operation is a no-op
4295 # but, make sure that we've calculated ea and advanced the opword pointer
4296 beq.w fmovm_data_done
4298 # separate move ins from move outs...
4300 beq.w fmovm_data_in # it's a move out
4302 #############
4303 # MOVE OUT: #
4304 #############
4305 fmovm_data_out:
4307 bne.w fmovm_out_ctrl # control
4309 ############################
4310 fmovm_out_predec:
4311 # for predecrement mode, the bit string is the opposite of both control
4312 # operations and postincrement mode. (bit7 = FP7 ... bit0 = FP0)
4313 # here, we convert it to be just like the others...
4319 fmovm_out_predec_s:
4321 bne.b fmovm_out_ctrl
4323 # the operation was unfortunately an: fmovm.x dn,-(sp)
4324 # called from supervisor mode.
4325 # we're also passing "size" and "strg" back to the calling routine
4326 rts
4328 ############################
4329 fmovm_out_ctrl:
4342 fmovm_out_ctrl_fp1:
4350 fmovm_out_ctrl_fp2:
4357 fmovm_out_ctrl_fp3:
4364 fmovm_out_ctrl_fp4:
4371 fmovm_out_ctrl_fp5:
4378 fmovm_out_ctrl_fp6:
4385 fmovm_out_ctrl_fp7:
4392 fmovm_out_ctrl_done:
4403 bne.w fmovm_out_err # yes
4405 rts
4407 ############
4408 # MOVE IN: #
4409 ############
4410 fmovm_data_in:
4424 bne.w fmovm_in_err # yes
4437 fmovm_data_in_fp1:
4445 fmovm_data_in_fp2:
4451 fmovm_data_in_fp3:
4457 fmovm_data_in_fp4:
4463 fmovm_data_in_fp5:
4469 fmovm_data_in_fp6:
4475 fmovm_data_in_fp7:
4481 fmovm_data_in_done:
4483 rts
4485 #####################################
4487 fmovm_data_done:
4488 rts
4490 ##############################################################################
4492 #
4493 # table indexed by the operation's bit string that gives the number
4494 # of bytes that will be moved.
4495 #
4496 # number of bytes = (# of 1's in bit string) * 12(bytes/fpreg)
4497 #
4498 tbl_fmovm_size:
4532 #
4533 # table to convert a pre-decrement bit string into a post-increment
4534 # or control bit string.
4535 # ex: 0x00 ==> 0x00
4536 # 0x01 ==> 0x80
4537 # 0x02 ==> 0x40
4538 # .
4539 # .
4540 # 0xfd ==> 0xbf
4541 # 0xfe ==> 0x7f
4542 # 0xff ==> 0xff
4543 #
4544 tbl_fmovm_convert:
4578 global fmovm_calc_ea
4579 ###############################################
4580 # _fmovm_calc_ea: calculate effective address #
4581 ###############################################
4582 fmovm_calc_ea:
4585 # currently, MODE and REG are taken from the EXC_OPWORD. this could be
4586 # easily changed if they were inputs passed in registers.
4593 # jump to the corresponding function for each {MODE,REG} pair.
4598 tbl_fea_mode:
4599 short tbl_fea_mode - tbl_fea_mode
4600 short tbl_fea_mode - tbl_fea_mode
4601 short tbl_fea_mode - tbl_fea_mode
4602 short tbl_fea_mode - tbl_fea_mode
4603 short tbl_fea_mode - tbl_fea_mode
4604 short tbl_fea_mode - tbl_fea_mode
4605 short tbl_fea_mode - tbl_fea_mode
4606 short tbl_fea_mode - tbl_fea_mode
4608 short tbl_fea_mode - tbl_fea_mode
4609 short tbl_fea_mode - tbl_fea_mode
4610 short tbl_fea_mode - tbl_fea_mode
4611 short tbl_fea_mode - tbl_fea_mode
4612 short tbl_fea_mode - tbl_fea_mode
4613 short tbl_fea_mode - tbl_fea_mode
4614 short tbl_fea_mode - tbl_fea_mode
4615 short tbl_fea_mode - tbl_fea_mode
4617 short faddr_ind_a0 - tbl_fea_mode
4618 short faddr_ind_a1 - tbl_fea_mode
4619 short faddr_ind_a2 - tbl_fea_mode
4620 short faddr_ind_a3 - tbl_fea_mode
4621 short faddr_ind_a4 - tbl_fea_mode
4622 short faddr_ind_a5 - tbl_fea_mode
4623 short faddr_ind_a6 - tbl_fea_mode
4624 short faddr_ind_a7 - tbl_fea_mode
4626 short faddr_ind_p_a0 - tbl_fea_mode
4627 short faddr_ind_p_a1 - tbl_fea_mode
4628 short faddr_ind_p_a2 - tbl_fea_mode
4629 short faddr_ind_p_a3 - tbl_fea_mode
4630 short faddr_ind_p_a4 - tbl_fea_mode
4631 short faddr_ind_p_a5 - tbl_fea_mode
4632 short faddr_ind_p_a6 - tbl_fea_mode
4633 short faddr_ind_p_a7 - tbl_fea_mode
4635 short faddr_ind_m_a0 - tbl_fea_mode
4636 short faddr_ind_m_a1 - tbl_fea_mode
4637 short faddr_ind_m_a2 - tbl_fea_mode
4638 short faddr_ind_m_a3 - tbl_fea_mode
4639 short faddr_ind_m_a4 - tbl_fea_mode
4640 short faddr_ind_m_a5 - tbl_fea_mode
4641 short faddr_ind_m_a6 - tbl_fea_mode
4642 short faddr_ind_m_a7 - tbl_fea_mode
4644 short faddr_ind_disp_a0 - tbl_fea_mode
4645 short faddr_ind_disp_a1 - tbl_fea_mode
4646 short faddr_ind_disp_a2 - tbl_fea_mode
4647 short faddr_ind_disp_a3 - tbl_fea_mode
4648 short faddr_ind_disp_a4 - tbl_fea_mode
4649 short faddr_ind_disp_a5 - tbl_fea_mode
4650 short faddr_ind_disp_a6 - tbl_fea_mode
4651 short faddr_ind_disp_a7 - tbl_fea_mode
4653 short faddr_ind_ext - tbl_fea_mode
4654 short faddr_ind_ext - tbl_fea_mode
4655 short faddr_ind_ext - tbl_fea_mode
4656 short faddr_ind_ext - tbl_fea_mode
4657 short faddr_ind_ext - tbl_fea_mode
4658 short faddr_ind_ext - tbl_fea_mode
4659 short faddr_ind_ext - tbl_fea_mode
4660 short faddr_ind_ext - tbl_fea_mode
4662 short fabs_short - tbl_fea_mode
4663 short fabs_long - tbl_fea_mode
4664 short fpc_ind - tbl_fea_mode
4665 short fpc_ind_ext - tbl_fea_mode
4666 short tbl_fea_mode - tbl_fea_mode
4667 short tbl_fea_mode - tbl_fea_mode
4668 short tbl_fea_mode - tbl_fea_mode
4669 short tbl_fea_mode - tbl_fea_mode
4671 ###################################
4672 # Address register indirect: (An) #
4673 ###################################
4674 faddr_ind_a0:
4676 rts
4678 faddr_ind_a1:
4680 rts
4682 faddr_ind_a2:
4684 rts
4686 faddr_ind_a3:
4688 rts
4690 faddr_ind_a4:
4692 rts
4694 faddr_ind_a5:
4696 rts
4698 faddr_ind_a6:
4700 rts
4702 faddr_ind_a7:
4704 rts
4706 #####################################################
4707 # Address register indirect w/ postincrement: (An)+ #
4708 #####################################################
4709 faddr_ind_p_a0:
4715 rts
4717 faddr_ind_p_a1:
4723 rts
4725 faddr_ind_p_a2:
4731 rts
4733 faddr_ind_p_a3:
4739 rts
4741 faddr_ind_p_a4:
4747 rts
4749 faddr_ind_p_a5:
4755 rts
4757 faddr_ind_p_a6:
4763 rts
4765 faddr_ind_p_a7:
4773 rts
4775 ####################################################
4776 # Address register indirect w/ predecrement: -(An) #
4777 ####################################################
4778 faddr_ind_m_a0:
4783 rts
4785 faddr_ind_m_a1:
4790 rts
4792 faddr_ind_m_a2:
4797 rts
4799 faddr_ind_m_a3:
4804 rts
4806 faddr_ind_m_a4:
4811 rts
4813 faddr_ind_m_a5:
4818 rts
4820 faddr_ind_m_a6:
4825 rts
4827 faddr_ind_m_a7:
4834 rts
4836 ########################################################
4837 # Address register indirect w/ displacement: (d16, An) #
4838 ########################################################
4839 faddr_ind_disp_a0:
4842 bsr.l _imem_read_word
4850 rts
4852 faddr_ind_disp_a1:
4855 bsr.l _imem_read_word
4863 rts
4865 faddr_ind_disp_a2:
4868 bsr.l _imem_read_word
4876 rts
4878 faddr_ind_disp_a3:
4881 bsr.l _imem_read_word
4889 rts
4891 faddr_ind_disp_a4:
4894 bsr.l _imem_read_word
4902 rts
4904 faddr_ind_disp_a5:
4907 bsr.l _imem_read_word
4915 rts
4917 faddr_ind_disp_a6:
4920 bsr.l _imem_read_word
4928 rts
4930 faddr_ind_disp_a7:
4933 bsr.l _imem_read_word
4941 rts
4943 ########################################################################
4944 # Address register indirect w/ index(8-bit displacement): (d8, An, Xn) #
4945 # " " " w/ " (base displacement): (bd, An, Xn) #
4946 # Memory indirect postindexed: ([bd, An], Xn, od) #
4947 # Memory indirect preindexed: ([bd, An, Xn], od) #
4948 ########################################################################
4949 faddr_ind_ext:
4964 bne.w fcalc_mem_ind
4972 # count on fetch_dreg() not to alter a0...
4979 bne.b faii8_long
4981 faii8_long:
4993 rts
4995 ###########################
4996 # Absolute short: (XXX).W #
4997 ###########################
4998 fabs_short:
5007 rts
5009 ##########################
5010 # Absolute long: (XXX).L #
5011 ##########################
5012 fabs_long:
5021 rts
5023 #######################################################
5024 # Program counter indirect w/ displacement: (d16, PC) #
5025 #######################################################
5026 fpc_ind:
5038 # _imem_read_word() increased the extwptr by 2. need to adjust here.
5040 rts
5042 ##########################################################
5043 # PC indirect w/ index(8-bit displacement): (d8, PC, An) #
5044 # " " w/ " (base displacement): (bd, PC, An) #
5045 # PC memory indirect postindexed: ([bd, PC], Xn, od) #
5046 # PC memory indirect preindexed: ([bd, PC, Xn], od) #
5047 ##########################################################
5048 fpc_ind_ext:
5060 bne.w fcalc_mem_ind # calc memory indirect
5068 # count on fetch_dreg() not to alter a0...
5077 fpii8_long:
5089 rts
5091 # d2 = index
5092 # d3 = base
5093 # d4 = od
5094 # d5 = extword
5095 fcalc_mem_ind:
5097 beq.b fcalc_index
5105 bra.b fbase_supp_ck
5107 # index:
5108 fcalc_index:
5111 bsr.l fetch_dreg
5119 bne.b fno_ext
5122 fno_ext:
5126 # base address (passed as parameter in d3):
5127 # we clear the value here if it should actually be suppressed.
5128 fbase_supp_ck:
5130 beq.b fno_base_sup
5133 # base displacement:
5134 fno_base_sup:
5136 # beq.l fmovm_error # if (size == 0) it's reserved
5139 blt.b fno_bd
5140 beq.b fget_word_bd
5144 bsr.l _imem_read_long
5149 bra.b fchk_ind
5151 fget_word_bd:
5154 bsr.l _imem_read_word
5161 fchk_ind:
5164 # outer displacement:
5165 fno_bd:
5167 beq.w faii_bd
5170 blt.b fnull_od
5171 beq.b fword_od
5175 bsr.l _imem_read_long
5180 bra.b fadd_them
5182 fword_od:
5185 bsr.l _imem_read_word
5191 bra.b fadd_them
5193 fnull_od:
5196 fadd_them:
5200 beq.b fpre_indexed
5203 bsr.l _dmem_read_long
5206 bne.w fcea_err # yes
5210 bra.b fdone_ea
5212 fpre_indexed:
5215 bsr.l _dmem_read_long
5218 bne.w fcea_err # yes
5221 bra.b fdone_ea
5223 faii_bd:
5226 fdone_ea:
5230 rts
5232 #########################################################
5233 fcea_err:
5238 bra.l iea_dacc
5240 fcea_iacc:
5242 bra.l iea_iacc
5244 fmovm_out_err:
5245 bsr.l restore
5247 bra.b fmovm_err
5249 fmovm_in_err:
5250 bsr.l restore
5253 fmovm_err:
5255 bra.l iea_dacc
5257 #########################################################################
5258 # XDEF **************************************************************** #
5259 # fmovm_ctrl(): emulate fmovm.l of control registers instr #
5260 # #
5261 # XREF **************************************************************** #
5262 # _imem_read_long() - read longword from memory #
5263 # iea_iacc() - _imem_read_long() failed; error recovery #
5264 # #
5265 # INPUT *************************************************************** #
5266 # None #
5267 # #
5268 # OUTPUT ************************************************************** #
5269 # If _imem_read_long() doesn't fail: #
5270 # USER_FPCR(a6) = new FPCR value #
5271 # USER_FPSR(a6) = new FPSR value #
5272 # USER_FPIAR(a6) = new FPIAR value #
5273 # #
5274 # ALGORITHM *********************************************************** #
5275 # Decode the instruction type by looking at the extension word #
5276 # in order to see how many control registers to fetch from memory. #
5277 # Fetch them using _imem_read_long(). If this fetch fails, exit through #
5278 # the special access error exit handler iea_iacc(). #
5279 # #
5280 # Instruction word decoding: #
5281 # #
5282 # fmovem.l #<data>, {FPIAR&|FPCR&|FPSR} #
5283 # #
5284 # WORD1 WORD2 #
5285 # 1111 0010 00 111100 100$ $$00 0000 0000 #
5286 # #
5287 # $$$ (100): FPCR #
5288 # (010): FPSR #
5289 # (001): FPIAR #
5290 # (000): FPIAR #
5291 # #
5292 #########################################################################
5294 global fmovm_ctrl
5295 fmovm_ctrl:
5298 beq.w fctrl_in_7 # yes
5300 beq.w fctrl_in_6 # yes
5304 # fmovem.l #<data>, fpsr/fpiar
5305 fctrl_in_3:
5322 rts
5324 # fmovem.l #<data>, fpcr/fpiar
5325 fctrl_in_5:
5342 rts
5344 # fmovem.l #<data>, fpcr/fpsr
5345 fctrl_in_6:
5362 rts
5364 # fmovem.l #<data>, fpcr/fpsr/fpiar
5365 fctrl_in_7:
5390 rts
5392 ##########################################################################
5394 #########################################################################
5395 # XDEF **************************************************************** #
5396 # addsub_scaler2(): scale inputs to fadd/fsub such that no #
5397 # OVFL/UNFL exceptions will result #
5398 # #
5399 # XREF **************************************************************** #
5400 # norm() - normalize mantissa after adjusting exponent #
5401 # #
5402 # INPUT *************************************************************** #
5403 # FP_SRC(a6) = fp op1(src) #
5404 # FP_DST(a6) = fp op2(dst) #
5405 # #
5406 # OUTPUT ************************************************************** #
5407 # FP_SRC(a6) = fp op1 scaled(src) #
5408 # FP_DST(a6) = fp op2 scaled(dst) #
5409 # d0 = scale amount #
5410 # #
5411 # ALGORITHM *********************************************************** #
5412 # If the DST exponent is > the SRC exponent, set the DST exponent #
5413 # equal to 0x3fff and scale the SRC exponent by the value that the #
5414 # DST exponent was scaled by. If the SRC exponent is greater or equal, #
5415 # do the opposite. Return this scale factor in d0. #
5416 # If the two exponents differ by > the number of mantissa bits #
5417 # plus two, then set the smallest exponent to a very small value as a #
5418 # quick shortcut. #
5419 # #
5420 #########################################################################
5422 global addsub_scaler2
5423 addsub_scaler2:
5439 bge.l src_exp_ge2
5441 # dst exp is > src exp; scale dst to exp = 0x3fff
5442 dst_exp_gt2:
5443 bsr.l scale_to_zero_dst
5447 bne.b cmpexp12
5454 cmpexp12:
5459 bge.b quick_scale12
5469 rts
5471 quick_scale12:
5476 rts
5478 # src exp is >= dst exp; scale src to exp = 0x3fff
5479 src_exp_ge2:
5480 bsr.l scale_to_zero_src
5484 bne.b cmpexp22
5490 cmpexp22:
5495 bge.b quick_scale22
5505 rts
5507 quick_scale22:
5512 rts
5514 ##########################################################################
5516 #########################################################################
5517 # XDEF **************************************************************** #
5518 # scale_to_zero_src(): scale the exponent of extended precision #
5519 # value at FP_SCR0(a6). #
5520 # #
5521 # XREF **************************************************************** #
5522 # norm() - normalize the mantissa if the operand was a DENORM #
5523 # #
5524 # INPUT *************************************************************** #
5525 # FP_SCR0(a6) = extended precision operand to be scaled #
5526 # #
5527 # OUTPUT ************************************************************** #
5528 # FP_SCR0(a6) = scaled extended precision operand #
5529 # d0 = scale value #
5530 # #
5531 # ALGORITHM *********************************************************** #
5532 # Set the exponent of the input operand to 0x3fff. Save the value #
5533 # of the difference between the original and new exponent. Then, #
5534 # normalize the operand if it was a DENORM. Add this normalization #
5535 # value to the previous value. Return the result. #
5536 # #
5537 #########################################################################
5539 global scale_to_zero_src
5540 scale_to_zero_src:
5554 stzs_norm:
5558 rts
5560 stzs_denorm:
5567 ###
5569 #########################################################################
5570 # XDEF **************************************************************** #
5571 # scale_sqrt(): scale the input operand exponent so a subsequent #
5572 # fsqrt operation won't take an exception. #
5573 # #
5574 # XREF **************************************************************** #
5575 # norm() - normalize the mantissa if the operand was a DENORM #
5576 # #
5577 # INPUT *************************************************************** #
5578 # FP_SCR0(a6) = extended precision operand to be scaled #
5579 # #
5580 # OUTPUT ************************************************************** #
5581 # FP_SCR0(a6) = scaled extended precision operand #
5582 # d0 = scale value #
5583 # #
5584 # ALGORITHM *********************************************************** #
5585 # If the input operand is a DENORM, normalize it. #
5586 # If the exponent of the input operand is even, set the exponent #
5587 # to 0x3ffe and return a scale factor of "(exp-0x3ffe)/2". If the #
5588 # exponent of the input operand is off, set the exponent to ox3fff and #
5589 # return a scale factor of "(exp-0x3fff)/2". #
5590 # #
5591 #########################################################################
5593 global scale_sqrt
5594 scale_sqrt:
5604 beq.b ss_norm_even
5611 rts
5613 ss_norm_even:
5619 rts
5621 ss_denorm:
5626 beq.b ss_denorm_even
5632 rts
5634 ss_denorm_even:
5639 rts
5641 ###
5643 #########################################################################
5644 # XDEF **************************************************************** #
5645 # scale_to_zero_dst(): scale the exponent of extended precision #
5646 # value at FP_SCR1(a6). #
5647 # #
5648 # XREF **************************************************************** #
5649 # norm() - normalize the mantissa if the operand was a DENORM #
5650 # #
5651 # INPUT *************************************************************** #
5652 # FP_SCR1(a6) = extended precision operand to be scaled #
5653 # #
5654 # OUTPUT ************************************************************** #
5655 # FP_SCR1(a6) = scaled extended precision operand #
5656 # d0 = scale value #
5657 # #
5658 # ALGORITHM *********************************************************** #
5659 # Set the exponent of the input operand to 0x3fff. Save the value #
5660 # of the difference between the original and new exponent. Then, #
5661 # normalize the operand if it was a DENORM. Add this normalization #
5662 # value to the previous value. Return the result. #
5663 # #
5664 #########################################################################
5666 global scale_to_zero_dst
5667 scale_to_zero_dst:
5681 stzd_norm:
5684 rts
5686 stzd_denorm:
5693 ##########################################################################
5695 #########################################################################
5696 # XDEF **************************************************************** #
5697 # res_qnan(): return default result w/ QNAN operand for dyadic #
5698 # res_snan(): return default result w/ SNAN operand for dyadic #
5699 # res_qnan_1op(): return dflt result w/ QNAN operand for monadic #
5700 # res_snan_1op(): return dflt result w/ SNAN operand for monadic #
5701 # #
5702 # XREF **************************************************************** #
5703 # None #
5704 # #
5705 # INPUT *************************************************************** #
5706 # FP_SRC(a6) = pointer to extended precision src operand #
5707 # FP_DST(a6) = pointer to extended precision dst operand #
5708 # #
5709 # OUTPUT ************************************************************** #
5710 # fp0 = default result #
5711 # #
5712 # ALGORITHM *********************************************************** #
5713 # If either operand (but not both operands) of an operation is a #
5714 # nonsignalling NAN, then that NAN is returned as the result. If both #
5715 # operands are nonsignalling NANs, then the destination operand #
5716 # nonsignalling NAN is returned as the result. #
5717 # If either operand to an operation is a signalling NAN (SNAN), #
5718 # then, the SNAN bit is set in the FPSR EXC byte. If the SNAN trap #
5719 # enable bit is set in the FPCR, then the trap is taken and the #
5720 # destination is not modified. If the SNAN trap enable bit is not set, #
5721 # then the SNAN is converted to a nonsignalling NAN (by setting the #
5722 # SNAN bit in the operand to one), and the operation continues as #
5723 # described in the preceding paragraph, for nonsignalling NANs. #
5724 # Make sure the appropriate FPSR bits are set before exiting. #
5725 # #
5726 #########################################################################
5728 global res_qnan
5729 global res_snan
5730 res_qnan:
5731 res_snan:
5733 beq.b dst_snan2
5735 beq.b dst_qnan2
5736 src_nan:
5738 beq.b src_qnan2
5739 global res_snan_1op
5740 res_snan_1op:
5741 src_snan2:
5745 bra.b nan_comp
5746 global res_qnan_1op
5747 res_qnan_1op:
5748 src_qnan2:
5751 bra.b nan_comp
5752 dst_snan2:
5756 bra.b nan_comp
5757 dst_qnan2:
5760 bne nan_done
5762 nan_done:
5764 nan_comp:
5766 beq.b nan_not_neg
5768 nan_not_neg:
5770 rts
5772 #########################################################################
5773 # XDEF **************************************************************** #
5774 # res_operr(): return default result during operand error #
5775 # #
5776 # XREF **************************************************************** #
5777 # None #
5778 # #
5779 # INPUT *************************************************************** #
5780 # None #
5781 # #
5782 # OUTPUT ************************************************************** #
5783 # fp0 = default operand error result #
5784 # #
5785 # ALGORITHM *********************************************************** #
5786 # An nonsignalling NAN is returned as the default result when #
5787 # an operand error occurs for the following cases: #
5788 # #
5789 # Multiply: (Infinity x Zero) #
5790 # Divide : (Zero / Zero) || (Infinity / Infinity) #
5791 # #
5792 #########################################################################
5794 global res_operr
5795 res_operr:
5798 rts
5800 nan_return:
5803 #########################################################################
5804 # XDEF **************************************************************** #
5805 # _denorm(): denormalize an intermediate result #
5806 # #
5807 # XREF **************************************************************** #
5808 # None #
5809 # #
5810 # INPUT *************************************************************** #
5811 # a0 = points to the operand to be denormalized #
5812 # (in the internal extended format) #
5813 # #
5814 # d0 = rounding precision #
5815 # #
5816 # OUTPUT ************************************************************** #
5817 # a0 = pointer to the denormalized result #
5818 # (in the internal extended format) #
5819 # #
5820 # d0 = guard,round,sticky #
5821 # #
5822 # ALGORITHM *********************************************************** #
5823 # According to the exponent underflow threshold for the given #
5824 # precision, shift the mantissa bits to the right in order raise the #
5825 # exponent of the operand to the threshold value. While shifting the #
5826 # mantissa bits right, maintain the value of the guard, round, and #
5827 # sticky bits. #
5828 # other notes: #
5829 # (1) _denorm() is called by the underflow routines #
5830 # (2) _denorm() does NOT affect the status register #
5831 # #
5832 #########################################################################
5834 #
5835 # table of exponent threshold values for each precision
5836 #
5837 tbl_thresh:
5838 short 0x0
5839 short sgl_thresh
5840 short dbl_thresh
5842 global _denorm
5843 _denorm:
5844 #
5845 # Load the exponent threshold for the precision selected and check
5846 # to see if (threshold - exponent) is > 65 in which case we can
5847 # simply calculate the sticky bit and zero the mantissa. otherwise
5848 # we have to call the denormalization routine.
5849 #
5862 denorm_call:
5864 rts
5866 #
5867 # all bit would have been shifted off during the denorm so simply
5868 # calculate if the sticky should be set and clear the entire mantissa.
5869 #
5870 denorm_set_stky:
5875 rts
5877 # #
5878 # dnrm_lp(): normalize exponent/mantissa to specified threshhold #
5879 # #
5880 # INPUT: #
5881 # %a0 : points to the operand to be denormalized #
5882 # %d0{31:29} : initial guard,round,sticky #
5883 # %d1{15:0} : denormalization threshold #
5884 # OUTPUT: #
5885 # %a0 : points to the denormalized operand #
5886 # %d0{31:29} : final guard,round,sticky #
5887 # #
5889 # *** Local Equates *** #
5893 global dnrm_lp
5894 dnrm_lp:
5896 #
5897 # make a copy of FTEMP_LO and place the g,r,s bits directly after it
5898 # in memory so as to make the bitfield extraction for denormalization easier.
5899 #
5903 #
5904 # check to see how much less than the underflow threshold the operand
5905 # exponent is.
5906 #
5914 bra.w case_3 # (d1 >= 64)
5916 #
5917 # No normalization necessary
5918 #
5919 dnrm_no_lp:
5921 rts
5923 #
5924 # case (0<d1<32)
5925 #
5926 # %d0 = denorm threshold
5927 # %d1 = "n" = amt to shift
5928 #
5929 # ---------------------------------------------------------
5930 # | FTEMP_HI | FTEMP_LO |grs000.........000|
5931 # ---------------------------------------------------------
5932 # <-(32 - n)-><-(n)-><-(32 - n)-><-(n)-><-(32 - n)-><-(n)->
5933 # \ \ \ \
5934 # \ \ \ \
5935 # \ \ \ \
5936 # \ \ \ \
5937 # \ \ \ \
5938 # \ \ \ \
5939 # \ \ \ \
5940 # \ \ \ \
5941 # <-(n)-><-(32 - n)-><------(32)-------><------(32)------->
5942 # ---------------------------------------------------------
5943 # |0.....0| NEW_HI | NEW_FTEMP_LO |grs |
5944 # ---------------------------------------------------------
5945 #
5946 case_1:
5958 case1_extract:
5970 case1_sticky_clear:
5973 rts
5975 #
5976 # case (32<=d1<64)
5977 #
5978 # %d0 = denorm threshold
5979 # %d1 = "n" = amt to shift
5980 #
5981 # ---------------------------------------------------------
5982 # | FTEMP_HI | FTEMP_LO |grs000.........000|
5983 # ---------------------------------------------------------
5984 # <-(32 - n)-><-(n)-><-(32 - n)-><-(n)-><-(32 - n)-><-(n)->
5985 # \ \ \
5986 # \ \ \
5987 # \ \ -------------------
5988 # \ -------------------- \
5989 # ------------------- \ \
5990 # \ \ \
5991 # \ \ \
5992 # \ \ \
5993 # <-------(32)------><-(n)-><-(32 - n)-><------(32)------->
5994 # ---------------------------------------------------------
5995 # |0...............0|0....0| NEW_LO |grs |
5996 # ---------------------------------------------------------
5997 #
5998 case_2:
6006 # subtle step here; or in the g,r,s at the bottom of FTEMP_LO to minimize
6007 # the number of bits to check for the sticky detect.
6008 # it only plays a role in shift amounts of 61-63.
6021 bra.b case2_end
6023 case2_set_sticky:
6027 case2_end:
6033 rts
6035 #
6036 # case (d1>=64)
6037 #
6038 # %d0 = denorm threshold
6039 # %d1 = amt to shift
6040 #
6041 case_3:
6048 #
6049 # case (d1>65)
6050 #
6051 # Shift value is > 65 and out of range. All bits are shifted off.
6052 # Return a zero mantissa with the sticky bit set
6053 #
6057 rts
6059 #
6060 # case (d1 == 64)
6061 #
6062 # ---------------------------------------------------------
6063 # | FTEMP_HI | FTEMP_LO |grs000.........000|
6064 # ---------------------------------------------------------
6065 # <-------(32)------>
6066 # \ \
6067 # \ \
6068 # \ \
6069 # \ ------------------------------
6070 # ------------------------------- \
6071 # \ \
6072 # \ \
6073 # \ \
6074 # <-------(32)------>
6075 # ---------------------------------------------------------
6076 # |0...............0|0................0|grs |
6077 # ---------------------------------------------------------
6078 #
6079 case3_64:
6085 bra.b case3_complete
6087 #
6088 # case (d1 == 65)
6089 #
6090 # ---------------------------------------------------------
6091 # | FTEMP_HI | FTEMP_LO |grs000.........000|
6092 # ---------------------------------------------------------
6093 # <-------(32)------>
6094 # \ \
6095 # \ \
6096 # \ \
6097 # \ ------------------------------
6098 # -------------------------------- \
6099 # \ \
6100 # \ \
6101 # \ \
6102 # <-------(31)----->
6103 # ---------------------------------------------------------
6104 # |0...............0|0................0|0rs |
6105 # ---------------------------------------------------------
6106 #
6107 case3_65:
6113 case3_complete:
6114 # last operation done was an "and" of the bits shifted off so the condition
6115 # codes are already set so branch accordingly.
6122 #
6123 # no bits were shifted off so don't set the sticky bit.
6124 # the guard and
6125 # the entire mantissa is zero.
6126 #
6129 rts
6131 #
6132 # some bits were shifted off so set the sticky bit.
6133 # the entire mantissa is zero.
6134 #
6135 case3_set_sticky:
6139 rts
6141 #########################################################################
6142 # XDEF **************************************************************** #
6143 # _round(): round result according to precision/mode #
6144 # #
6145 # XREF **************************************************************** #
6146 # None #
6147 # #
6148 # INPUT *************************************************************** #
6149 # a0 = ptr to input operand in internal extended format #
6150 # d1(hi) = contains rounding precision: #
6151 # ext = $0000xxxx #
6152 # sgl = $0004xxxx #
6153 # dbl = $0008xxxx #
6154 # d1(lo) = contains rounding mode: #
6155 # RN = $xxxx0000 #
6156 # RZ = $xxxx0001 #
6157 # RM = $xxxx0002 #
6158 # RP = $xxxx0003 #
6159 # d0{31:29} = contains the g,r,s bits (extended) #
6160 # #
6161 # OUTPUT ************************************************************** #
6162 # a0 = pointer to rounded result #
6163 # #
6164 # ALGORITHM *********************************************************** #
6165 # On return the value pointed to by a0 is correctly rounded, #
6166 # a0 is preserved and the g-r-s bits in d0 are cleared. #
6167 # The result is not typed - the tag field is invalid. The #
6168 # result is still in the internal extended format. #
6169 # #
6170 # The INEX bit of USER_FPSR will be set if the rounded result was #
6171 # inexact (i.e. if any of the g-r-s bits were set). #
6172 # #
6173 #########################################################################
6175 global _round
6176 _round:
6177 #
6178 # ext_grs() looks at the rounding precision and sets the appropriate
6179 # G,R,S bits.
6180 # If (G,R,S == 0) then result is exact and round is done, else set
6181 # the inex flag in status reg and continue.
6182 #
6186 beq.w truncate # yes; round is complete
6190 #
6191 # Use rounding mode as an index into a jump table for these modes.
6192 # All of the following assumes grs != 0.
6193 #
6197 tbl_mode:
6198 short rnd_near - tbl_mode
6200 short rnd_mnus - tbl_mode
6201 short rnd_plus - tbl_mode
6203 #################################################################
6204 # ROUND PLUS INFINITY #
6205 # #
6206 # If sign of fp number = 0 (positive), then add 1 to l. #
6207 #################################################################
6208 rnd_plus:
6210 bmi.w truncate # if positive then truncate
6216 beq.w add_sgl # yes
6217 bgt.w add_dbl # no; it's dbl
6218 bra.w add_ext # no; it's ext
6220 #################################################################
6221 # ROUND MINUS INFINITY #
6222 # #
6223 # If sign of fp number = 1 (negative), then add 1 to l. #
6224 #################################################################
6225 rnd_mnus:
6227 bpl.w truncate # if negative then truncate
6233 beq.w add_sgl # yes
6234 bgt.w add_dbl # no; it's dbl
6235 bra.w add_ext # no; it's ext
6237 #################################################################
6238 # ROUND NEAREST #
6239 # #
6240 # If (g=1), then add 1 to l and if (r=s=0), then clear l #
6241 # Note that this will round to even in case of a tie. #
6242 #################################################################
6243 rnd_near:
6245 bcc.w truncate # if (g=1) then
6250 beq.w add_sgl # yes
6251 bgt.w add_dbl # no; it's dbl
6252 bra.w add_ext # no; it's ext
6254 # *** LOCAL EQUATES ***
6258 #########################
6259 # ADD SINGLE #
6260 #########################
6261 add_sgl:
6267 scc_clr:
6269 bne.b sgl_done
6271 sgl_done:
6274 rts
6276 #########################
6277 # ADD EXTENDED #
6278 #########################
6279 add_ext:
6283 bcc.b xcc_clr
6289 xcc_clr:
6291 bne.b add_ext_done
6293 add_ext_done:
6294 rts
6296 #########################
6297 # ADD DOUBLE #
6298 #########################
6299 add_dbl:
6310 dcc_clr:
6312 bne.b dbl_done
6315 dbl_done:
6317 rts
6319 ###########################
6320 # Truncate all other bits #
6321 ###########################
6322 truncate:
6326 beq.w sgl_done # yes
6328 rts # no; it's ext
6331 #
6332 # ext_grs(): extract guard, round and sticky bits according to
6333 # rounding precision.
6334 #
6335 # INPUT
6336 # d0 = extended precision g,r,s (in d0{31:29})
6337 # d1 = {PREC,ROUND}
6338 # OUTPUT
6339 # d0{31:29} = guard, round, sticky
6340 #
6341 # The ext_grs extract the guard/round/sticky bits according to the
6342 # selected rounding precision. It is called by the round subroutine
6343 # only. All registers except d0 are kept intact. d0 becomes an
6344 # updated guard,round,sticky in d0{31:29}
6345 #
6346 # Notes: the ext_grs uses the round PREC, and therefore has to swap d1
6347 # prior to usage, and needs to restore d1 to original. this
6348 # routine is tightly tied to the round routine and not meant to
6349 # uphold standard subroutine calling practices.
6350 #
6352 ext_grs:
6357 #
6358 # %d0 actually already hold g,r,s since _round() had it before calling
6359 # this function. so, as long as we don't disturb it, we are "returning" it.
6360 #
6361 ext_grs_ext:
6363 rts
6365 ext_grs_not_ext:
6371 #
6372 # sgl:
6373 # 96 64 40 32 0
6374 # -----------------------------------------------------
6375 # | EXP |XXXXXXX| |xx | |grs|
6376 # -----------------------------------------------------
6377 # <--(24)--->nn\ /
6378 # ee ---------------------
6379 # ww |
6380 # v
6381 # gr new sticky
6382 #
6383 ext_grs_sgl:
6396 #
6397 # dbl:
6398 # 96 64 32 11 0
6399 # -----------------------------------------------------
6400 # | EXP |XXXXXXX| | |xx |grs|
6401 # -----------------------------------------------------
6402 # nn\ /
6403 # ee -------
6404 # ww |
6405 # v
6406 # gr new sticky
6407 #
6408 ext_grs_dbl:
6419 ext_grs_st_stky:
6421 ext_grs_end_sd:
6427 rts
6429 #########################################################################
6430 # norm(): normalize the mantissa of an extended precision input. the #
6431 # input operand should not be normalized already. #
6432 # #
6433 # XDEF **************************************************************** #
6434 # norm() #
6435 # #
6436 # XREF **************************************************************** #
6437 # none #
6438 # #
6439 # INPUT *************************************************************** #
6440 # a0 = pointer fp extended precision operand to normalize #
6441 # #
6442 # OUTPUT ************************************************************** #
6443 # d0 = number of bit positions the mantissa was shifted #
6444 # a0 = the input operand's mantissa is normalized; the exponent #
6445 # is unchanged. #
6446 # #
6447 #########################################################################
6448 global norm
6449 norm:
6459 norm_hi:
6474 rts
6476 norm_lo:
6489 rts
6491 #########################################################################
6492 # unnorm_fix(): - changes an UNNORM to one of NORM, DENORM, or ZERO #
6493 # - returns corresponding optype tag #
6494 # #
6495 # XDEF **************************************************************** #
6496 # unnorm_fix() #
6497 # #
6498 # XREF **************************************************************** #
6499 # norm() - normalize the mantissa #
6500 # #
6501 # INPUT *************************************************************** #
6502 # a0 = pointer to unnormalized extended precision number #
6503 # #
6504 # OUTPUT ************************************************************** #
6505 # d0 = optype tag - is corrected to one of NORM, DENORM, or ZERO #
6506 # a0 = input operand has been converted to a norm, denorm, or #
6507 # zero; both the exponent and mantissa are changed. #
6508 # #
6509 #########################################################################
6511 global unnorm_fix
6512 unnorm_fix:
6516 #
6517 # hi(man) is all zeroes so see if any bits in lo(man) are set
6518 #
6519 unnorm_chk_lo:
6521 beq.w unnorm_zero # yes
6525 #
6526 # d0 = # shifts needed for complete normalization
6527 #
6528 unnorm_shift:
6536 #
6537 # exponent would not go < 0. therefore, number stays normalized
6538 #
6548 rts
6550 #
6551 # exponent would go < 0, so only denormalize until exp = 0
6552 #
6553 unnorm_nrm_zero:
6567 rts
6569 #
6570 # only mantissa bits set are in lo(man)
6571 #
6572 unnorm_nrm_zero_lrg:
6584 rts
6586 #
6587 # whole mantissa is zero so this UNNORM is actually a zero
6588 #
6589 unnorm_zero:
6593 rts
6595 #########################################################################
6596 # XDEF **************************************************************** #
6597 # set_tag_x(): return the optype of the input ext fp number #
6598 # #
6599 # XREF **************************************************************** #
6600 # None #
6601 # #
6602 # INPUT *************************************************************** #
6603 # a0 = pointer to extended precision operand #
6604 # #
6605 # OUTPUT ************************************************************** #
6606 # d0 = value of type tag #
6607 # one of: NORM, INF, QNAN, SNAN, DENORM, UNNORM, ZERO #
6608 # #
6609 # ALGORITHM *********************************************************** #
6610 # Simply test the exponent, j-bit, and mantissa values to #
6611 # determine the type of operand. #
6612 # If it's an unnormalized zero, alter the operand and force it #
6613 # to be a normal zero. #
6614 # #
6615 #########################################################################
6617 global set_tag_x
6618 set_tag_x:
6622 beq.b inf_or_nan_x
6623 not_inf_or_nan_x:
6625 beq.b not_norm_x
6626 is_norm_x:
6628 rts
6629 not_norm_x:
6631 bne.b is_unnorm_x
6632 not_unnorm_x:
6634 bne.b is_denorm_x
6636 bne.b is_denorm_x
6637 is_zero_x:
6639 rts
6640 is_denorm_x:
6642 rts
6643 # must distinguish now "Unnormalized zeroes" which we
6644 # must convert to zero.
6645 is_unnorm_x:
6647 bne.b is_unnorm_reg_x
6649 bne.b is_unnorm_reg_x
6650 # it's an "unnormalized zero". let's convert it to an actual zero...
6653 rts
6654 is_unnorm_reg_x:
6656 rts
6657 inf_or_nan_x:
6659 bne.b is_nan_x
6662 bne.b is_nan_x
6663 is_inf_x:
6665 rts
6666 is_nan_x:
6668 beq.b is_snan_x
6670 rts
6671 is_snan_x:
6673 rts
6675 #########################################################################
6676 # XDEF **************************************************************** #
6677 # set_tag_d(): return the optype of the input dbl fp number #
6678 # #
6679 # XREF **************************************************************** #
6680 # None #
6681 # #
6682 # INPUT *************************************************************** #
6683 # a0 = points to double precision operand #
6684 # #
6685 # OUTPUT ************************************************************** #
6686 # d0 = value of type tag #
6687 # one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
6688 # #
6689 # ALGORITHM *********************************************************** #
6690 # Simply test the exponent, j-bit, and mantissa values to #
6691 # determine the type of operand. #
6692 # #
6693 #########################################################################
6695 global set_tag_d
6696 set_tag_d:
6701 beq.b zero_or_denorm_d
6704 beq.b inf_or_nan_d
6706 is_norm_d:
6708 rts
6709 zero_or_denorm_d:
6711 bne is_denorm_d
6713 bne is_denorm_d
6714 is_zero_d:
6716 rts
6717 is_denorm_d:
6719 rts
6720 inf_or_nan_d:
6722 bne is_nan_d
6724 bne is_nan_d
6725 is_inf_d:
6727 rts
6728 is_nan_d:
6730 bne is_qnan_d
6731 is_snan_d:
6733 rts
6734 is_qnan_d:
6736 rts
6738 #########################################################################
6739 # XDEF **************************************************************** #
6740 # set_tag_s(): return the optype of the input sgl fp number #
6741 # #
6742 # XREF **************************************************************** #
6743 # None #
6744 # #
6745 # INPUT *************************************************************** #
6746 # a0 = pointer to single precision operand #
6747 # #
6748 # OUTPUT ************************************************************** #
6749 # d0 = value of type tag #
6750 # one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
6751 # #
6752 # ALGORITHM *********************************************************** #
6753 # Simply test the exponent, j-bit, and mantissa values to #
6754 # determine the type of operand. #
6755 # #
6756 #########################################################################
6758 global set_tag_s
6759 set_tag_s:
6764 beq.b zero_or_denorm_s
6767 beq.b inf_or_nan_s
6769 is_norm_s:
6771 rts
6772 zero_or_denorm_s:
6774 bne is_denorm_s
6775 is_zero_s:
6777 rts
6778 is_denorm_s:
6780 rts
6781 inf_or_nan_s:
6783 bne is_nan_s
6784 is_inf_s:
6786 rts
6787 is_nan_s:
6789 bne is_qnan_s
6790 is_snan_s:
6792 rts
6793 is_qnan_s:
6795 rts
6797 #########################################################################
6798 # XDEF **************************************************************** #
6799 # unf_res(): routine to produce default underflow result of a #
6800 # scaled extended precision number; this is used by #
6801 # fadd/fdiv/fmul/etc. emulation routines. #
6802 # unf_res4(): same as above but for fsglmul/fsgldiv which use #
6803 # single round prec and extended prec mode. #
6804 # #
6805 # XREF **************************************************************** #
6806 # _denorm() - denormalize according to scale factor #
6807 # _round() - round denormalized number according to rnd prec #
6808 # #
6809 # INPUT *************************************************************** #
6810 # a0 = pointer to extended precison operand #
6811 # d0 = scale factor #
6812 # d1 = rounding precision/mode #
6813 # #
6814 # OUTPUT ************************************************************** #
6815 # a0 = pointer to default underflow result in extended precision #
6816 # d0.b = result FPSR_cc which caller may or may not want to save #
6817 # #
6818 # ALGORITHM *********************************************************** #
6819 # Convert the input operand to "internal format" which means the #
6820 # exponent is extended to 16 bits and the sign is stored in the unused #
6821 # portion of the extended precison operand. Denormalize the number #
6822 # according to the scale factor passed in d0. Then, round the #
6823 # denormalized result. #
6824 # Set the FPSR_exc bits as appropriate but return the cc bits in #
6825 # d0 in case the caller doesn't want to save them (as is the case for #
6826 # fmove out). #
6827 # unf_res4() for fsglmul/fsgldiv forces the denorm to extended #
6828 # precision and the rounding mode to single. #
6829 # #
6830 #########################################################################
6831 global unf_res
6832 unf_res:
6854 swap %d1
6862 # result is now rounded properly. convert back to normal format
6869 # the number may have become zero after rounding. set ccodes accordingly.
6870 unf_res_chkifzero:
6876 # bset &z_bit, FPSR_CC(%a6) # yes; set zero ccode bit
6879 unf_res_cont:
6881 #
6882 # can inex1 also be set along with unfl and inex2???
6883 #
6884 # we know that underflow has occurred. aunfl should be set if INEX2 is also set.
6885 #
6890 unf_res_end:
6892 rts
6894 # unf_res() for fsglmul() and fsgldiv().
6895 global unf_res4
6896 unf_res4:
6914 swap %d1
6922 # result is now rounded properly. convert back to normal format
6929 # the number may have become zero after rounding. set ccodes accordingly.
6930 unf_res4_chkifzero:
6936 # bset &z_bit,FPSR_CC(%a6) # yes; set zero ccode bit
6939 unf_res4_cont:
6941 #
6942 # can inex1 also be set along with unfl and inex2???
6943 #
6944 # we know that underflow has occurred. aunfl should be set if INEX2 is also set.
6945 #
6950 unf_res4_end:
6952 rts
6954 #########################################################################
6955 # XDEF **************************************************************** #
6956 # ovf_res(): routine to produce the default overflow result of #
6957 # an overflowing number. #
6958 # ovf_res2(): same as above but the rnd mode/prec are passed #
6959 # differently. #
6960 # #
6961 # XREF **************************************************************** #
6962 # none #
6963 # #
6964 # INPUT *************************************************************** #
6965 # d1.b = '-1' => (-); '0' => (+) #
6966 # ovf_res(): #
6967 # d0 = rnd mode/prec #
6968 # ovf_res2(): #
6969 # hi(d0) = rnd prec #
6970 # lo(d0) = rnd mode #
6971 # #
6972 # OUTPUT ************************************************************** #
6973 # a0 = points to extended precision result #
6974 # d0.b = condition code bits #
6975 # #
6976 # ALGORITHM *********************************************************** #
6977 # The default overflow result can be determined by the sign of #
6978 # the result and the rounding mode/prec in effect. These bits are #
6979 # concatenated together to create an index into the default result #
6980 # table. A pointer to the correct result is returned in a0. The #
6981 # resulting condition codes are returned in d0 in case the caller #
6982 # doesn't want FPSR_cc altered (as is the case for fmove out). #
6983 # #
6984 #########################################################################
6986 global ovf_res
6987 ovf_res:
6993 bra.b ovf_res_load
6995 global ovf_res2
6996 ovf_res2:
6999 swap %d0
7004 #
7005 # use the rounding mode, precision, and result sign as in index into the
7006 # two tables below to fetch the default result and the result ccodes.
7007 #
7008 ovf_res_load:
7012 rts
7014 tbl_ovfl_cc:
7023 tbl_ovfl_result:
7059 #########################################################################
7060 # XDEF **************************************************************** #
7061 # fout(): move from fp register to memory or data register #
7062 # #
7063 # XREF **************************************************************** #
7064 # _round() - needed to create EXOP for sgl/dbl precision #
7065 # norm() - needed to create EXOP for extended precision #
7066 # ovf_res() - create default overflow result for sgl/dbl precision#
7067 # unf_res() - create default underflow result for sgl/dbl prec. #
7068 # dst_dbl() - create rounded dbl precision result. #
7069 # dst_sgl() - create rounded sgl precision result. #
7070 # fetch_dreg() - fetch dynamic k-factor reg for packed. #
7071 # bindec() - convert FP binary number to packed number. #
7072 # _mem_write() - write data to memory. #
7073 # _mem_write2() - write data to memory unless supv mode -(a7) exc.#
7074 # _dmem_write_{byte,word,long}() - write data to memory. #
7075 # store_dreg_{b,w,l}() - store data to data register file. #
7076 # facc_out_{b,w,l,d,x}() - data access error occurred. #
7077 # #
7078 # INPUT *************************************************************** #
7079 # a0 = pointer to extended precision source operand #
7080 # d0 = round prec,mode #
7081 # #
7082 # OUTPUT ************************************************************** #
7083 # fp0 : intermediate underflow or overflow result if #
7084 # OVFL/UNFL occurred for a sgl or dbl operand #
7085 # #
7086 # ALGORITHM *********************************************************** #
7087 # This routine is accessed by many handlers that need to do an #
7088 # opclass three move of an operand out to memory. #
7089 # Decode an fmove out (opclass 3) instruction to determine if #
7090 # it's b,w,l,s,d,x, or p in size. b,w,l can be stored to either a data #
7091 # register or memory. The algorithm uses a standard "fmove" to create #
7092 # the rounded result. Also, since exceptions are disabled, this also #
7093 # create the correct OPERR default result if appropriate. #
7094 # For sgl or dbl precision, overflow or underflow can occur. If #
7095 # either occurs and is enabled, the EXOP. #
7096 # For extended precision, the stacked <ea> must be fixed along #
7097 # w/ the address index register as appropriate w/ _calc_ea_fout(). If #
7098 # the source is a denorm and if underflow is enabled, an EXOP must be #
7099 # created. #
7100 # For packed, the k-factor must be fetched from the instruction #
7101 # word or a data register. The <ea> must be fixed as w/ extended #
7102 # precision. Then, bindec() is called to create the appropriate #
7103 # packed result. #
7104 # If at any time an access error is flagged by one of the move- #
7105 # to-memory routines, then a special exit must be made so that the #
7106 # access error can be handled properly. #
7107 # #
7108 #########################################################################
7110 global fout
7111 fout:
7117 tbl_fout:
7118 short fout_long - tbl_fout
7119 short fout_sgl - tbl_fout
7120 short fout_ext - tbl_fout
7121 short fout_pack - tbl_fout
7122 short fout_word - tbl_fout
7123 short fout_dbl - tbl_fout
7124 short fout_byte - tbl_fout
7125 short fout_pack - tbl_fout
7127 #################################################################
7128 # fmove.b out ###################################################
7129 #################################################################
7131 # Only "Unimplemented Data Type" exceptions enter here. The operand
7132 # is either a DENORM or a NORM.
7133 fout_byte:
7139 fout_byte_norm:
7158 rts
7160 fout_byte_dn:
7163 bsr.l store_dreg_b
7164 rts
7166 fout_byte_denorm:
7171 bra.b fout_byte_norm
7173 #################################################################
7174 # fmove.w out ###################################################
7175 #################################################################
7177 # Only "Unimplemented Data Type" exceptions enter here. The operand
7178 # is either a DENORM or a NORM.
7179 fout_word:
7185 fout_word_norm:
7204 rts
7206 fout_word_dn:
7209 bsr.l store_dreg_w
7210 rts
7212 fout_word_denorm:
7217 bra.b fout_word_norm
7219 #################################################################
7220 # fmove.l out ###################################################
7221 #################################################################
7223 # Only "Unimplemented Data Type" exceptions enter here. The operand
7224 # is either a DENORM or a NORM.
7225 fout_long:
7231 fout_long_norm:
7240 fout_long_write:
7251 rts
7253 fout_long_dn:
7256 bsr.l store_dreg_l
7257 rts
7259 fout_long_denorm:
7264 bra.b fout_long_norm
7266 #################################################################
7267 # fmove.x out ###################################################
7268 #################################################################
7270 # Only "Unimplemented Data Type" exceptions enter here. The operand
7271 # is either a DENORM or a NORM.
7272 # The DENORM causes an Underflow exception.
7273 fout_ext:
7275 # we copy the extended precision result to FP_SCR0 so that the reserved
7276 # 16-bit field gets zeroed. we do this since we promise not to disturb
7277 # what's at SRC(a0).
7291 # we must not yet write the extended precision data to the stack
7292 # in the pre-decrement case from supervisor mode or else we'll corrupt
7293 # the stack frame. so, leave it in FP_SRC for now and deal with it later...
7295 beq.b fout_ext_a7
7300 bne.w fout_ext_err # yes
7304 rts
7306 # the number is a DENORM. must set the underflow exception bit
7307 fout_ext_denorm:
7313 rts
7315 # we don't want to do the write if the exception occurred in supervisor mode
7316 # so _mem_write2() handles this for us.
7317 fout_ext_a7:
7321 bne.w fout_ext_err # yes
7325 rts
7327 fout_ext_exc:
7335 rts
7337 fout_ext_err:
7339 bra.l facc_out_x
7341 #########################################################################
7342 # fmove.s out ###########################################################
7343 #########################################################################
7344 fout_sgl:
7349 #
7350 # operand is a normalized number. first, we check to see if the move out
7351 # would cause either an underflow or overflow. these cases are handled
7352 # separately. otherwise, set the FPCR to the proper rounding mode and
7353 # execute the move.
7354 #
7359 bgt.w fout_sgl_ovfl # yes; go handle OVFL
7360 beq.w fout_sgl_may_ovfl # maybe; go handle possible OVFL
7362 blt.w fout_sgl_unfl # yes; go handle underflow
7364 #
7365 # NORMs(in range) can be stored out by a simple "fmov.s"
7366 # Unnormalized inputs can come through this point.
7367 #
7368 fout_sgl_exg:
7381 fout_sgl_exg_write:
7392 rts
7394 fout_sgl_exg_write_dn:
7397 bsr.l store_dreg_l
7398 rts
7400 #
7401 # here, we know that the operand would UNFL if moved out to single prec,
7402 # so, denorm and round and then use generic store single routine to
7403 # write the value to memory.
7404 #
7405 fout_sgl_unfl:
7421 fout_sgl_unfl_cont:
7439 bra.b fout_sgl_unfl_chkexc
7441 fout_sgl_unfl_dn:
7444 bsr.l store_dreg_l
7446 fout_sgl_unfl_chkexc:
7449 bne.w fout_sd_exc_unfl # yes
7451 rts
7453 #
7454 # it's definitely an overflow so call ovf_res to get the correct answer
7455 #
7456 fout_sgl_ovfl:
7458 bne.b fout_sgl_ovfl_inex2
7460 bne.b fout_sgl_ovfl_inex2
7462 bra.b fout_sgl_ovfl_cont
7463 fout_sgl_ovfl_inex2:
7466 fout_sgl_ovfl_cont:
7469 # call ovf_res() w/ sgl prec and the correct rnd mode to create the default
7470 # overflow result. DON'T save the returned ccodes from ovf_res() since
7471 # fmove out doesn't alter them.
7489 bra.b fout_sgl_ovfl_chkexc
7491 fout_sgl_ovfl_dn:
7494 bsr.l store_dreg_l
7496 fout_sgl_ovfl_chkexc:
7499 bne.w fout_sd_exc_ovfl # yes
7501 rts
7503 #
7504 # move out MAY overflow:
7505 # (1) force the exp to 0x3fff
7506 # (2) do a move w/ appropriate rnd mode
7507 # (3) if exp still equals zero, then insert original exponent
7508 # for the correct result.
7509 # if exp now equals one, then it overflowed so call ovf_res.
7510 #
7511 fout_sgl_may_ovfl:
7526 fblt.w fout_sgl_exg # no; go finish NORM
7527 bra.w fout_sgl_ovfl # yes; go handle overflow
7529 ################
7531 fout_sd_exc_unfl:
7542 bsr.l norm
7546 bra.b fout_sd_exc_cont
7548 fout_sd_exc:
7549 fout_sd_exc_ovfl:
7556 fout_sd_exc_cont:
7564 swap %d1
7575 fout_sd_exc_done:
7577 rts
7579 #################################################################
7580 # fmove.d out ###################################################
7581 #################################################################
7582 fout_dbl:
7587 #
7588 # operand is a normalized number. first, we check to see if the move out
7589 # would cause either an underflow or overflow. these cases are handled
7590 # separately. otherwise, set the FPCR to the proper rounding mode and
7591 # execute the move.
7592 #
7597 bgt.w fout_dbl_ovfl # yes; go handle OVFL
7598 beq.w fout_dbl_may_ovfl # maybe; go handle possible OVFL
7600 blt.w fout_dbl_unfl # yes; go handle underflow
7602 #
7603 # NORMs(in range) can be stored out by a simple "fmov.d"
7604 # Unnormalized inputs can come through this point.
7605 #
7606 fout_dbl_exg:
7627 rts # no; so we're finished
7629 #
7630 # here, we know that the operand would UNFL if moved out to double prec,
7631 # so, denorm and round and then use generic store double routine to
7632 # write the value to memory.
7633 #
7634 fout_dbl_unfl:
7650 fout_dbl_unfl_cont:
7670 bne.w fout_sd_exc_unfl # yes
7672 rts
7674 #
7675 # it's definitely an overflow so call ovf_res to get the correct answer
7676 #
7677 fout_dbl_ovfl:
7680 bne.b fout_dbl_ovfl_inex2
7683 bra.b fout_dbl_ovfl_cont
7684 fout_dbl_ovfl_inex2:
7687 fout_dbl_ovfl_cont:
7690 # call ovf_res() w/ dbl prec and the correct rnd mode to create the default
7691 # overflow result. DON'T save the returned ccodes from ovf_res() since
7692 # fmove out doesn't alter them.
7710 bne.w fout_sd_exc_ovfl # yes
7712 rts
7714 #
7715 # move out MAY overflow:
7716 # (1) force the exp to 0x3fff
7717 # (2) do a move w/ appropriate rnd mode
7718 # (3) if exp still equals zero, then insert original exponent
7719 # for the correct result.
7720 # if exp now equals one, then it overflowed so call ovf_res.
7721 #
7722 fout_dbl_may_ovfl:
7737 fblt.w fout_dbl_exg # no; go finish NORM
7738 bra.w fout_dbl_ovfl # yes; go handle overflow
7740 #########################################################################
7741 # XDEF **************************************************************** #
7742 # dst_dbl(): create double precision value from extended prec. #
7743 # #
7744 # XREF **************************************************************** #
7745 # None #
7746 # #
7747 # INPUT *************************************************************** #
7748 # a0 = pointer to source operand in extended precision #
7749 # #
7750 # OUTPUT ************************************************************** #
7751 # d0 = hi(double precision result) #
7752 # d1 = lo(double precision result) #
7753 # #
7754 # ALGORITHM *********************************************************** #
7755 # #
7756 # Changes extended precision to double precision. #
7757 # Note: no attempt is made to round the extended value to double. #
7758 # dbl_sign = ext_sign #
7759 # dbl_exp = ext_exp - $3fff(ext bias) + $7ff(dbl bias) #
7760 # get rid of ext integer bit #
7761 # dbl_mant = ext_mant{62:12} #
7762 # #
7763 # --------------- --------------- --------------- #
7764 # extended -> |s| exp | |1| ms mant | | ls mant | #
7765 # --------------- --------------- --------------- #
7766 # 95 64 63 62 32 31 11 0 #
7767 # | | #
7768 # | | #
7769 # | | #
7770 # v v #
7771 # --------------- --------------- #
7772 # double -> |s|exp| mant | | mant | #
7773 # --------------- --------------- #
7774 # 63 51 32 31 0 #
7775 # #
7776 #########################################################################
7778 dst_dbl:
7786 dst_get_dupper:
7792 dst_get_dman:
7806 rts
7808 #########################################################################
7809 # XDEF **************************************************************** #
7810 # dst_sgl(): create single precision value from extended prec #
7811 # #
7812 # XREF **************************************************************** #
7813 # #
7814 # INPUT *************************************************************** #
7815 # a0 = pointer to source operand in extended precision #
7816 # #
7817 # OUTPUT ************************************************************** #
7818 # d0 = single precision result #
7819 # #
7820 # ALGORITHM *********************************************************** #
7821 # #
7822 # Changes extended precision to single precision. #
7823 # sgl_sign = ext_sign #
7824 # sgl_exp = ext_exp - $3fff(ext bias) + $7f(sgl bias) #
7825 # get rid of ext integer bit #
7826 # sgl_mant = ext_mant{62:12} #
7827 # #
7828 # --------------- --------------- --------------- #
7829 # extended -> |s| exp | |1| ms mant | | ls mant | #
7830 # --------------- --------------- --------------- #
7831 # 95 64 63 62 40 32 31 12 0 #
7832 # | | #
7833 # | | #
7834 # | | #
7835 # v v #
7836 # --------------- #
7837 # single -> |s|exp| mant | #
7838 # --------------- #
7839 # 31 22 0 #
7840 # #
7841 #########################################################################
7843 dst_sgl:
7851 dst_get_supper:
7857 dst_get_sman:
7862 rts
7864 ##############################################################################
7865 fout_pack:
7870 bne.w fout_pack_not_norm # input is not NORM
7872 fout_pack_norm:
7876 fout_pack_d:
7883 bra.b fout_pack_type
7884 fout_pack_s:
7887 fout_pack_type:
7893 # bindec is currently scrambling FP_SRC for denorm inputs.
7894 # we'll have to change this, but for now, tough luck!!!
7897 # andi.l &0xcfff000f,FP_SCR0(%a6) # clear unused fields
7903 bne.b fout_pack_set
7905 bne.b fout_pack_set
7907 bne.b fout_pack_set
7909 # add the extra condition that only if the k-factor was zero, too, should
7910 # we zero the exponent
7912 bne.b fout_pack_set
7913 # "mantissa" is all zero which means that the answer is zero. but, the '040
7914 # algorithm allows the exponent to be non-zero. the 881/2 do not. therefore,
7915 # if the mantissa is zero, I will zero the exponent, too.
7916 # the question now is whether the exponents sign bit is allowed to be non-zero
7917 # for a zero, also...
7920 fout_pack_set:
7924 fout_pack_write:
7929 beq.b fout_pack_a7
7934 bne.w fout_ext_err # yes
7936 rts
7938 # we don't want to do the write if the exception occurred in supervisor mode
7939 # so _mem_write2() handles this for us.
7940 fout_pack_a7:
7944 bne.w fout_ext_err # yes
7946 rts
7948 fout_pack_not_norm:
7950 beq.w fout_pack_norm # yes
7957 fout_pack_snan:
7960 bra.b fout_pack_write
7962 #########################################################################
7963 # XDEF **************************************************************** #
7964 # fmul(): emulates the fmul instruction #
7965 # fsmul(): emulates the fsmul instruction #
7966 # fdmul(): emulates the fdmul instruction #
7967 # #
7968 # XREF **************************************************************** #
7969 # scale_to_zero_src() - scale src exponent to zero #
7970 # scale_to_zero_dst() - scale dst exponent to zero #
7971 # unf_res() - return default underflow result #
7972 # ovf_res() - return default overflow result #
7973 # res_qnan() - return QNAN result #
7974 # res_snan() - return SNAN result #
7975 # #
7976 # INPUT *************************************************************** #
7977 # a0 = pointer to extended precision source operand #
7978 # a1 = pointer to extended precision destination operand #
7979 # d0 rnd prec,mode #
7980 # #
7981 # OUTPUT ************************************************************** #
7982 # fp0 = result #
7983 # fp1 = EXOP (if exception occurred) #
7984 # #
7985 # ALGORITHM *********************************************************** #
7986 # Handle NANs, infinities, and zeroes as special cases. Divide #
7987 # norms/denorms into ext/sgl/dbl precision. #
7988 # For norms/denorms, scale the exponents such that a multiply #
7989 # instruction won't cause an exception. Use the regular fmul to #
7990 # compute a result. Check if the regular operands would have taken #
7991 # an exception. If so, return the default overflow/underflow result #
7992 # and return the EXOP if exceptions are enabled. Else, scale the #
7993 # result operand to the proper exponent. #
7994 # #
7995 #########################################################################
7997 align 0x10
7998 tbl_fmul_ovfl:
8002 tbl_fmul_unfl:
8007 global fsmul
8008 fsmul:
8011 bra.b fmul
8013 global fdmul
8014 fdmul:
8018 global fmul
8022 clr.w %d1
8026 bne.w fmul_not_norm # optimize on non-norm input
8028 fmul_norm:
8048 beq.w fmul_may_ovfl # result may rnd to overflow
8049 blt.w fmul_ovfl # result will overflow
8052 beq.w fmul_may_unfl # result may rnd to no unfl
8053 bgt.w fmul_unfl # result will underflow
8055 #
8056 # NORMAL:
8057 # - the result of the multiply operation will neither overflow nor underflow.
8058 # - do the multiply to the proper precision and rounding mode.
8059 # - scale the result exponent using the scale factor. if both operands were
8060 # normalized then we really don't need to go through this scaling. but for now,
8061 # this will do.
8062 #
8063 fmul_normal:
8076 fmul_normal_exit:
8088 rts
8090 #
8091 # OVERFLOW:
8092 # - the result of the multiply operation is an overflow.
8093 # - do the multiply to the proper precision and rounding mode in order to
8094 # set the inexact bits.
8095 # - calculate the default result and return it in fp0.
8096 # - if overflow or inexact is enabled, we need a multiply result rounded to
8097 # extended precision. if the original operation was extended, then we have this
8098 # result. if the original operation was single or double, we have to do another
8099 # multiply using extended precision and the correct rounding mode. the result
8100 # of this operation then has its exponent scaled by -0x6000 to create the
8101 # exceptional operand.
8102 #
8103 fmul_ovfl:
8116 # save setting this until now because this is where fmul_may_ovfl may jump in
8117 fmul_ovfl_tst:
8124 # calculate the default result
8125 fmul_ovfl_dis:
8132 rts
8134 #
8135 # OVFL is enabled; Create EXOP:
8136 # - if precision is extended, then we have the EXOP. simply bias the exponent
8137 # with an extra -0x6000. if the precision is single or double, we need to
8138 # calculate a result rounded to extended precision.
8139 #
8140 fmul_ovfl_ena:
8145 fmul_ovfl_ena_cont:
8160 bra.b fmul_ovfl_dis
8162 fmul_ovfl_ena_sd:
8172 bra.b fmul_ovfl_ena_cont
8174 #
8175 # may OVERFLOW:
8176 # - the result of the multiply operation MAY overflow.
8177 # - do the multiply to the proper precision and rounding mode in order to
8178 # set the inexact bits.
8179 # - calculate the default result and return it in fp0.
8180 #
8181 fmul_may_ovfl:
8196 fbge.w fmul_ovfl_tst # yes; overflow has occurred
8198 # no, it didn't overflow; we have correct result
8199 bra.w fmul_normal_exit
8201 #
8202 # UNDERFLOW:
8203 # - the result of the multiply operation is an underflow.
8204 # - do the multiply to the proper precision and rounding mode in order to
8205 # set the inexact bits.
8206 # - calculate the default result and return it in fp0.
8207 # - if overflow or inexact is enabled, we need a multiply result rounded to
8208 # extended precision. if the original operation was extended, then we have this
8209 # result. if the original operation was single or double, we have to do another
8210 # multiply using extended precision and the correct rounding mode. the result
8211 # of this operation then has its exponent scaled by -0x6000 to create the
8212 # exceptional operand.
8213 #
8214 fmul_unfl:
8217 # for fun, let's use only extended precision, round to zero. then, let
8218 # the unf_res() routine figure out all the rest.
8219 # will we get the correct answer.
8236 fmul_unfl_dis:
8244 rts
8246 #
8247 # UNFL is enabled.
8248 #
8249 fmul_unfl_ena:
8256 # if the rnd mode is anything but RZ, then we have to re-do the above
8257 # multiplication because we used RZ for all.
8260 fmul_unfl_ena_cont:
8280 bra.w fmul_unfl_dis
8282 fmul_unfl_ena_sd:
8287 bra.b fmul_unfl_ena_cont
8289 # MAY UNDERFLOW:
8290 # -use the correct rounding mode and precision. this code favors operations
8291 # that do not underflow.
8292 fmul_may_unfl:
8307 fbgt.w fmul_normal_exit # no; no underflow occurred
8308 fblt.w fmul_unfl # yes; underflow occurred
8310 #
8311 # we still don't know if underflow occurred. result is ~ equal to 2. but,
8312 # we don't know if the result was an underflow that rounded up to a 2 or
8313 # a normalized number that rounded down to a 2. so, redo the entire operation
8314 # using RZ as the rounding mode to see what the pre-rounded result is.
8315 # this case should be relatively rare.
8316 #
8331 fbge.w fmul_normal_exit # no; no underflow occurred
8332 bra.w fmul_unfl # yes, underflow occurred
8334 ################################################################################
8336 #
8337 # Multiply: inputs are not both normalized; what are they?
8338 #
8339 fmul_not_norm:
8344 tbl_fmul_op:
8399 fmul_res_operr:
8400 bra.l res_operr
8401 fmul_res_snan:
8402 bra.l res_snan
8403 fmul_res_qnan:
8404 bra.l res_qnan
8406 #
8407 # Multiply: (Zero x Zero) || (Zero x norm) || (Zero x denorm)
8408 #
8409 global fmul_zero # global for fsglmul
8410 fmul_zero:
8415 fmul_zero_n:
8418 rts
8419 fmul_zero_p:
8422 rts
8424 #
8425 # Multiply: (inf x inf) || (inf x norm) || (inf x denorm)
8426 #
8427 # Note: The j-bit for an infinity is a don't-care. However, to be
8428 # strictly compatible w/ the 68881/882, we make sure to return an
8429 # INF w/ the j-bit set if the input INF j-bit was set. Destination
8430 # INFs take priority.
8431 #
8432 global fmul_inf_dst # global for fsglmul
8433 fmul_inf_dst:
8439 fmul_inf_dst_n:
8443 rts
8444 fmul_inf_dst_p:
8447 rts
8449 global fmul_inf_src # global for fsglmul
8450 fmul_inf_src:
8456 bra.b fmul_inf_dst_n
8458 #########################################################################
8459 # XDEF **************************************************************** #
8460 # fin(): emulates the fmove instruction #
8461 # fsin(): emulates the fsmove instruction #
8462 # fdin(): emulates the fdmove instruction #
8463 # #
8464 # XREF **************************************************************** #
8465 # norm() - normalize mantissa for EXOP on denorm #
8466 # scale_to_zero_src() - scale src exponent to zero #
8467 # ovf_res() - return default overflow result #
8468 # unf_res() - return default underflow result #
8469 # res_qnan_1op() - return QNAN result #
8470 # res_snan_1op() - return SNAN result #
8471 # #
8472 # INPUT *************************************************************** #
8473 # a0 = pointer to extended precision source operand #
8474 # d0 = round prec/mode #
8475 # #
8476 # OUTPUT ************************************************************** #
8477 # fp0 = result #
8478 # fp1 = EXOP (if exception occurred) #
8479 # #
8480 # ALGORITHM *********************************************************** #
8481 # Handle NANs, infinities, and zeroes as special cases. Divide #
8482 # norms into extended, single, and double precision. #
8483 # Norms can be emulated w/ a regular fmove instruction. For #
8484 # sgl/dbl, must scale exponent and perform an "fmove". Check to see #
8485 # if the result would have overflowed/underflowed. If so, use unf_res() #
8486 # or ovf_res() to return the default result. Also return EXOP if #
8487 # exception is enabled. If no exception, return the default result. #
8488 # Unnorms don't pass through here. #
8489 # #
8490 #########################################################################
8492 global fsin
8493 fsin:
8496 bra.b fin
8498 global fdin
8499 fdin:
8503 global fin
8504 fin:
8508 bne.w fin_not_norm # optimize on non-norm input
8510 #
8511 # FP MOVE IN: NORMs and DENORMs ONLY!
8512 #
8513 fin_norm:
8515 bne.w fin_not_ext # no, so go handle dbl or sgl
8517 #
8518 # precision selected is extended. so...we cannot get an underflow
8519 # or overflow because of rounding to the correct precision. so...
8520 # skip the scaling and unscaling...
8521 #
8525 fin_norm_done:
8527 rts
8529 #
8530 # for an extended precision DENORM, the UNFL exception bit is set
8531 # the accrued bit is NOT set in this instance(no inexactness!)
8532 #
8533 fin_denorm:
8535 bne.w fin_not_ext # no, so go handle dbl or sgl
8541 fin_denorm_done:
8545 rts
8547 #
8548 # the input is an extended DENORM and underflow is enabled in the FPCR.
8549 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
8550 # exponent and insert back into the operand.
8551 #
8552 fin_denorm_unfl_ena:
8566 rts
8568 #
8569 # operand is to be rounded to single or double precision
8570 #
8571 fin_not_ext:
8573 bne.b fin_dbl
8575 #
8576 # operand is to be rounded to single precision
8577 #
8578 fin_sgl:
8585 bge.w fin_sd_unfl # yes; go handle underflow
8587 beq.w fin_sd_may_ovfl # maybe; go check
8588 blt.w fin_sd_ovfl # yes; go handle overflow
8590 #
8591 # operand will NOT overflow or underflow when moved into the fp reg file
8592 #
8593 fin_sd_normal:
8604 fin_sd_normal_exit:
8616 rts
8618 #
8619 # operand is to be rounded to double precision
8620 #
8621 fin_dbl:
8628 bge.w fin_sd_unfl # yes; go handle underflow
8630 beq.w fin_sd_may_ovfl # maybe; go check
8631 blt.w fin_sd_ovfl # yes; go handle overflow
8632 bra.w fin_sd_normal # no; ho handle normalized op
8634 #
8635 # operand WILL underflow when moved in to the fp register file
8636 #
8637 fin_sd_unfl:
8641 bpl.b fin_sd_unfl_tst
8644 # if underflow or inexact is enabled, then go calculate the EXOP first.
8645 fin_sd_unfl_tst:
8650 fin_sd_unfl_dis:
8656 rts
8658 #
8659 # operand will underflow AND underflow or inexact is enabled.
8660 # therefore, we must return the result rounded to extended precision.
8661 #
8662 fin_sd_unfl_ena:
8678 bra.b fin_sd_unfl_dis
8680 #
8681 # operand WILL overflow.
8682 #
8683 fin_sd_ovfl:
8694 fin_sd_ovfl_tst:
8701 #
8702 # OVFL is not enabled; therefore, we must create the default result by
8703 # calling ovf_res().
8704 #
8705 fin_sd_ovfl_dis:
8712 rts
8714 #
8715 # OVFL is enabled.
8716 # the INEX2 bit has already been updated by the round to the correct precision.
8717 # now, round to extended(and don't alter the FPSR).
8718 #
8719 fin_sd_ovfl_ena:
8732 bra.b fin_sd_ovfl_dis
8734 #
8735 # the move in MAY overflow. so...
8736 #
8737 fin_sd_may_ovfl:
8750 fbge.w fin_sd_ovfl_tst # yes; overflow has occurred
8752 # no, it didn't overflow; we have correct result
8753 bra.w fin_sd_normal_exit
8755 ##########################################################################
8757 #
8758 # operand is not a NORM: check its optype and branch accordingly
8759 #
8760 fin_not_norm:
8762 beq.w fin_denorm
8764 beq.l res_snan_1op
8766 beq.l res_qnan_1op
8768 #
8769 # do the fmove in; at this point, only possible ops are ZERO and INF.
8770 # use fmov to determine ccodes.
8771 # prec:mode should be zero at this point but it won't affect answer anyways.
8772 #
8777 rts
8779 #########################################################################
8780 # XDEF **************************************************************** #
8781 # fdiv(): emulates the fdiv instruction #
8782 # fsdiv(): emulates the fsdiv instruction #
8783 # fddiv(): emulates the fddiv instruction #
8784 # #
8785 # XREF **************************************************************** #
8786 # scale_to_zero_src() - scale src exponent to zero #
8787 # scale_to_zero_dst() - scale dst exponent to zero #
8788 # unf_res() - return default underflow result #
8789 # ovf_res() - return default overflow result #
8790 # res_qnan() - return QNAN result #
8791 # res_snan() - return SNAN result #
8792 # #
8793 # INPUT *************************************************************** #
8794 # a0 = pointer to extended precision source operand #
8795 # a1 = pointer to extended precision destination operand #
8796 # d0 rnd prec,mode #
8797 # #
8798 # OUTPUT ************************************************************** #
8799 # fp0 = result #
8800 # fp1 = EXOP (if exception occurred) #
8801 # #
8802 # ALGORITHM *********************************************************** #
8803 # Handle NANs, infinities, and zeroes as special cases. Divide #
8804 # norms/denorms into ext/sgl/dbl precision. #
8805 # For norms/denorms, scale the exponents such that a divide #
8806 # instruction won't cause an exception. Use the regular fdiv to #
8807 # compute a result. Check if the regular operands would have taken #
8808 # an exception. If so, return the default overflow/underflow result #
8809 # and return the EXOP if exceptions are enabled. Else, scale the #
8810 # result operand to the proper exponent. #
8811 # #
8812 #########################################################################
8814 align 0x10
8815 tbl_fdiv_unfl:
8820 tbl_fdiv_ovfl:
8825 global fsdiv
8826 fsdiv:
8829 bra.b fdiv
8831 global fddiv
8832 fddiv:
8836 global fdiv
8840 clr.w %d1
8845 bne.w fdiv_not_norm # optimize on non-norm input
8847 #
8848 # DIVIDE: NORMs and DENORMs ONLY!
8849 #
8850 fdiv_norm:
8871 ble.w fdiv_may_ovfl # result will overflow
8874 beq.w fdiv_may_unfl # maybe
8875 bgt.w fdiv_unfl # yes; go handle underflow
8877 fdiv_normal:
8890 fdiv_normal_exit:
8902 rts
8904 tbl_fdiv_ovfl2:
8905 long 0x7fff
8906 long 0x407f
8907 long 0x43ff
8909 fdiv_no_ovfl:
8911 bra.b fdiv_normal_exit
8913 fdiv_may_ovfl:
8934 blt.b fdiv_no_ovfl
8937 fdiv_ovfl_tst:
8944 fdiv_ovfl_dis:
8951 rts
8953 fdiv_ovfl_ena:
8958 fdiv_ovfl_ena_cont:
8973 bra.b fdiv_ovfl_dis
8975 fdiv_ovfl_ena_sd:
8985 bra.b fdiv_ovfl_ena_cont
8987 fdiv_unfl:
9006 fdiv_unfl_dis:
9014 rts
9016 #
9017 # UNFL is enabled.
9018 #
9019 fdiv_unfl_ena:
9028 fdiv_unfl_ena_cont:
9048 bra.w fdiv_unfl_dis
9050 fdiv_unfl_ena_sd:
9055 bra.b fdiv_unfl_ena_cont
9057 #
9058 # the divide operation MAY underflow:
9059 #
9060 fdiv_may_unfl:
9075 fbgt.w fdiv_normal_exit # no; no underflow occurred
9076 fblt.w fdiv_unfl # yes; underflow occurred
9078 #
9079 # we still don't know if underflow occurred. result is ~ equal to 1. but,
9080 # we don't know if the result was an underflow that rounded up to a 1
9081 # or a normalized number that rounded down to a 1. so, redo the entire
9082 # operation using RZ as the rounding mode to see what the pre-rounded
9083 # result is. this case should be relatively rare.
9084 #
9099 fbge.w fdiv_normal_exit # no; no underflow occurred
9100 bra.w fdiv_unfl # yes; underflow occurred
9102 ############################################################################
9104 #
9105 # Divide: inputs are not both normalized; what are they?
9106 #
9107 fdiv_not_norm:
9112 tbl_fdiv_op:
9167 fdiv_res_qnan:
9168 bra.l res_qnan
9169 fdiv_res_snan:
9170 bra.l res_snan
9171 fdiv_res_operr:
9172 bra.l res_operr
9174 global fdiv_zero_load # global for fsgldiv
9175 fdiv_zero_load:
9182 rts
9183 fdiv_zero_load_p:
9186 rts
9188 #
9189 # The destination was In Range and the source was a ZERO. The result,
9190 # therefore, is an INF w/ the proper sign.
9191 # So, determine the sign and return a new INF (w/ the j-bit cleared).
9192 #
9193 global fdiv_inf_load # global for fsgldiv
9194 fdiv_inf_load:
9202 rts
9203 fdiv_inf_load_p:
9206 rts
9208 #
9209 # The destination was an INF w/ an In Range or ZERO source, the result is
9210 # an INF w/ the proper sign.
9211 # The 68881/882 returns the destination INF w/ the new sign(if the j-bit of the
9212 # dst INF is set, then then j-bit of the result INF is also set).
9213 #
9214 global fdiv_inf_dst # global for fsgldiv
9215 fdiv_inf_dst:
9225 rts
9227 fdiv_inf_dst_p:
9231 rts
9233 #########################################################################
9234 # XDEF **************************************************************** #
9235 # fneg(): emulates the fneg instruction #
9236 # fsneg(): emulates the fsneg instruction #
9237 # fdneg(): emulates the fdneg instruction #
9238 # #
9239 # XREF **************************************************************** #
9240 # norm() - normalize a denorm to provide EXOP #
9241 # scale_to_zero_src() - scale sgl/dbl source exponent #
9242 # ovf_res() - return default overflow result #
9243 # unf_res() - return default underflow result #
9244 # res_qnan_1op() - return QNAN result #
9245 # res_snan_1op() - return SNAN result #
9246 # #
9247 # INPUT *************************************************************** #
9248 # a0 = pointer to extended precision source operand #
9249 # d0 = rnd prec,mode #
9250 # #
9251 # OUTPUT ************************************************************** #
9252 # fp0 = result #
9253 # fp1 = EXOP (if exception occurred) #
9254 # #
9255 # ALGORITHM *********************************************************** #
9256 # Handle NANs, zeroes, and infinities as special cases. Separate #
9257 # norms/denorms into ext/sgl/dbl precisions. Extended precision can be #
9258 # emulated by simply setting sign bit. Sgl/dbl operands must be scaled #
9259 # and an actual fneg performed to see if overflow/underflow would have #
9260 # occurred. If so, return default underflow/overflow result. Else, #
9261 # scale the result exponent and return result. FPSR gets set based on #
9262 # the result value. #
9263 # #
9264 #########################################################################
9266 global fsneg
9267 fsneg:
9270 bra.b fneg
9272 global fdneg
9273 fdneg:
9277 global fneg
9281 bne.w fneg_not_norm # optimize on non-norm input
9283 #
9284 # NEGATE SIGN : norms and denorms ONLY!
9285 #
9286 fneg_norm:
9288 bne.w fneg_not_ext # no; go handle sgl or dbl
9290 #
9291 # precision selected is extended. so...we can not get an underflow
9292 # or overflow because of rounding to the correct precision. so...
9293 # skip the scaling and unscaling...
9294 #
9301 fneg_norm_load:
9304 rts
9306 #
9307 # for an extended precision DENORM, the UNFL exception bit is set
9308 # the accrued bit is NOT set in this instance(no inexactness!)
9309 #
9310 fneg_denorm:
9322 fneg_denorm_done:
9328 rts
9330 #
9331 # the input is an extended DENORM and underflow is enabled in the FPCR.
9332 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
9333 # exponent and insert back into the operand.
9334 #
9335 fneg_ext_unfl_ena:
9346 rts
9348 #
9349 # operand is either single or double
9350 #
9351 fneg_not_ext:
9353 bne.b fneg_dbl
9355 #
9356 # operand is to be rounded to single precision
9357 #
9358 fneg_sgl:
9365 bge.w fneg_sd_unfl # yes; go handle underflow
9367 beq.w fneg_sd_may_ovfl # maybe; go check
9368 blt.w fneg_sd_ovfl # yes; go handle overflow
9370 #
9371 # operand will NOT overflow or underflow when moved in to the fp reg file
9372 #
9373 fneg_sd_normal:
9384 fneg_sd_normal_exit:
9396 rts
9398 #
9399 # operand is to be rounded to double precision
9400 #
9401 fneg_dbl:
9410 beq.w fneg_sd_may_ovfl # maybe; go check
9411 blt.w fneg_sd_ovfl # yes; go handle overflow
9412 bra.w fneg_sd_normal # no; ho handle normalized op
9414 #
9415 # operand WILL underflow when moved in to the fp register file
9416 #
9417 fneg_sd_unfl:
9421 bpl.b fneg_sd_unfl_tst
9424 # if underflow or inexact is enabled, go calculate EXOP first.
9425 fneg_sd_unfl_tst:
9430 fneg_sd_unfl_dis:
9436 rts
9438 #
9439 # operand will underflow AND underflow is enabled.
9440 # therefore, we must return the result rounded to extended precision.
9441 #
9442 fneg_sd_unfl_ena:
9458 bra.b fneg_sd_unfl_dis
9460 #
9461 # operand WILL overflow.
9462 #
9463 fneg_sd_ovfl:
9474 fneg_sd_ovfl_tst:
9481 #
9482 # OVFL is not enabled; therefore, we must create the default result by
9483 # calling ovf_res().
9484 #
9485 fneg_sd_ovfl_dis:
9492 rts
9494 #
9495 # OVFL is enabled.
9496 # the INEX2 bit has already been updated by the round to the correct precision.
9497 # now, round to extended(and don't alter the FPSR).
9498 #
9499 fneg_sd_ovfl_ena:
9512 bra.b fneg_sd_ovfl_dis
9514 #
9515 # the move in MAY underflow. so...
9516 #
9517 fneg_sd_may_ovfl:
9530 fbge.w fneg_sd_ovfl_tst # yes; overflow has occurred
9532 # no, it didn't overflow; we have correct result
9533 bra.w fneg_sd_normal_exit
9535 ##########################################################################
9537 #
9538 # input is not normalized; what is it?
9539 #
9540 fneg_not_norm:
9542 beq.w fneg_denorm
9544 beq.l res_snan_1op
9546 beq.l res_qnan_1op
9548 #
9549 # do the fneg; at this point, only possible ops are ZERO and INF.
9550 # use fneg to determine ccodes.
9551 # prec:mode should be zero at this point but it won't affect answer anyways.
9552 #
9557 rts
9559 #########################################################################
9560 # XDEF **************************************************************** #
9561 # ftst(): emulates the ftest instruction #
9562 # #
9563 # XREF **************************************************************** #
9564 # res{s,q}nan_1op() - set NAN result for monadic instruction #
9565 # #
9566 # INPUT *************************************************************** #
9567 # a0 = pointer to extended precision source operand #
9568 # #
9569 # OUTPUT ************************************************************** #
9570 # none #
9571 # #
9572 # ALGORITHM *********************************************************** #
9573 # Check the source operand tag (STAG) and set the FPCR according #
9574 # to the operand type and sign. #
9575 # #
9576 #########################################################################
9578 global ftst
9579 ftst:
9583 #
9584 # Norm:
9585 #
9586 ftst_norm:
9589 rts
9590 ftst_norm_m:
9592 rts
9594 #
9595 # input is not normalized; what is it?
9596 #
9597 ftst_not_norm:
9599 beq.b ftst_zero
9601 beq.b ftst_inf
9603 beq.l res_snan_1op
9605 beq.l res_qnan_1op
9607 #
9608 # Denorm:
9609 #
9610 ftst_denorm:
9613 rts
9614 ftst_denorm_m:
9616 rts
9618 #
9619 # Infinity:
9620 #
9621 ftst_inf:
9624 ftst_inf_p:
9626 rts
9627 ftst_inf_m:
9629 rts
9631 #
9632 # Zero:
9633 #
9634 ftst_zero:
9637 ftst_zero_p:
9639 rts
9640 ftst_zero_m:
9642 rts
9644 #########################################################################
9645 # XDEF **************************************************************** #
9646 # fint(): emulates the fint instruction #
9647 # #
9648 # XREF **************************************************************** #
9649 # res_{s,q}nan_1op() - set NAN result for monadic operation #
9650 # #
9651 # INPUT *************************************************************** #
9652 # a0 = pointer to extended precision source operand #
9653 # d0 = round precision/mode #
9654 # #
9655 # OUTPUT ************************************************************** #
9656 # fp0 = result #
9657 # #
9658 # ALGORITHM *********************************************************** #
9659 # Separate according to operand type. Unnorms don't pass through #
9660 # here. For norms, load the rounding mode/prec, execute a "fint", then #
9661 # store the resulting FPSR bits. #
9662 # For denorms, force the j-bit to a one and do the same as for #
9663 # norms. Denorms are so low that the answer will either be a zero or a #
9664 # one. #
9665 # For zeroes/infs/NANs, return the same while setting the FPSR #
9666 # as appropriate. #
9667 # #
9668 #########################################################################
9670 global fint
9671 fint:
9675 #
9676 # Norm:
9677 #
9678 fint_norm:
9690 rts
9692 #
9693 # input is not normalized; what is it?
9694 #
9695 fint_not_norm:
9697 beq.b fint_zero
9699 beq.b fint_inf
9701 beq.b fint_denorm
9703 beq.l res_snan_1op
9706 #
9707 # Denorm:
9708 #
9709 # for DENORMs, the result will be either (+/-)ZERO or (+/-)1.
9710 # also, the INEX2 and AINEX exception bits will be set.
9711 # so, we could either set these manually or force the DENORM
9712 # to a very small NORM and ship it to the NORM routine.
9713 # I do the latter.
9714 #
9715 fint_denorm:
9719 bra.b fint_norm
9721 #
9722 # Zero:
9723 #
9724 fint_zero:
9727 fint_zero_p:
9730 rts
9731 fint_zero_m:
9734 rts
9736 #
9737 # Infinity:
9738 #
9739 fint_inf:
9743 fint_inf_p:
9745 rts
9746 fint_inf_m:
9748 rts
9750 #########################################################################
9751 # XDEF **************************************************************** #
9752 # fintrz(): emulates the fintrz instruction #
9753 # #
9754 # XREF **************************************************************** #
9755 # res_{s,q}nan_1op() - set NAN result for monadic operation #
9756 # #
9757 # INPUT *************************************************************** #
9758 # a0 = pointer to extended precision source operand #
9759 # d0 = round precision/mode #
9760 # #
9761 # OUTPUT ************************************************************** #
9762 # fp0 = result #
9763 # #
9764 # ALGORITHM *********************************************************** #
9765 # Separate according to operand type. Unnorms don't pass through #
9766 # here. For norms, load the rounding mode/prec, execute a "fintrz", #
9767 # then store the resulting FPSR bits. #
9768 # For denorms, force the j-bit to a one and do the same as for #
9769 # norms. Denorms are so low that the answer will either be a zero or a #
9770 # one. #
9771 # For zeroes/infs/NANs, return the same while setting the FPSR #
9772 # as appropriate. #
9773 # #
9774 #########################################################################
9776 global fintrz
9777 fintrz:
9781 #
9782 # Norm:
9783 #
9784 fintrz_norm:
9792 rts
9794 #
9795 # input is not normalized; what is it?
9796 #
9797 fintrz_not_norm:
9799 beq.b fintrz_zero
9801 beq.b fintrz_inf
9803 beq.b fintrz_denorm
9805 beq.l res_snan_1op
9808 #
9809 # Denorm:
9810 #
9811 # for DENORMs, the result will be (+/-)ZERO.
9812 # also, the INEX2 and AINEX exception bits will be set.
9813 # so, we could either set these manually or force the DENORM
9814 # to a very small NORM and ship it to the NORM routine.
9815 # I do the latter.
9816 #
9817 fintrz_denorm:
9821 bra.b fintrz_norm
9823 #
9824 # Zero:
9825 #
9826 fintrz_zero:
9829 fintrz_zero_p:
9832 rts
9833 fintrz_zero_m:
9836 rts
9838 #
9839 # Infinity:
9840 #
9841 fintrz_inf:
9845 fintrz_inf_p:
9847 rts
9848 fintrz_inf_m:
9850 rts
9852 #########################################################################
9853 # XDEF **************************************************************** #
9854 # fabs(): emulates the fabs instruction #
9855 # fsabs(): emulates the fsabs instruction #
9856 # fdabs(): emulates the fdabs instruction #
9857 # #
9858 # XREF **************************************************************** #
9859 # norm() - normalize denorm mantissa to provide EXOP #
9860 # scale_to_zero_src() - make exponent. = 0; get scale factor #
9861 # unf_res() - calculate underflow result #
9862 # ovf_res() - calculate overflow result #
9863 # res_{s,q}nan_1op() - set NAN result for monadic operation #
9864 # #
9865 # INPUT *************************************************************** #
9866 # a0 = pointer to extended precision source operand #
9867 # d0 = rnd precision/mode #
9868 # #
9869 # OUTPUT ************************************************************** #
9870 # fp0 = result #
9871 # fp1 = EXOP (if exception occurred) #
9872 # #
9873 # ALGORITHM *********************************************************** #
9874 # Handle NANs, infinities, and zeroes as special cases. Divide #
9875 # norms into extended, single, and double precision. #
9876 # Simply clear sign for extended precision norm. Ext prec denorm #
9877 # gets an EXOP created for it since it's an underflow. #
9878 # Double and single precision can overflow and underflow. First, #
9879 # scale the operand such that the exponent is zero. Perform an "fabs" #
9880 # using the correct rnd mode/prec. Check to see if the original #
9881 # exponent would take an exception. If so, use unf_res() or ovf_res() #
9882 # to calculate the default result. Also, create the EXOP for the #
9883 # exceptional case. If no exception should occur, insert the correct #
9884 # result exponent and return. #
9885 # Unnorms don't pass through here. #
9886 # #
9887 #########################################################################
9889 global fsabs
9890 fsabs:
9893 bra.b fabs
9895 global fdabs
9896 fdabs:
9900 global fabs
9904 bne.w fabs_not_norm # optimize on non-norm input
9906 #
9907 # ABSOLUTE VALUE: norms and denorms ONLY!
9908 #
9909 fabs_norm:
9913 #
9914 # precision selected is extended. so...we can not get an underflow
9915 # or overflow because of rounding to the correct precision. so...
9916 # skip the scaling and unscaling...
9917 #
9924 rts
9926 #
9927 # for an extended precision DENORM, the UNFL exception bit is set
9928 # the accrued bit is NOT set in this instance(no inexactness!)
9929 #
9930 fabs_denorm:
9945 bne.b fabs_ext_unfl_ena
9946 rts
9948 #
9949 # the input is an extended DENORM and underflow is enabled in the FPCR.
9950 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
9951 # exponent and insert back into the operand.
9952 #
9953 fabs_ext_unfl_ena:
9964 rts
9966 #
9967 # operand is either single or double
9968 #
9969 fabs_not_ext:
9971 bne.b fabs_dbl
9973 #
9974 # operand is to be rounded to single precision
9975 #
9976 fabs_sgl:
9983 bge.w fabs_sd_unfl # yes; go handle underflow
9985 beq.w fabs_sd_may_ovfl # maybe; go check
9986 blt.w fabs_sd_ovfl # yes; go handle overflow
9988 #
9989 # operand will NOT overflow or underflow when moved in to the fp reg file
9990 #
9991 fabs_sd_normal:
10002 fabs_sd_normal_exit:
10014 rts
10016 #
10017 # operand is to be rounded to double precision
10018 #
10019 fabs_dbl:
10028 beq.w fabs_sd_may_ovfl # maybe; go check
10029 blt.w fabs_sd_ovfl # yes; go handle overflow
10030 bra.w fabs_sd_normal # no; ho handle normalized op
10032 #
10033 # operand WILL underflow when moved in to the fp register file
10034 #
10035 fabs_sd_unfl:
10040 # if underflow or inexact is enabled, go calculate EXOP first.
10045 fabs_sd_unfl_dis:
10051 rts
10053 #
10054 # operand will underflow AND underflow is enabled.
10055 # therefore, we must return the result rounded to extended precision.
10056 #
10057 fabs_sd_unfl_ena:
10073 bra.b fabs_sd_unfl_dis
10075 #
10076 # operand WILL overflow.
10077 #
10078 fabs_sd_ovfl:
10089 fabs_sd_ovfl_tst:
10096 #
10097 # OVFL is not enabled; therefore, we must create the default result by
10098 # calling ovf_res().
10099 #
10100 fabs_sd_ovfl_dis:
10107 rts
10109 #
10110 # OVFL is enabled.
10111 # the INEX2 bit has already been updated by the round to the correct precision.
10112 # now, round to extended(and don't alter the FPSR).
10113 #
10114 fabs_sd_ovfl_ena:
10127 bra.b fabs_sd_ovfl_dis
10129 #
10130 # the move in MAY underflow. so...
10131 #
10132 fabs_sd_may_ovfl:
10145 fbge.w fabs_sd_ovfl_tst # yes; overflow has occurred
10147 # no, it didn't overflow; we have correct result
10148 bra.w fabs_sd_normal_exit
10150 ##########################################################################
10152 #
10153 # input is not normalized; what is it?
10154 #
10155 fabs_not_norm:
10157 beq.w fabs_denorm
10159 beq.l res_snan_1op
10161 beq.l res_qnan_1op
10166 beq.b fabs_inf
10167 fabs_zero:
10169 rts
10170 fabs_inf:
10172 rts
10174 #########################################################################
10175 # XDEF **************************************************************** #
10176 # fcmp(): fp compare op routine #
10177 # #
10178 # XREF **************************************************************** #
10179 # res_qnan() - return QNAN result #
10180 # res_snan() - return SNAN result #
10181 # #
10182 # INPUT *************************************************************** #
10183 # a0 = pointer to extended precision source operand #
10184 # a1 = pointer to extended precision destination operand #
10185 # d0 = round prec/mode #
10186 # #
10187 # OUTPUT ************************************************************** #
10188 # None #
10189 # #
10190 # ALGORITHM *********************************************************** #
10191 # Handle NANs and denorms as special cases. For everything else, #
10192 # just use the actual fcmp instruction to produce the correct condition #
10193 # codes. #
10194 # #
10195 #########################################################################
10197 global fcmp
10198 fcmp:
10199 clr.w %d1
10205 #
10206 # COMPARE FP OPs : NORMs, ZEROs, INFs, and "corrected" DENORMs
10207 #
10208 fcmp_norm:
10217 rts
10219 #
10220 # fcmp: inputs are not both normalized; what are they?
10221 #
10222 fcmp_not_norm:
10227 tbl_fcmp_op:
10282 # unlike all other functions for QNAN and SNAN, fcmp does NOT set the
10283 # 'N' bit for a negative QNAN or SNAN input so we must squelch it here.
10284 fcmp_res_qnan:
10285 bsr.l res_qnan
10287 rts
10288 fcmp_res_snan:
10289 bsr.l res_snan
10291 rts
10293 #
10294 # DENORMs are a little more difficult.
10295 # If you have a 2 DENORMs, then you can just force the j-bit to a one
10296 # and use the fcmp_norm routine.
10297 # If you have a DENORM and an INF or ZERO, just force the DENORM's j-bit to a one
10298 # and use the fcmp_norm routine.
10299 # If you have a DENORM and a NORM with opposite signs, then use fcmp_norm, also.
10300 # But with a DENORM and a NORM of the same sign, the neg bit is set if the
10301 # (1) signs are (+) and the DENORM is the dst or
10302 # (2) signs are (-) and the DENORM is the src
10303 #
10305 fcmp_dnrm_s:
10312 bra.w fcmp_norm
10314 fcmp_dnrm_d:
10321 bra.w fcmp_norm
10323 fcmp_dnrm_sd:
10336 bra.w fcmp_norm
10338 fcmp_nrm_dnrm:
10342 bmi.w fcmp_dnrm_s
10344 # signs are the same, so must determine the answer ourselves.
10347 rts
10348 fcmp_nrm_dnrm_m:
10350 rts
10352 fcmp_dnrm_nrm:
10356 bmi.w fcmp_dnrm_d
10358 # signs are the same, so must determine the answer ourselves.
10361 rts
10362 fcmp_dnrm_nrm_m:
10364 rts
10366 #########################################################################
10367 # XDEF **************************************************************** #
10368 # fsglmul(): emulates the fsglmul instruction #
10369 # #
10370 # XREF **************************************************************** #
10371 # scale_to_zero_src() - scale src exponent to zero #
10372 # scale_to_zero_dst() - scale dst exponent to zero #
10373 # unf_res4() - return default underflow result for sglop #
10374 # ovf_res() - return default overflow result #
10375 # res_qnan() - return QNAN result #
10376 # res_snan() - return SNAN result #
10377 # #
10378 # INPUT *************************************************************** #
10379 # a0 = pointer to extended precision source operand #
10380 # a1 = pointer to extended precision destination operand #
10381 # d0 rnd prec,mode #
10382 # #
10383 # OUTPUT ************************************************************** #
10384 # fp0 = result #
10385 # fp1 = EXOP (if exception occurred) #
10386 # #
10387 # ALGORITHM *********************************************************** #
10388 # Handle NANs, infinities, and zeroes as special cases. Divide #
10389 # norms/denorms into ext/sgl/dbl precision. #
10390 # For norms/denorms, scale the exponents such that a multiply #
10391 # instruction won't cause an exception. Use the regular fsglmul to #
10392 # compute a result. Check if the regular operands would have taken #
10393 # an exception. If so, return the default overflow/underflow result #
10394 # and return the EXOP if exceptions are enabled. Else, scale the #
10395 # result operand to the proper exponent. #
10396 # #
10397 #########################################################################
10399 global fsglmul
10400 fsglmul:
10403 clr.w %d1
10408 bne.w fsglmul_not_norm # optimize on non-norm input
10410 fsglmul_norm:
10427 beq.w fsglmul_may_ovfl # result may rnd to overflow
10428 blt.w fsglmul_ovfl # result will overflow
10431 beq.w fsglmul_may_unfl # result may rnd to no unfl
10432 bgt.w fsglmul_unfl # result will underflow
10434 fsglmul_normal:
10447 fsglmul_normal_exit:
10459 rts
10461 fsglmul_ovfl:
10474 fsglmul_ovfl_tst:
10476 # save setting this until now because this is where fsglmul_may_ovfl may jump in
10483 fsglmul_ovfl_dis:
10491 rts
10493 fsglmul_ovfl_ena:
10508 bra.b fsglmul_ovfl_dis
10510 fsglmul_may_ovfl:
10525 fbge.w fsglmul_ovfl_tst # yes; overflow has occurred
10527 # no, it didn't overflow; we have correct result
10528 bra.w fsglmul_normal_exit
10530 fsglmul_unfl:
10549 fsglmul_unfl_dis:
10557 rts
10559 #
10560 # UNFL is enabled.
10561 #
10562 fsglmul_unfl_ena:
10585 bra.w fsglmul_unfl_dis
10587 fsglmul_may_unfl:
10602 fbgt.w fsglmul_normal_exit # no; no underflow occurred
10603 fblt.w fsglmul_unfl # yes; underflow occurred
10605 #
10606 # we still don't know if underflow occurred. result is ~ equal to 2. but,
10607 # we don't know if the result was an underflow that rounded up to a 2 or
10608 # a normalized number that rounded down to a 2. so, redo the entire operation
10609 # using RZ as the rounding mode to see what the pre-rounded result is.
10610 # this case should be relatively rare.
10611 #
10626 fbge.w fsglmul_normal_exit # no; no underflow occurred
10627 bra.w fsglmul_unfl # yes, underflow occurred
10629 ##############################################################################
10631 #
10632 # Single Precision Multiply: inputs are not both normalized; what are they?
10633 #
10634 fsglmul_not_norm:
10639 tbl_fsglmul_op:
10694 fsglmul_res_operr:
10695 bra.l res_operr
10696 fsglmul_res_snan:
10697 bra.l res_snan
10698 fsglmul_res_qnan:
10699 bra.l res_qnan
10700 fsglmul_zero:
10701 bra.l fmul_zero
10702 fsglmul_inf_src:
10703 bra.l fmul_inf_src
10704 fsglmul_inf_dst:
10705 bra.l fmul_inf_dst
10707 #########################################################################
10708 # XDEF **************************************************************** #
10709 # fsgldiv(): emulates the fsgldiv instruction #
10710 # #
10711 # XREF **************************************************************** #
10712 # scale_to_zero_src() - scale src exponent to zero #
10713 # scale_to_zero_dst() - scale dst exponent to zero #
10714 # unf_res4() - return default underflow result for sglop #
10715 # ovf_res() - return default overflow result #
10716 # res_qnan() - return QNAN result #
10717 # res_snan() - return SNAN result #
10718 # #
10719 # INPUT *************************************************************** #
10720 # a0 = pointer to extended precision source operand #
10721 # a1 = pointer to extended precision destination operand #
10722 # d0 rnd prec,mode #
10723 # #
10724 # OUTPUT ************************************************************** #
10725 # fp0 = result #
10726 # fp1 = EXOP (if exception occurred) #
10727 # #
10728 # ALGORITHM *********************************************************** #
10729 # Handle NANs, infinities, and zeroes as special cases. Divide #
10730 # norms/denorms into ext/sgl/dbl precision. #
10731 # For norms/denorms, scale the exponents such that a divide #
10732 # instruction won't cause an exception. Use the regular fsgldiv to #
10733 # compute a result. Check if the regular operands would have taken #
10734 # an exception. If so, return the default overflow/underflow result #
10735 # and return the EXOP if exceptions are enabled. Else, scale the #
10736 # result operand to the proper exponent. #
10737 # #
10738 #########################################################################
10740 global fsgldiv
10741 fsgldiv:
10744 clr.w %d1
10749 bne.w fsgldiv_not_norm # optimize on non-norm input
10751 #
10752 # DIVIDE: NORMs and DENORMs ONLY!
10753 #
10754 fsgldiv_norm:
10775 ble.w fsgldiv_may_ovfl
10778 beq.w fsgldiv_may_unfl # maybe
10779 bgt.w fsgldiv_unfl # yes; go handle underflow
10781 fsgldiv_normal:
10794 fsgldiv_normal_exit:
10806 rts
10808 fsgldiv_may_ovfl:
10827 blt.b fsgldiv_normal_exit
10829 fsgldiv_ovfl_tst:
10836 fsgldiv_ovfl_dis:
10844 rts
10846 fsgldiv_ovfl_ena:
10861 bra.b fsgldiv_ovfl_dis
10863 fsgldiv_unfl:
10882 fsgldiv_unfl_dis:
10890 rts
10892 #
10893 # UNFL is enabled.
10894 #
10895 fsgldiv_unfl_ena:
10918 bra.b fsgldiv_unfl_dis
10920 #
10921 # the divide operation MAY underflow:
10922 #
10923 fsgldiv_may_unfl:
10938 fbgt.w fsgldiv_normal_exit # no; no underflow occurred
10939 fblt.w fsgldiv_unfl # yes; underflow occurred
10941 #
10942 # we still don't know if underflow occurred. result is ~ equal to 1. but,
10943 # we don't know if the result was an underflow that rounded up to a 1
10944 # or a normalized number that rounded down to a 1. so, redo the entire
10945 # operation using RZ as the rounding mode to see what the pre-rounded
10946 # result is. this case should be relatively rare.
10947 #
10961 fbge.w fsgldiv_normal_exit # no; no underflow occurred
10962 bra.w fsgldiv_unfl # yes; underflow occurred
10964 ############################################################################
10966 #
10967 # Divide: inputs are not both normalized; what are they?
10968 #
10969 fsgldiv_not_norm:
10974 tbl_fsgldiv_op:
11029 fsgldiv_res_qnan:
11030 bra.l res_qnan
11031 fsgldiv_res_snan:
11032 bra.l res_snan
11033 fsgldiv_res_operr:
11034 bra.l res_operr
11035 fsgldiv_inf_load:
11036 bra.l fdiv_inf_load
11037 fsgldiv_zero_load:
11038 bra.l fdiv_zero_load
11039 fsgldiv_inf_dst:
11040 bra.l fdiv_inf_dst
11042 #########################################################################
11043 # XDEF **************************************************************** #
11044 # fadd(): emulates the fadd instruction #
11045 # fsadd(): emulates the fadd instruction #
11046 # fdadd(): emulates the fdadd instruction #
11047 # #
11048 # XREF **************************************************************** #
11049 # addsub_scaler2() - scale the operands so they won't take exc #
11050 # ovf_res() - return default overflow result #
11051 # unf_res() - return default underflow result #
11052 # res_qnan() - set QNAN result #
11053 # res_snan() - set SNAN result #
11054 # res_operr() - set OPERR result #
11055 # scale_to_zero_src() - set src operand exponent equal to zero #
11056 # scale_to_zero_dst() - set dst operand exponent equal to zero #
11057 # #
11058 # INPUT *************************************************************** #
11059 # a0 = pointer to extended precision source operand #
11060 # a1 = pointer to extended precision destination operand #
11061 # #
11062 # OUTPUT ************************************************************** #
11063 # fp0 = result #
11064 # fp1 = EXOP (if exception occurred) #
11065 # #
11066 # ALGORITHM *********************************************************** #
11067 # Handle NANs, infinities, and zeroes as special cases. Divide #
11068 # norms into extended, single, and double precision. #
11069 # Do addition after scaling exponents such that exception won't #
11070 # occur. Then, check result exponent to see if exception would have #
11071 # occurred. If so, return default result and maybe EXOP. Else, insert #
11072 # the correct result exponent and return. Set FPSR bits as appropriate. #
11073 # #
11074 #########################################################################
11076 global fsadd
11077 fsadd:
11080 bra.b fadd
11082 global fdadd
11083 fdadd:
11087 global fadd
11091 clr.w %d1
11096 bne.w fadd_not_norm # optimize on non-norm input
11098 #
11099 # ADD: norms and denorms
11100 #
11101 fadd_norm:
11104 fadd_zero_entry:
11117 fbeq.w fadd_zero_exit # if result is zero, end now
11134 blt.w fadd_unfl # yes
11135 beq.w fadd_may_unfl # maybe; go find out
11137 fadd_normal:
11146 rts
11148 fadd_zero_exit:
11149 # fmov.s &0x00000000,%fp0 # return zero in fp0
11150 rts
11152 tbl_fadd_ovfl:
11157 tbl_fadd_unfl:
11162 fadd_ovfl:
11170 fadd_ovfl_dis:
11178 rts
11180 fadd_ovfl_ena:
11185 fadd_ovfl_ena_cont:
11194 bra.b fadd_ovfl_dis
11196 fadd_ovfl_ena_sd:
11209 bra.b fadd_ovfl_ena_cont
11211 fadd_unfl:
11232 fadd_unfl_dis:
11241 rts
11243 fadd_unfl_ena:
11252 fadd_unfl_ena_cont:
11270 bra.w fadd_unfl_dis
11272 fadd_unfl_ena_sd:
11277 bra.b fadd_unfl_ena_cont
11279 #
11280 # result is equal to the smallest normalized number in the selected precision
11281 # if the precision is extended, this result could not have come from an
11282 # underflow that rounded up.
11283 #
11284 fadd_may_unfl:
11287 beq.w fadd_normal # yes; no underflow occurred
11291 bne.w fadd_normal # no; no underflow occurred
11294 bne.w fadd_normal # no; no underflow occurred
11297 beq.w fadd_normal # no; no underflow occurred
11299 #
11300 # ok, so now the result has a exponent equal to the smallest normalized
11301 # exponent for the selected precision. also, the mantissa is equal to
11302 # 0x8000000000000000 and this mantissa is the result of rounding non-zero
11303 # g,r,s.
11304 # now, we must determine whether the pre-rounded result was an underflow
11305 # rounded "up" or a normalized number rounded "down".
11306 # so, we do this be re-executing the add using RZ as the rounding mode and
11307 # seeing if the new result is smaller or equal to the current result.
11308 #
11325 fbgt.w fadd_unfl # yes; it's an underflow
11326 bra.w fadd_normal # no; it's not an underflow
11328 ##########################################################################
11330 #
11331 # Add: inputs are not both normalized; what are they?
11332 #
11333 fadd_not_norm:
11338 tbl_fadd_op:
11393 fadd_res_qnan:
11394 bra.l res_qnan
11395 fadd_res_snan:
11396 bra.l res_snan
11398 #
11399 # both operands are ZEROes
11400 #
11401 fadd_zero_2:
11405 bmi.w fadd_zero_2_chk_rm # weed out (-ZERO)+(+ZERO)
11407 # the signs are the same. so determine whether they are positive or negative
11408 # and return the appropriately signed zero.
11413 rts
11415 #
11416 # the ZEROes have opposite signs:
11417 # - therefore, we return +ZERO if the rounding modes are RN,RZ, or RP.
11418 # - -ZERO is returned in the case of RM.
11419 #
11420 fadd_zero_2_chk_rm:
11427 rts
11429 fadd_zero_rm:
11432 rts
11434 #
11435 # one operand is a ZERO and the other is a DENORM or NORM. scale
11436 # the DENORM or NORM and jump to the regular fadd routine.
11437 #
11438 fadd_zero_dst:
11446 bra.w fadd_zero_entry # go execute fadd
11448 fadd_zero_src:
11456 bra.w fadd_zero_entry # go execute fadd
11458 #
11459 # both operands are INFs. an OPERR will result if the INFs have
11460 # different signs. else, an INF of the same sign is returned
11461 #
11462 fadd_inf_2:
11468 # ok, so it's not an OPERR. but, we do have to remember to return the
11469 # src INF since that's where the 881/882 gets the j-bit from...
11471 #
11472 # operands are INF and one of {ZERO, INF, DENORM, NORM}
11473 #
11474 fadd_inf_src:
11479 rts
11481 #
11482 # operands are INF and one of {ZERO, INF, DENORM, NORM}
11483 #
11484 fadd_inf_dst:
11489 rts
11491 fadd_inf_done:
11493 rts
11495 #########################################################################
11496 # XDEF **************************************************************** #
11497 # fsub(): emulates the fsub instruction #
11498 # fssub(): emulates the fssub instruction #
11499 # fdsub(): emulates the fdsub instruction #
11500 # #
11501 # XREF **************************************************************** #
11502 # addsub_scaler2() - scale the operands so they won't take exc #
11503 # ovf_res() - return default overflow result #
11504 # unf_res() - return default underflow result #
11505 # res_qnan() - set QNAN result #
11506 # res_snan() - set SNAN result #
11507 # res_operr() - set OPERR result #
11508 # scale_to_zero_src() - set src operand exponent equal to zero #
11509 # scale_to_zero_dst() - set dst operand exponent equal to zero #
11510 # #
11511 # INPUT *************************************************************** #
11512 # a0 = pointer to extended precision source operand #
11513 # a1 = pointer to extended precision destination operand #
11514 # #
11515 # OUTPUT ************************************************************** #
11516 # fp0 = result #
11517 # fp1 = EXOP (if exception occurred) #
11518 # #
11519 # ALGORITHM *********************************************************** #
11520 # Handle NANs, infinities, and zeroes as special cases. Divide #
11521 # norms into extended, single, and double precision. #
11522 # Do subtraction after scaling exponents such that exception won't#
11523 # occur. Then, check result exponent to see if exception would have #
11524 # occurred. If so, return default result and maybe EXOP. Else, insert #
11525 # the correct result exponent and return. Set FPSR bits as appropriate. #
11526 # #
11527 #########################################################################
11529 global fssub
11530 fssub:
11533 bra.b fsub
11535 global fdsub
11536 fdsub:
11540 global fsub
11544 clr.w %d1
11549 bne.w fsub_not_norm # optimize on non-norm input
11551 #
11552 # SUB: norms and denorms
11553 #
11554 fsub_norm:
11557 fsub_zero_entry:
11570 fbeq.w fsub_zero_exit # if result zero, end now
11587 blt.w fsub_unfl # yes
11588 beq.w fsub_may_unfl # maybe; go find out
11590 fsub_normal:
11599 rts
11601 fsub_zero_exit:
11602 # fmov.s &0x00000000,%fp0 # return zero in fp0
11603 rts
11605 tbl_fsub_ovfl:
11610 tbl_fsub_unfl:
11615 fsub_ovfl:
11623 fsub_ovfl_dis:
11631 rts
11633 fsub_ovfl_ena:
11638 fsub_ovfl_ena_cont:
11647 bra.b fsub_ovfl_dis
11649 fsub_ovfl_ena_sd:
11662 bra.b fsub_ovfl_ena_cont
11664 fsub_unfl:
11685 fsub_unfl_dis:
11694 rts
11696 fsub_unfl_ena:
11705 fsub_unfl_ena_cont:
11723 bra.w fsub_unfl_dis
11725 fsub_unfl_ena_sd:
11730 bra.b fsub_unfl_ena_cont
11732 #
11733 # result is equal to the smallest normalized number in the selected precision
11734 # if the precision is extended, this result could not have come from an
11735 # underflow that rounded up.
11736 #
11737 fsub_may_unfl:
11740 beq.w fsub_normal # yes; no underflow occurred
11744 bne.w fsub_normal # no; no underflow occurred
11747 bne.w fsub_normal # no; no underflow occurred
11750 beq.w fsub_normal # no; no underflow occurred
11752 #
11753 # ok, so now the result has a exponent equal to the smallest normalized
11754 # exponent for the selected precision. also, the mantissa is equal to
11755 # 0x8000000000000000 and this mantissa is the result of rounding non-zero
11756 # g,r,s.
11757 # now, we must determine whether the pre-rounded result was an underflow
11758 # rounded "up" or a normalized number rounded "down".
11759 # so, we do this be re-executing the add using RZ as the rounding mode and
11760 # seeing if the new result is smaller or equal to the current result.
11761 #
11778 fbgt.w fsub_unfl # yes; it's an underflow
11779 bra.w fsub_normal # no; it's not an underflow
11781 ##########################################################################
11783 #
11784 # Sub: inputs are not both normalized; what are they?
11785 #
11786 fsub_not_norm:
11791 tbl_fsub_op:
11846 fsub_res_qnan:
11847 bra.l res_qnan
11848 fsub_res_snan:
11849 bra.l res_snan
11851 #
11852 # both operands are ZEROes
11853 #
11854 fsub_zero_2:
11858 bpl.b fsub_zero_2_chk_rm
11860 # the signs are opposite, so, return a ZERO w/ the sign of the dst ZERO
11865 rts
11867 #
11868 # the ZEROes have the same signs:
11869 # - therefore, we return +ZERO if the rounding mode is RN,RZ, or RP
11870 # - -ZERO is returned in the case of RM.
11871 #
11872 fsub_zero_2_chk_rm:
11879 rts
11881 fsub_zero_2_rm:
11884 rts
11886 #
11887 # one operand is a ZERO and the other is a DENORM or a NORM.
11888 # scale the DENORM or NORM and jump to the regular fsub routine.
11889 #
11890 fsub_zero_dst:
11898 bra.w fsub_zero_entry # go execute fsub
11900 fsub_zero_src:
11908 bra.w fsub_zero_entry # go execute fsub
11910 #
11911 # both operands are INFs. an OPERR will result if the INFs have the
11912 # same signs. else,
11913 #
11914 fsub_inf_2:
11920 # ok, so it's not an OPERR. but we do have to remember to return
11921 # the src INF since that's where the 881/882 gets the j-bit.
11923 fsub_inf_src:
11926 fbge.w fsub_inf_done # sign is now positive
11928 rts
11930 fsub_inf_dst:
11935 rts
11937 fsub_inf_done:
11939 rts
11941 #########################################################################
11942 # XDEF **************************************************************** #
11943 # fsqrt(): emulates the fsqrt instruction #
11944 # fssqrt(): emulates the fssqrt instruction #
11945 # fdsqrt(): emulates the fdsqrt instruction #
11946 # #
11947 # XREF **************************************************************** #
11948 # scale_sqrt() - scale the source operand #
11949 # unf_res() - return default underflow result #
11950 # ovf_res() - return default overflow result #
11951 # res_qnan_1op() - return QNAN result #
11952 # res_snan_1op() - return SNAN result #
11953 # #
11954 # INPUT *************************************************************** #
11955 # a0 = pointer to extended precision source operand #
11956 # d0 rnd prec,mode #
11957 # #
11958 # OUTPUT ************************************************************** #
11959 # fp0 = result #
11960 # fp1 = EXOP (if exception occurred) #
11961 # #
11962 # ALGORITHM *********************************************************** #
11963 # Handle NANs, infinities, and zeroes as special cases. Divide #
11964 # norms/denorms into ext/sgl/dbl precision. #
11965 # For norms/denorms, scale the exponents such that a sqrt #
11966 # instruction won't cause an exception. Use the regular fsqrt to #
11967 # compute a result. Check if the regular operands would have taken #
11968 # an exception. If so, return the default overflow/underflow result #
11969 # and return the EXOP if exceptions are enabled. Else, scale the #
11970 # result operand to the proper exponent. #
11971 # #
11972 #########################################################################
11974 global fssqrt
11975 fssqrt:
11978 bra.b fsqrt
11980 global fdsqrt
11981 fdsqrt:
11985 global fsqrt
11988 clr.w %d1
11990 bne.w fsqrt_not_norm # optimize on non-norm input
11992 #
11993 # SQUARE ROOT: norms and denorms ONLY!
11994 #
11995 fsqrt_norm:
12010 rts
12012 fsqrt_denorm:
12025 bra.w fsqrt_sd_normal
12027 #
12028 # operand is either single or double
12029 #
12030 fsqrt_not_ext:
12032 bne.w fsqrt_dbl
12034 #
12035 # operand is to be rounded to single precision
12036 #
12037 fsqrt_sgl:
12045 beq.w fsqrt_sd_may_unfl
12046 bgt.w fsqrt_sd_unfl # yes; go handle underflow
12048 beq.w fsqrt_sd_may_ovfl # maybe; go check
12049 blt.w fsqrt_sd_ovfl # yes; go handle overflow
12051 #
12052 # operand will NOT overflow or underflow when moved in to the fp reg file
12053 #
12054 fsqrt_sd_normal:
12065 fsqrt_sd_normal_exit:
12077 rts
12079 #
12080 # operand is to be rounded to double precision
12081 #
12082 fsqrt_dbl:
12090 beq.w fsqrt_sd_may_unfl
12093 beq.w fsqrt_sd_may_ovfl # maybe; go check
12094 blt.w fsqrt_sd_ovfl # yes; go handle overflow
12095 bra.w fsqrt_sd_normal # no; ho handle normalized op
12097 # we're on the line here and the distinguising characteristic is whether
12098 # the exponent is 3fff or 3ffe. if it's 3ffe, then it's a safe number
12099 # elsewise fall through to underflow.
12100 fsqrt_sd_may_unfl:
12102 bne.w fsqrt_sd_normal # yes, so no underflow
12104 #
12105 # operand WILL underflow when moved in to the fp register file
12106 #
12107 fsqrt_sd_unfl:
12120 # if underflow or inexact is enabled, go calculate EXOP first.
12125 fsqrt_sd_unfl_dis:
12133 rts
12135 #
12136 # operand will underflow AND underflow is enabled.
12137 # therefore, we must return the result rounded to extended precision.
12138 #
12139 fsqrt_sd_unfl_ena:
12155 bra.b fsqrt_sd_unfl_dis
12157 #
12158 # operand WILL overflow.
12159 #
12160 fsqrt_sd_ovfl:
12171 fsqrt_sd_ovfl_tst:
12178 #
12179 # OVFL is not enabled; therefore, we must create the default result by
12180 # calling ovf_res().
12181 #
12182 fsqrt_sd_ovfl_dis:
12189 rts
12191 #
12192 # OVFL is enabled.
12193 # the INEX2 bit has already been updated by the round to the correct precision.
12194 # now, round to extended(and don't alter the FPSR).
12195 #
12196 fsqrt_sd_ovfl_ena:
12209 bra.b fsqrt_sd_ovfl_dis
12211 #
12212 # the move in MAY underflow. so...
12213 #
12214 fsqrt_sd_may_ovfl:
12216 bne.w fsqrt_sd_ovfl # yes, so overflow
12230 fbge.w fsqrt_sd_ovfl_tst # yes; overflow has occurred
12232 # no, it didn't overflow; we have correct result
12233 bra.w fsqrt_sd_normal_exit
12235 ##########################################################################
12237 #
12238 # input is not normalized; what is it?
12239 #
12240 fsqrt_not_norm:
12242 beq.w fsqrt_denorm
12244 beq.b fsqrt_zero
12246 beq.b fsqrt_inf
12248 beq.l res_snan_1op
12249 bra.l res_qnan_1op
12251 #
12252 # fsqrt(+0) = +0
12253 # fsqrt(-0) = -0
12254 # fsqrt(+INF) = +INF
12255 # fsqrt(-INF) = OPERR
12256 #
12257 fsqrt_zero:
12260 fsqrt_zero_p:
12263 rts
12264 fsqrt_zero_m:
12267 rts
12269 fsqrt_inf:
12272 fsqrt_inf_p:
12275 rts
12277 #########################################################################
12278 # XDEF **************************************************************** #
12279 # fetch_dreg(): fetch register according to index in d1 #
12280 # #
12281 # XREF **************************************************************** #
12282 # None #
12283 # #
12284 # INPUT *************************************************************** #
12285 # d1 = index of register to fetch from #
12286 # #
12287 # OUTPUT ************************************************************** #
12288 # d0 = value of register fetched #
12289 # #
12290 # ALGORITHM *********************************************************** #
12291 # According to the index value in d1 which can range from zero #
12292 # to fifteen, load the corresponding register file value (where #
12293 # address register indexes start at 8). D0/D1/A0/A1/A6/A7 are on the #
12294 # stack. The rest should still be in their original places. #
12295 # #
12296 #########################################################################
12298 # this routine leaves d1 intact for subsequent store_dreg calls.
12299 global fetch_dreg
12300 fetch_dreg:
12304 tbl_fdreg:
12305 short fdreg0 - tbl_fdreg
12306 short fdreg1 - tbl_fdreg
12307 short fdreg2 - tbl_fdreg
12308 short fdreg3 - tbl_fdreg
12309 short fdreg4 - tbl_fdreg
12310 short fdreg5 - tbl_fdreg
12311 short fdreg6 - tbl_fdreg
12312 short fdreg7 - tbl_fdreg
12313 short fdreg8 - tbl_fdreg
12314 short fdreg9 - tbl_fdreg
12315 short fdrega - tbl_fdreg
12316 short fdregb - tbl_fdreg
12317 short fdregc - tbl_fdreg
12318 short fdregd - tbl_fdreg
12319 short fdrege - tbl_fdreg
12320 short fdregf - tbl_fdreg
12322 fdreg0:
12324 rts
12325 fdreg1:
12327 rts
12328 fdreg2:
12330 rts
12331 fdreg3:
12333 rts
12334 fdreg4:
12336 rts
12337 fdreg5:
12339 rts
12340 fdreg6:
12342 rts
12343 fdreg7:
12345 rts
12346 fdreg8:
12348 rts
12349 fdreg9:
12351 rts
12352 fdrega:
12354 rts
12355 fdregb:
12357 rts
12358 fdregc:
12360 rts
12361 fdregd:
12363 rts
12364 fdrege:
12366 rts
12367 fdregf:
12369 rts
12371 #########################################################################
12372 # XDEF **************************************************************** #
12373 # store_dreg_l(): store longword to data register specified by d1 #
12374 # #
12375 # XREF **************************************************************** #
12376 # None #
12377 # #
12378 # INPUT *************************************************************** #
12379 # d0 = longowrd value to store #
12380 # d1 = index of register to fetch from #
12381 # #
12382 # OUTPUT ************************************************************** #
12383 # (data register is updated) #
12384 # #
12385 # ALGORITHM *********************************************************** #
12386 # According to the index value in d1, store the longword value #
12387 # in d0 to the corresponding data register. D0/D1 are on the stack #
12388 # while the rest are in their initial places. #
12389 # #
12390 #########################################################################
12392 global store_dreg_l
12393 store_dreg_l:
12397 tbl_sdregl:
12398 short sdregl0 - tbl_sdregl
12399 short sdregl1 - tbl_sdregl
12400 short sdregl2 - tbl_sdregl
12401 short sdregl3 - tbl_sdregl
12402 short sdregl4 - tbl_sdregl
12403 short sdregl5 - tbl_sdregl
12404 short sdregl6 - tbl_sdregl
12405 short sdregl7 - tbl_sdregl
12407 sdregl0:
12409 rts
12410 sdregl1:
12412 rts
12413 sdregl2:
12415 rts
12416 sdregl3:
12418 rts
12419 sdregl4:
12421 rts
12422 sdregl5:
12424 rts
12425 sdregl6:
12427 rts
12428 sdregl7:
12430 rts
12432 #########################################################################
12433 # XDEF **************************************************************** #
12434 # store_dreg_w(): store word to data register specified by d1 #
12435 # #
12436 # XREF **************************************************************** #
12437 # None #
12438 # #
12439 # INPUT *************************************************************** #
12440 # d0 = word value to store #
12441 # d1 = index of register to fetch from #
12442 # #
12443 # OUTPUT ************************************************************** #
12444 # (data register is updated) #
12445 # #
12446 # ALGORITHM *********************************************************** #
12447 # According to the index value in d1, store the word value #
12448 # in d0 to the corresponding data register. D0/D1 are on the stack #
12449 # while the rest are in their initial places. #
12450 # #
12451 #########################################################################
12453 global store_dreg_w
12454 store_dreg_w:
12458 tbl_sdregw:
12459 short sdregw0 - tbl_sdregw
12460 short sdregw1 - tbl_sdregw
12461 short sdregw2 - tbl_sdregw
12462 short sdregw3 - tbl_sdregw
12463 short sdregw4 - tbl_sdregw
12464 short sdregw5 - tbl_sdregw
12465 short sdregw6 - tbl_sdregw
12466 short sdregw7 - tbl_sdregw
12468 sdregw0:
12470 rts
12471 sdregw1:
12473 rts
12474 sdregw2:
12476 rts
12477 sdregw3:
12479 rts
12480 sdregw4:
12482 rts
12483 sdregw5:
12485 rts
12486 sdregw6:
12488 rts
12489 sdregw7:
12491 rts
12493 #########################################################################
12494 # XDEF **************************************************************** #
12495 # store_dreg_b(): store byte to data register specified by d1 #
12496 # #
12497 # XREF **************************************************************** #
12498 # None #
12499 # #
12500 # INPUT *************************************************************** #
12501 # d0 = byte value to store #
12502 # d1 = index of register to fetch from #
12503 # #
12504 # OUTPUT ************************************************************** #
12505 # (data register is updated) #
12506 # #
12507 # ALGORITHM *********************************************************** #
12508 # According to the index value in d1, store the byte value #
12509 # in d0 to the corresponding data register. D0/D1 are on the stack #
12510 # while the rest are in their initial places. #
12511 # #
12512 #########################################################################
12514 global store_dreg_b
12515 store_dreg_b:
12519 tbl_sdregb:
12520 short sdregb0 - tbl_sdregb
12521 short sdregb1 - tbl_sdregb
12522 short sdregb2 - tbl_sdregb
12523 short sdregb3 - tbl_sdregb
12524 short sdregb4 - tbl_sdregb
12525 short sdregb5 - tbl_sdregb
12526 short sdregb6 - tbl_sdregb
12527 short sdregb7 - tbl_sdregb
12529 sdregb0:
12531 rts
12532 sdregb1:
12534 rts
12535 sdregb2:
12537 rts
12538 sdregb3:
12540 rts
12541 sdregb4:
12543 rts
12544 sdregb5:
12546 rts
12547 sdregb6:
12549 rts
12550 sdregb7:
12552 rts
12554 #########################################################################
12555 # XDEF **************************************************************** #
12556 # inc_areg(): increment an address register by the value in d0 #
12557 # #
12558 # XREF **************************************************************** #
12559 # None #
12560 # #
12561 # INPUT *************************************************************** #
12562 # d0 = amount to increment by #
12563 # d1 = index of address register to increment #
12564 # #
12565 # OUTPUT ************************************************************** #
12566 # (address register is updated) #
12567 # #
12568 # ALGORITHM *********************************************************** #
12569 # Typically used for an instruction w/ a post-increment <ea>, #
12570 # this routine adds the increment value in d0 to the address register #
12571 # specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
12572 # in their original places. #
12573 # For a7, if the increment amount is one, then we have to #
12574 # increment by two. For any a7 update, set the mia7_flag so that if #
12575 # an access error exception occurs later in emulation, this address #
12576 # register update can be undone. #
12577 # #
12578 #########################################################################
12580 global inc_areg
12581 inc_areg:
12585 tbl_iareg:
12586 short iareg0 - tbl_iareg
12587 short iareg1 - tbl_iareg
12588 short iareg2 - tbl_iareg
12589 short iareg3 - tbl_iareg
12590 short iareg4 - tbl_iareg
12591 short iareg5 - tbl_iareg
12592 short iareg6 - tbl_iareg
12593 short iareg7 - tbl_iareg
12596 rts
12598 rts
12600 rts
12602 rts
12604 rts
12606 rts
12608 rts
12611 beq.b iareg7b
12613 rts
12614 iareg7b:
12616 rts
12618 #########################################################################
12619 # XDEF **************************************************************** #
12620 # dec_areg(): decrement an address register by the value in d0 #
12621 # #
12622 # XREF **************************************************************** #
12623 # None #
12624 # #
12625 # INPUT *************************************************************** #
12626 # d0 = amount to decrement by #
12627 # d1 = index of address register to decrement #
12628 # #
12629 # OUTPUT ************************************************************** #
12630 # (address register is updated) #
12631 # #
12632 # ALGORITHM *********************************************************** #
12633 # Typically used for an instruction w/ a pre-decrement <ea>, #
12634 # this routine adds the decrement value in d0 to the address register #
12635 # specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
12636 # in their original places. #
12637 # For a7, if the decrement amount is one, then we have to #
12638 # decrement by two. For any a7 update, set the mda7_flag so that if #
12639 # an access error exception occurs later in emulation, this address #
12640 # register update can be undone. #
12641 # #
12642 #########################################################################
12644 global dec_areg
12645 dec_areg:
12649 tbl_dareg:
12650 short dareg0 - tbl_dareg
12651 short dareg1 - tbl_dareg
12652 short dareg2 - tbl_dareg
12653 short dareg3 - tbl_dareg
12654 short dareg4 - tbl_dareg
12655 short dareg5 - tbl_dareg
12656 short dareg6 - tbl_dareg
12657 short dareg7 - tbl_dareg
12660 rts
12662 rts
12664 rts
12666 rts
12668 rts
12670 rts
12672 rts
12675 beq.b dareg7b
12677 rts
12678 dareg7b:
12680 rts
12682 ##############################################################################
12684 #########################################################################
12685 # XDEF **************************************************************** #
12686 # load_fpn1(): load FP register value into FP_SRC(a6). #
12687 # #
12688 # XREF **************************************************************** #
12689 # None #
12690 # #
12691 # INPUT *************************************************************** #
12692 # d0 = index of FP register to load #
12693 # #
12694 # OUTPUT ************************************************************** #
12695 # FP_SRC(a6) = value loaded from FP register file #
12696 # #
12697 # ALGORITHM *********************************************************** #
12698 # Using the index in d0, load FP_SRC(a6) with a number from the #
12699 # FP register file. #
12700 # #
12701 #########################################################################
12703 global load_fpn1
12704 load_fpn1:
12708 tbl_load_fpn1:
12709 short load_fpn1_0 - tbl_load_fpn1
12710 short load_fpn1_1 - tbl_load_fpn1
12711 short load_fpn1_2 - tbl_load_fpn1
12712 short load_fpn1_3 - tbl_load_fpn1
12713 short load_fpn1_4 - tbl_load_fpn1
12714 short load_fpn1_5 - tbl_load_fpn1
12715 short load_fpn1_6 - tbl_load_fpn1
12716 short load_fpn1_7 - tbl_load_fpn1
12718 load_fpn1_0:
12723 rts
12724 load_fpn1_1:
12729 rts
12730 load_fpn1_2:
12733 rts
12734 load_fpn1_3:
12737 rts
12738 load_fpn1_4:
12741 rts
12742 load_fpn1_5:
12745 rts
12746 load_fpn1_6:
12749 rts
12750 load_fpn1_7:
12753 rts
12755 #############################################################################
12757 #########################################################################
12758 # XDEF **************************************************************** #
12759 # load_fpn2(): load FP register value into FP_DST(a6). #
12760 # #
12761 # XREF **************************************************************** #
12762 # None #
12763 # #
12764 # INPUT *************************************************************** #
12765 # d0 = index of FP register to load #
12766 # #
12767 # OUTPUT ************************************************************** #
12768 # FP_DST(a6) = value loaded from FP register file #
12769 # #
12770 # ALGORITHM *********************************************************** #
12771 # Using the index in d0, load FP_DST(a6) with a number from the #
12772 # FP register file. #
12773 # #
12774 #########################################################################
12776 global load_fpn2
12777 load_fpn2:
12781 tbl_load_fpn2:
12782 short load_fpn2_0 - tbl_load_fpn2
12783 short load_fpn2_1 - tbl_load_fpn2
12784 short load_fpn2_2 - tbl_load_fpn2
12785 short load_fpn2_3 - tbl_load_fpn2
12786 short load_fpn2_4 - tbl_load_fpn2
12787 short load_fpn2_5 - tbl_load_fpn2
12788 short load_fpn2_6 - tbl_load_fpn2
12789 short load_fpn2_7 - tbl_load_fpn2
12791 load_fpn2_0:
12796 rts
12797 load_fpn2_1:
12802 rts
12803 load_fpn2_2:
12806 rts
12807 load_fpn2_3:
12810 rts
12811 load_fpn2_4:
12814 rts
12815 load_fpn2_5:
12818 rts
12819 load_fpn2_6:
12822 rts
12823 load_fpn2_7:
12826 rts
12828 #############################################################################
12830 #########################################################################
12831 # XDEF **************************************************************** #
12832 # store_fpreg(): store an fp value to the fpreg designated d0. #
12833 # #
12834 # XREF **************************************************************** #
12835 # None #
12836 # #
12837 # INPUT *************************************************************** #
12838 # fp0 = extended precision value to store #
12839 # d0 = index of floating-point register #
12840 # #
12841 # OUTPUT ************************************************************** #
12842 # None #
12843 # #
12844 # ALGORITHM *********************************************************** #
12845 # Store the value in fp0 to the FP register designated by the #
12846 # value in d0. The FP number can be DENORM or SNAN so we have to be #
12847 # careful that we don't take an exception here. #
12848 # #
12849 #########################################################################
12851 global store_fpreg
12852 store_fpreg:
12856 tbl_store_fpreg:
12857 short store_fpreg_0 - tbl_store_fpreg
12858 short store_fpreg_1 - tbl_store_fpreg
12859 short store_fpreg_2 - tbl_store_fpreg
12860 short store_fpreg_3 - tbl_store_fpreg
12861 short store_fpreg_4 - tbl_store_fpreg
12862 short store_fpreg_5 - tbl_store_fpreg
12863 short store_fpreg_6 - tbl_store_fpreg
12864 short store_fpreg_7 - tbl_store_fpreg
12866 store_fpreg_0:
12868 rts
12869 store_fpreg_1:
12871 rts
12872 store_fpreg_2:
12875 rts
12876 store_fpreg_3:
12879 rts
12880 store_fpreg_4:
12883 rts
12884 store_fpreg_5:
12887 rts
12888 store_fpreg_6:
12891 rts
12892 store_fpreg_7:
12895 rts
12897 #########################################################################
12898 # XDEF **************************************************************** #
12899 # get_packed(): fetch a packed operand from memory and then #
12900 # convert it to a floating-point binary number. #
12901 # #
12902 # XREF **************************************************************** #
12903 # _dcalc_ea() - calculate the correct <ea> #
12904 # _mem_read() - fetch the packed operand from memory #
12905 # facc_in_x() - the fetch failed so jump to special exit code #
12906 # decbin() - convert packed to binary extended precision #
12907 # #
12908 # INPUT *************************************************************** #
12909 # None #
12910 # #
12911 # OUTPUT ************************************************************** #
12912 # If no failure on _mem_read(): #
12913 # FP_SRC(a6) = packed operand now as a binary FP number #
12914 # #
12915 # ALGORITHM *********************************************************** #
12916 # Get the correct <ea> whihc is the value on the exception stack #
12917 # frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. #
12918 # Then, fetch the operand from memory. If the fetch fails, exit #
12919 # through facc_in_x(). #
12920 # If the packed operand is a ZERO,NAN, or INF, convert it to #
12921 # its binary representation here. Else, call decbin() which will #
12922 # convert the packed value to an extended precision binary value. #
12923 # #
12924 #########################################################################
12926 # the stacked <ea> for packed is correct except for -(An).
12927 # the base reg must be updated for both -(An) and (An)+.
12928 global get_packed
12929 get_packed:
12940 # The packed operand is an INF or a NAN if the exponent field is all ones.
12944 rts # operand is an INF or NAN
12946 # The packed operand is a zero if the mantissa is all zero, else it's
12947 # a normal packed op.
12948 gp_try_zero:
12956 rts # operand is a ZERO
12957 gp_not_spec:
12961 rts
12963 #########################################################################
12964 # decbin(): Converts normalized packed bcd value pointed to by register #
12965 # a0 to extended-precision value in fp0. #
12966 # #
12967 # INPUT *************************************************************** #
12968 # a0 = pointer to normalized packed bcd value #
12969 # #
12970 # OUTPUT ************************************************************** #
12971 # fp0 = exact fp representation of the packed bcd value. #
12972 # #
12973 # ALGORITHM *********************************************************** #
12974 # Expected is a normal bcd (i.e. non-exceptional; all inf, zero, #
12975 # and NaN operands are dispatched without entering this routine) #
12976 # value in 68881/882 format at location (a0). #
12977 # #
12978 # A1. Convert the bcd exponent to binary by successive adds and #
12979 # muls. Set the sign according to SE. Subtract 16 to compensate #
12980 # for the mantissa which is to be interpreted as 17 integer #
12981 # digits, rather than 1 integer and 16 fraction digits. #
12982 # Note: this operation can never overflow. #
12983 # #
12984 # A2. Convert the bcd mantissa to binary by successive #
12985 # adds and muls in FP0. Set the sign according to SM. #
12986 # The mantissa digits will be converted with the decimal point #
12987 # assumed following the least-significant digit. #
12988 # Note: this operation can never overflow. #
12989 # #
12990 # A3. Count the number of leading/trailing zeros in the #
12991 # bcd string. If SE is positive, count the leading zeros; #
12992 # if negative, count the trailing zeros. Set the adjusted #
12993 # exponent equal to the exponent from A1 and the zero count #
12994 # added if SM = 1 and subtracted if SM = 0. Scale the #
12995 # mantissa the equivalent of forcing in the bcd value: #
12996 # #
12997 # SM = 0 a non-zero digit in the integer position #
12998 # SM = 1 a non-zero digit in Mant0, lsd of the fraction #
12999 # #
13000 # this will insure that any value, regardless of its #
13001 # representation (ex. 0.1E2, 1E1, 10E0, 100E-1), is converted #
13002 # consistently. #
13003 # #
13004 # A4. Calculate the factor 10^exp in FP1 using a table of #
13005 # 10^(2^n) values. To reduce the error in forming factors #
13006 # greater than 10^27, a directed rounding scheme is used with #
13007 # tables rounded to RN, RM, and RP, according to the table #
13008 # in the comments of the pwrten section. #
13009 # #
13010 # A5. Form the final binary number by scaling the mantissa by #
13011 # the exponent factor. This is done by multiplying the #
13012 # mantissa in FP0 by the factor in FP1 if the adjusted #
13013 # exponent sign is positive, and dividing FP0 by FP1 if #
13014 # it is negative. #
13015 # #
13016 # Clean up and return. Check if the final mul or div was inexact. #
13017 # If so, set INEX1 in USER_FPSR. #
13018 # #
13019 #########################################################################
13021 #
13022 # PTENRN, PTENRM, and PTENRP are arrays of powers of 10 rounded
13023 # to nearest, minus, and plus, respectively. The tables include
13024 # 10**{1,2,4,8,16,32,64,128,256,512,1024,2048,4096}. No rounding
13025 # is required until the power is greater than 27, however, all
13026 # tables include the first 5 for ease of indexing.
13027 #
13028 RTABLE:
13040 global decbin
13041 decbin:
13050 #
13051 # Calculate exponent:
13052 # 1. Copy bcd value in memory for use as a working copy.
13053 # 2. Calculate absolute value of exponent in d1 by mul and add.
13054 # 3. Correct for exponent sign.
13055 # 4. Subtract 16 to compensate for interpreting the mant as all integer digits.
13056 # (i.e., all digits assumed left of the decimal point.)
13057 #
13058 # Register usage:
13059 #
13060 # calc_e:
13061 # (*) d0: temp digit storage
13062 # (*) d1: accumulator for binary exponent
13063 # (*) d2: digit count
13064 # (*) d3: offset pointer
13065 # ( ) d4: first word of bcd
13066 # ( ) a0: pointer to working bcd value
13067 # ( ) a6: pointer to original bcd value
13068 # (*) FP_SCR1: working copy of original bcd value
13069 # (*) L_SCR1: copy of original exponent word
13070 #
13071 calc_e:
13076 e_gd:
13085 e_pos:
13091 e_save:
13093 #
13094 #
13095 # Calculate mantissa:
13096 # 1. Calculate absolute value of mantissa in fp0 by mul and add.
13097 # 2. Correct for mantissa sign.
13098 # (i.e., all digits assumed left of the decimal point.)
13099 #
13100 # Register usage:
13101 #
13102 # calc_m:
13103 # (*) d0: temp digit storage
13104 # (*) d1: lword counter
13105 # (*) d2: digit count
13106 # (*) d3: offset pointer
13107 # ( ) d4: words 2 and 3 of bcd
13108 # ( ) a0: pointer to working bcd value
13109 # ( ) a6: pointer to original bcd value
13110 # (*) fp0: mantissa accumulator
13111 # ( ) FP_SCR1: working copy of original bcd value
13112 # ( ) L_SCR1: copy of original exponent word
13113 #
13114 calc_m:
13117 #
13118 #
13119 # Since the packed number has a long word between the first & second parts,
13120 # get the integer digit then skip down & get the rest of the
13121 # mantissa. We will unroll the loop once.
13122 #
13125 #
13126 #
13127 # Get the rest of the mantissa.
13128 #
13129 loadlw:
13133 md2b:
13137 #
13138 #
13139 # If all the digits (8) in that long word have been converted (d2=0),
13140 # then inc d1 (=2) to point to the next long word and reset d3 to 0
13141 # to initialize the digit offset, and set d2 to 7 for the digit count;
13142 # else continue with this long word.
13143 #
13146 nextlw:
13150 #
13151 # Check the sign of the mant and make the value in fp0 the same sign.
13152 #
13153 m_sign:
13157 #
13158 # Append/strip zeros:
13159 #
13160 # For adjusted exponents which have an absolute value greater than 27*,
13161 # this routine calculates the amount needed to normalize the mantissa
13162 # for the adjusted exponent. That number is subtracted from the exp
13163 # if the exp was positive, and added if it was negative. The purpose
13164 # of this is to reduce the value of the exponent and the possibility
13165 # of error in calculation of pwrten.
13166 #
13167 # 1. Branch on the sign of the adjusted exponent.
13168 # 2p.(positive exp)
13169 # 2. Check M16 and the digits in lwords 2 and 3 in decending order.
13170 # 3. Add one for each zero encountered until a non-zero digit.
13171 # 4. Subtract the count from the exp.
13172 # 5. Check if the exp has crossed zero in #3 above; make the exp abs
13173 # and set SE.
13174 # 6. Multiply the mantissa by 10**count.
13175 # 2n.(negative exp)
13176 # 2. Check the digits in lwords 3 and 2 in decending order.
13177 # 3. Add one for each zero encountered until a non-zero digit.
13178 # 4. Add the count to the exp.
13179 # 5. Check if the exp has crossed zero in #3 above; clear SE.
13180 # 6. Divide the mantissa by 10**count.
13181 #
13182 # *Why 27? If the adjusted exponent is within -28 < expA < 28, than
13183 # any adjustment due to append/strip zeros will drive the resultane
13184 # exponent towards zero. Since all pwrten constants with a power
13185 # of 27 or less are exact, there is no need to use this routine to
13186 # attempt to lessen the resultant exponent.
13187 #
13188 # Register usage:
13189 #
13190 # ap_st_z:
13191 # (*) d0: temp digit storage
13192 # (*) d1: zero count
13193 # (*) d2: digit count
13194 # (*) d3: offset pointer
13195 # ( ) d4: first word of bcd
13196 # (*) d5: lword counter
13197 # ( ) a0: pointer to working bcd value
13198 # ( ) FP_SCR1: working copy of original bcd value
13199 # ( ) L_SCR1: copy of original exponent word
13200 #
13201 #
13202 # First check the absolute value of the exponent to see if this
13203 # routine is necessary. If so, then check the sign of the exponent
13204 # and do append (+) or strip (-) zeros accordingly.
13205 # This section handles a positive adjusted exponent.
13206 #
13207 ap_st_z:
13210 ble.w pwrten # if abs(expA) <28, skip ap/st zeros
13224 ap_p_cl:
13227 ap_p_gd:
13233 ap_p_fx:
13242 #
13243 # Calculate the mantissa multiplier to compensate for the striping of
13244 # zeros from the mantissa.
13245 #
13246 ap_p_fm:
13251 ap_p_el:
13255 ap_p_en:
13261 #
13262 # This section handles a negative adjusted exponent.
13263 #
13264 ap_st_n:
13272 ap_n_cl:
13275 ap_n_gd:
13281 ap_n_fx:
13290 #
13291 # Calculate the mantissa multiplier to compensate for the appending of
13292 # zeros to the mantissa.
13293 #
13294 ap_n_fm:
13299 ap_n_el:
13303 ap_n_en:
13308 #
13309 #
13310 # Calculate power-of-ten factor from adjusted and shifted exponent.
13311 #
13312 # Register usage:
13313 #
13314 # pwrten:
13315 # (*) d0: temp
13316 # ( ) d1: exponent
13317 # (*) d2: {FPCR[6:5],SM,SE} as index in RTABLE; temp
13318 # (*) d3: FPCR work copy
13319 # ( ) d4: first word of bcd
13320 # (*) a1: RTABLE pointer
13321 # calc_p:
13322 # (*) d0: temp
13323 # ( ) d1: exponent
13324 # (*) d3: PWRTxx table index
13325 # ( ) a0: pointer to working copy of bcd
13326 # (*) a1: PWRTxx pointer
13327 # (*) fp1: power-of-ten accumulator
13328 #
13329 # Pwrten calculates the exponent factor in the selected rounding mode
13330 # according to the following table:
13331 #
13332 # Sign of Mant Sign of Exp Rounding Mode PWRTEN Rounding Mode
13333 #
13334 # ANY ANY RN RN
13335 #
13336 # + + RP RP
13337 # - + RP RM
13338 # + - RP RM
13339 # - - RP RP
13340 #
13341 # + + RM RM
13342 # - + RM RP
13343 # + - RM RP
13344 # - - RM RM
13345 #
13346 # + + RZ RM
13347 # - + RZ RM
13348 # + - RZ RP
13349 # - - RZ RP
13350 #
13351 #
13352 pwrten:
13368 not_rp:
13370 bcc.b not_rm
13373 not_rm:
13375 calc_p:
13380 no_neg:
13383 e_loop:
13387 e_next:
13391 #
13392 #
13393 # Check the sign of the adjusted exp and make the value in fp0 the
13394 # same sign. If the exp was pos then multiply fp1*fp0;
13395 # else divide fp0/fp1.
13396 #
13397 # Register Usage:
13398 # norm:
13399 # ( ) a0: pointer to working bcd value
13400 # (*) fp0: mantissa accumulator
13401 # ( ) fp1: scaling factor - 10**(abs(exp))
13402 #
13403 pnorm:
13408 bra.b end_dec
13411 #
13412 #
13413 # Clean up and return with result in fp0.
13414 #
13415 # If the final mul/div in decbin incurred an inex exception,
13416 # it will be inex2, but will be reported as inex1 by get_op.
13417 #
13418 end_dec:
13423 no_exc:
13429 rts
13431 #########################################################################
13432 # bindec(): Converts an input in extended precision format to bcd format#
13433 # #
13434 # INPUT *************************************************************** #
13435 # a0 = pointer to the input extended precision value in memory. #
13436 # the input may be either normalized, unnormalized, or #
13437 # denormalized. #
13438 # d0 = contains the k-factor sign-extended to 32-bits. #
13439 # #
13440 # OUTPUT ************************************************************** #
13441 # FP_SCR0(a6) = bcd format result on the stack. #
13442 # #
13443 # ALGORITHM *********************************************************** #
13444 # #
13445 # A1. Set RM and size ext; Set SIGMA = sign of input. #
13446 # The k-factor is saved for use in d7. Clear the #
13447 # BINDEC_FLG for separating normalized/denormalized #
13448 # input. If input is unnormalized or denormalized, #
13449 # normalize it. #
13450 # #
13451 # A2. Set X = abs(input). #
13452 # #
13453 # A3. Compute ILOG. #
13454 # ILOG is the log base 10 of the input value. It is #
13455 # approximated by adding e + 0.f when the original #
13456 # value is viewed as 2^^e * 1.f in extended precision. #
13457 # This value is stored in d6. #
13458 # #
13459 # A4. Clr INEX bit. #
13460 # The operation in A3 above may have set INEX2. #
13461 # #
13462 # A5. Set ICTR = 0; #
13463 # ICTR is a flag used in A13. It must be set before the #
13464 # loop entry A6. #
13465 # #
13466 # A6. Calculate LEN. #
13467 # LEN is the number of digits to be displayed. The #
13468 # k-factor can dictate either the total number of digits, #
13469 # if it is a positive number, or the number of digits #
13470 # after the decimal point which are to be included as #
13471 # significant. See the 68882 manual for examples. #
13472 # If LEN is computed to be greater than 17, set OPERR in #
13473 # USER_FPSR. LEN is stored in d4. #
13474 # #
13475 # A7. Calculate SCALE. #
13476 # SCALE is equal to 10^ISCALE, where ISCALE is the number #
13477 # of decimal places needed to insure LEN integer digits #
13478 # in the output before conversion to bcd. LAMBDA is the #
13479 # sign of ISCALE, used in A9. Fp1 contains #
13480 # 10^^(abs(ISCALE)) using a rounding mode which is a #
13481 # function of the original rounding mode and the signs #
13482 # of ISCALE and X. A table is given in the code. #
13483 # #
13484 # A8. Clr INEX; Force RZ. #
13485 # The operation in A3 above may have set INEX2. #
13486 # RZ mode is forced for the scaling operation to insure #
13487 # only one rounding error. The grs bits are collected in #
13488 # the INEX flag for use in A10. #
13489 # #
13490 # A9. Scale X -> Y. #
13491 # The mantissa is scaled to the desired number of #
13492 # significant digits. The excess digits are collected #
13493 # in INEX2. #
13494 # #
13495 # A10. Or in INEX. #
13496 # If INEX is set, round error occurred. This is #
13497 # compensated for by 'or-ing' in the INEX2 flag to #
13498 # the lsb of Y. #
13499 # #
13500 # A11. Restore original FPCR; set size ext. #
13501 # Perform FINT operation in the user's rounding mode. #
13502 # Keep the size to extended. #
13503 # #
13504 # A12. Calculate YINT = FINT(Y) according to user's rounding #
13505 # mode. The FPSP routine sintd0 is used. The output #
13506 # is in fp0. #
13507 # #
13508 # A13. Check for LEN digits. #
13509 # If the int operation results in more than LEN digits, #
13510 # or less than LEN -1 digits, adjust ILOG and repeat from #
13511 # A6. This test occurs only on the first pass. If the #
13512 # result is exactly 10^LEN, decrement ILOG and divide #
13513 # the mantissa by 10. #
13514 # #
13515 # A14. Convert the mantissa to bcd. #
13516 # The binstr routine is used to convert the LEN digit #
13517 # mantissa to bcd in memory. The input to binstr is #
13518 # to be a fraction; i.e. (mantissa)/10^LEN and adjusted #
13519 # such that the decimal point is to the left of bit 63. #
13520 # The bcd digits are stored in the correct position in #
13521 # the final string area in memory. #
13522 # #
13523 # A15. Convert the exponent to bcd. #
13524 # As in A14 above, the exp is converted to bcd and the #
13525 # digits are stored in the final string. #
13526 # Test the length of the final exponent string. If the #
13527 # length is 4, set operr. #
13528 # #
13529 # A16. Write sign bits to final string. #
13530 # #
13531 #########################################################################
13535 # Constants in extended precision
13536 PLOG2:
13538 PLOG2UP1:
13541 # Constants in single precision
13542 FONE:
13544 FTWO:
13546 FTEN:
13548 F4933:
13551 RBDTBL:
13557 # Implementation Notes:
13558 #
13559 # The registers are used as follows:
13560 #
13561 # d0: scratch; LEN input to binstr
13562 # d1: scratch
13563 # d2: upper 32-bits of mantissa for binstr
13564 # d3: scratch;lower 32-bits of mantissa for binstr
13565 # d4: LEN
13566 # d5: LAMBDA/ICTR
13567 # d6: ILOG
13568 # d7: k-factor
13569 # a0: ptr for original operand/final result
13570 # a1: scratch pointer
13571 # a2: pointer to FP_X; abs(original value) in ext
13572 # fp0: scratch
13573 # fp1: scratch
13574 # fp2: scratch
13575 # F_SCR1:
13576 # F_SCR2:
13577 # L_SCR1:
13578 # L_SCR2:
13580 global bindec
13581 bindec:
13585 # A1. Set RM and size ext. Set SIGMA = sign input;
13586 # The k-factor is saved for use in d7. Clear BINDEC_FLG for
13587 # separating normalized/denormalized input. If the input
13588 # is a denormalized number, set the BINDEC_FLG memory word
13589 # to signal denorm. If the input is unnormalized, normalize
13590 # the input and test for denormalized result.
13591 #
13598 bne.w A2_str # no; input is a NORM
13600 #
13601 # Normalize the denorm
13602 #
13603 un_de_norm:
13608 norm_loop:
13613 bge.b norm_loop
13614 #
13615 # Test if the normalized input is denormalized
13616 #
13617 tst.w %d0
13620 pos_exp:
13626 # A2. Set X = abs(input).
13627 #
13628 A2_str:
13634 # A3. Compute ILOG.
13635 # ILOG is the log base 10 of the input value. It is approx-
13636 # imated by adding e + 0.f when the original value is viewed
13637 # as 2^^e * 1.f in extended precision. This value is stored
13638 # in d6.
13639 #
13640 # Register usage:
13641 # Input/Output
13642 # d0: k-factor/exponent
13643 # d2: x/x
13644 # d3: x/x
13645 # d4: x/x
13646 # d5: x/x
13647 # d6: x/ILOG
13648 # d7: k-factor/Unchanged
13649 # a0: ptr for original operand/final result
13650 # a1: x/x
13651 # a2: x/x
13652 # fp0: x/float(ILOG)
13653 # fp1: x/x
13654 # fp2: x/x
13655 # F_SCR1:x/x
13656 # F_SCR2:Abs(X)/Abs(X) with $3fff exponent
13657 # L_SCR1:x/x
13658 # L_SCR2:first word of X packed/Unchanged
13663 bra.b A4_str
13664 A3_cont:
13671 fbge.w pos_res # if pos, branch
13675 pos_res:
13680 # A4. Clr INEX bit.
13681 # The operation in A3 above may have set INEX2.
13683 A4_str:
13687 # A5. Set ICTR = 0;
13688 # ICTR is a flag used in A13. It must be set before the
13689 # loop entry A6. The lower word of d5 is used for ICTR.
13693 # A6. Calculate LEN.
13694 # LEN is the number of digits to be displayed. The k-factor
13695 # can dictate either the total number of digits, if it is
13696 # a positive number, or the number of digits after the
13697 # original decimal point which are to be included as
13698 # significant. See the 68882 manual for examples.
13699 # If LEN is computed to be greater than 17, set OPERR in
13700 # USER_FPSR. LEN is stored in d4.
13701 #
13702 # Register usage:
13703 # Input/Output
13704 # d0: exponent/Unchanged
13705 # d2: x/x/scratch
13706 # d3: x/x
13707 # d4: exc picture/LEN
13708 # d5: ICTR/Unchanged
13709 # d6: ILOG/Unchanged
13710 # d7: k-factor/Unchanged
13711 # a0: ptr for original operand/final result
13712 # a1: x/x
13713 # a2: x/x
13714 # fp0: float(ILOG)/Unchanged
13715 # fp1: x/x
13716 # fp2: x/x
13717 # F_SCR1:x/x
13718 # F_SCR2:Abs(X) with $3fff exponent/Unchanged
13719 # L_SCR1:x/x
13720 # L_SCR2:first word of X packed/Unchanged
13722 A6_str:
13727 k_neg:
13731 len_ck:
13741 LEN_ng:
13745 # A7. Calculate SCALE.
13746 # SCALE is equal to 10^ISCALE, where ISCALE is the number
13747 # of decimal places needed to insure LEN integer digits
13748 # in the output before conversion to bcd. LAMBDA is the sign
13749 # of ISCALE, used in A9. Fp1 contains 10^^(abs(ISCALE)) using
13750 # the rounding mode as given in the following table (see
13751 # Coonen, p. 7.23 as ref.; however, the SCALE variable is
13752 # of opposite sign in bindec.sa from Coonen).
13753 #
13754 # Initial USE
13755 # FPCR[6:5] LAMBDA SIGN(X) FPCR[6:5]
13756 # ----------------------------------------------
13757 # RN 00 0 0 00/0 RN
13758 # RN 00 0 1 00/0 RN
13759 # RN 00 1 0 00/0 RN
13760 # RN 00 1 1 00/0 RN
13761 # RZ 01 0 0 11/3 RP
13762 # RZ 01 0 1 11/3 RP
13763 # RZ 01 1 0 10/2 RM
13764 # RZ 01 1 1 10/2 RM
13765 # RM 10 0 0 11/3 RP
13766 # RM 10 0 1 10/2 RM
13767 # RM 10 1 0 10/2 RM
13768 # RM 10 1 1 11/3 RP
13769 # RP 11 0 0 10/2 RM
13770 # RP 11 0 1 11/3 RP
13771 # RP 11 1 0 11/3 RP
13772 # RP 11 1 1 10/2 RM
13773 #
13774 # Register usage:
13775 # Input/Output
13776 # d0: exponent/scratch - final is 0
13777 # d2: x/0 or 24 for A9
13778 # d3: x/scratch - offset ptr into PTENRM array
13779 # d4: LEN/Unchanged
13780 # d5: 0/ICTR:LAMBDA
13781 # d6: ILOG/ILOG or k if ((k<=0)&(ILOG<k))
13782 # d7: k-factor/Unchanged
13783 # a0: ptr for original operand/final result
13784 # a1: x/ptr to PTENRM array
13785 # a2: x/x
13786 # fp0: float(ILOG)/Unchanged
13787 # fp1: x/10^ISCALE
13788 # fp2: x/x
13789 # F_SCR1:x/x
13790 # F_SCR2:Abs(X) with $3fff exponent/Unchanged
13791 # L_SCR1:x/x
13792 # L_SCR2:first word of X packed/Unchanged
13794 A7_str:
13800 k_pos:
13814 no_inf:
13816 iscale:
13825 x_pos:
13835 not_rn:
13840 not_rp2:
13842 rmode:
13844 e_loop2:
13848 e_next2:
13853 # A8. Clr INEX; Force RZ.
13854 # The operation in A3 above may have set INEX2.
13855 # RZ mode is forced for the scaling operation to insure
13856 # only one rounding error. The grs bits are collected in
13857 # the INEX flag for use in A10.
13858 #
13859 # Register usage:
13860 # Input/Output
13865 # A9. Scale X -> Y.
13866 # The mantissa is scaled to the desired number of significant
13867 # digits. The excess digits are collected in INEX2. If mul,
13868 # Check d2 for excess 10 exponential value. If not zero,
13869 # the iscale value would have caused the pwrten calculation
13870 # to overflow. Only a negative iscale can cause this, so
13871 # multiply by 10^(d2), which is now only allowed to be 24,
13872 # with a multiply by 10^8 and 10^16, which is exact since
13873 # 10^24 is exact. If the input was denormalized, we must
13874 # create a busy stack frame with the mul command and the
13875 # two operands, and allow the fpu to complete the multiply.
13876 #
13877 # Register usage:
13878 # Input/Output
13879 # d0: FPCR with RZ mode/Unchanged
13880 # d2: 0 or 24/unchanged
13881 # d3: x/x
13882 # d4: LEN/Unchanged
13883 # d5: ICTR:LAMBDA
13884 # d6: ILOG/Unchanged
13885 # d7: k-factor/Unchanged
13886 # a0: ptr for original operand/final result
13887 # a1: ptr to PTENRM array/Unchanged
13888 # a2: x/x
13889 # fp0: float(ILOG)/X adjusted for SCALE (Y)
13890 # fp1: 10^ISCALE/Unchanged
13891 # fp2: x/x
13892 # F_SCR1:x/x
13893 # F_SCR2:Abs(X) with $3fff exponent/Unchanged
13894 # L_SCR1:x/x
13895 # L_SCR2:first word of X packed/Unchanged
13897 A9_str:
13903 bra.w A10_st # branch to A10
13905 sc_mul:
13907 beq.w A9_norm # if norm, continue with mul
13909 # for DENORM, we must calculate:
13910 # fp0 = input_op * 10^ISCALE * 10^24
13911 # since the input operand is a DENORM, we can't multiply it directly.
13912 # so, we do the multiplication of the exponents and mantissas separately.
13913 # in this way, we avoid underflow on intermediate stages of the
13914 # multiplication and guarantee a result without exception.
13927 bmi.w sc_mul_err # is result is DENORM, punt!!!
13938 # fmul.x 36(%a1),%fp0 # multiply fp0 by 10^8
13939 # fmul.x 48(%a1),%fp0 # multiply fp0 by 10^16
13948 bra.b A10_st
13950 sc_mul_err:
13951 bra.b sc_mul_err
13953 A9_norm:
13958 A9_con:
13961 # A10. Or in INEX.
13962 # If INEX is set, round error occurred. This is compensated
13963 # for by 'or-ing' in the INEX2 flag to the lsb of Y.
13964 #
13965 # Register usage:
13966 # Input/Output
13967 # d0: FPCR with RZ mode/FPSR with INEX2 isolated
13968 # d2: x/x
13969 # d3: x/x
13970 # d4: LEN/Unchanged
13971 # d5: ICTR:LAMBDA
13972 # d6: ILOG/Unchanged
13973 # d7: k-factor/Unchanged
13974 # a0: ptr for original operand/final result
13975 # a1: ptr to PTENxx array/Unchanged
13976 # a2: x/ptr to FP_SCR1(a6)
13977 # fp0: Y/Y with lsb adjusted
13978 # fp1: 10^ISCALE/Unchanged
13979 # fp2: x/x
13981 A10_st:
13991 # A11. Restore original FPCR; set size ext.
13992 # Perform FINT operation in the user's rounding mode. Keep
13993 # the size to extended. The sintdo entry point in the sint
13994 # routine expects the FPCR value to be in USER_FPCR for
13995 # mode and precision. The original FPCR is saved in L_SCR1.
13997 A11_st:
14000 # ;block exceptions
14003 # A12. Calculate YINT = FINT(Y) according to user's rounding mode.
14004 # The FPSP routine sintd0 is used. The output is in fp0.
14005 #
14006 # Register usage:
14007 # Input/Output
14008 # d0: FPSR with AINEX cleared/FPCR with size set to ext
14009 # d2: x/x/scratch
14010 # d3: x/x
14011 # d4: LEN/Unchanged
14012 # d5: ICTR:LAMBDA/Unchanged
14013 # d6: ILOG/Unchanged
14014 # d7: k-factor/Unchanged
14015 # a0: ptr for original operand/src ptr for sintdo
14016 # a1: ptr to PTENxx array/Unchanged
14017 # a2: ptr to FP_SCR1(a6)/Unchanged
14018 # a6: temp pointer to FP_SCR1(a6) - orig value saved and restored
14019 # fp0: Y/YINT
14020 # fp1: 10^ISCALE/Unchanged
14021 # fp2: x/x
14022 # F_SCR1:x/x
14023 # F_SCR2:Y adjusted for inex/Y with original exponent
14024 # L_SCR1:x/original USER_FPCR
14025 # L_SCR2:first word of X packed/Unchanged
14027 A12_st:
14037 do_fint12:
14039 # bsr sintdo # sint routine returns int in fp0
14043 ## mov.l USER_FPCR(%a6),%d0 # ext prec/keep rnd mode
14044 ## andi.l &0x00000030,%d0
14045 ## fmov.l %d0,%fpcr
14049 ## fmov.l &0x0,%fpcr
14050 ## fmov.l %fpsr,%d0 # don't keep ccodes
14051 ## or.w %d0,FPSR_EXCEPT(%a6)
14063 # A13. Check for LEN digits.
14064 # If the int operation results in more than LEN digits,
14065 # or less than LEN -1 digits, adjust ILOG and repeat from
14066 # A6. This test occurs only on the first pass. If the
14067 # result is exactly 10^LEN, decrement ILOG and divide
14068 # the mantissa by 10. The calculation of 10^LEN cannot
14069 # be inexact, since all powers of ten upto 10^27 are exact
14070 # in extended precision, so the use of a previous power-of-ten
14071 # table will introduce no error.
14072 #
14073 #
14074 # Register usage:
14075 # Input/Output
14076 # d0: FPCR with size set to ext/scratch final = 0
14077 # d2: x/x
14078 # d3: x/scratch final = x
14079 # d4: LEN/LEN adjusted
14080 # d5: ICTR:LAMBDA/LAMBDA:ICTR
14081 # d6: ILOG/ILOG adjusted
14082 # d7: k-factor/Unchanged
14083 # a0: pointer into memory for packed bcd string formation
14084 # a1: ptr to PTENxx array/Unchanged
14085 # a2: ptr to FP_SCR1(a6)/Unchanged
14086 # fp0: int portion of Y/abs(YINT) adjusted
14087 # fp1: 10^ISCALE/Unchanged
14088 # fp2: x/10^LEN
14089 # F_SCR1:x/x
14090 # F_SCR2:Y with original exponent/Unchanged
14091 # L_SCR1:original USER_FPCR/Unchanged
14092 # L_SCR2:first word of X packed/Unchanged
14094 A13_st:
14098 #
14099 # Compute 10^(LEN-1)
14100 #
14105 l_loop:
14109 l_next:
14113 #
14114 # 10^LEN-1 is computed for this test and A14. If the input was
14115 # denormalized, check only the case in which YINT > 10^LEN.
14116 #
14120 bra test_2
14121 #
14122 # Compare abs(YINT) to 10^(LEN-1) and 10^LEN
14123 #
14124 A13_con:
14127 fbge.w test_2 # if greater, do next test
14132 bra.w A6_str # return to A6 and recompute YINT
14133 test_2:
14136 fblt.w A14_st # if less, all is ok, go to A14
14137 fbgt.w fix_ex # if greater, fix and redo
14141 fix_ex:
14145 bra.w A6_str # return to A6 and recompute YINT
14146 #
14147 # Since ICTR <> 0, we have already been through one adjustment,
14148 # and shouldn't have another; this is to check if abs(YINT) = 10^LEN
14149 # 10^LEN is again computed using whatever table is in a1 since the
14150 # value calculated cannot be inexact.
14151 #
14152 not_zr:
14156 z_loop:
14160 z_next:
14166 fbneq.w A14_st # if not, skip this
14172 # A14. Convert the mantissa to bcd.
14173 # The binstr routine is used to convert the LEN digit
14174 # mantissa to bcd in memory. The input to binstr is
14175 # to be a fraction; i.e. (mantissa)/10^LEN and adjusted
14176 # such that the decimal point is to the left of bit 63.
14177 # The bcd digits are stored in the correct position in
14178 # the final string area in memory.
14179 #
14180 #
14181 # Register usage:
14182 # Input/Output
14183 # d0: x/LEN call to binstr - final is 0
14184 # d1: x/0
14185 # d2: x/ms 32-bits of mant of abs(YINT)
14186 # d3: x/ls 32-bits of mant of abs(YINT)
14187 # d4: LEN/Unchanged
14188 # d5: ICTR:LAMBDA/LAMBDA:ICTR
14189 # d6: ILOG
14190 # d7: k-factor/Unchanged
14191 # a0: pointer into memory for packed bcd string formation
14192 # /ptr to first mantissa byte in result string
14193 # a1: ptr to PTENxx array/Unchanged
14194 # a2: ptr to FP_SCR1(a6)/Unchanged
14195 # fp0: int portion of Y/abs(YINT) adjusted
14196 # fp1: 10^ISCALE/Unchanged
14197 # fp2: 10^LEN/Unchanged
14198 # F_SCR1:x/Work area for final result
14199 # F_SCR2:Y with original exponent/Unchanged
14200 # L_SCR1:original USER_FPCR/Unchanged
14201 # L_SCR2:first word of X packed/Unchanged
14203 A14_st:
14219 m_loop:
14223 no_sft:
14228 no_zr:
14233 zer_m:
14236 bsr binstr # call binstr to convert mant
14239 # A15. Convert the exponent to bcd.
14240 # As in A14 above, the exp is converted to bcd and the
14241 # digits are stored in the final string.
14242 #
14243 # Digits are stored in L_SCR1(a6) on return from BINDEC as:
14244 #
14245 # 32 16 15 0
14246 # -----------------------------------------
14247 # | 0 | e3 | e2 | e1 | e4 | X | X | X |
14248 # -----------------------------------------
14249 #
14250 # And are moved into their proper places in FP_SCR0. If digit e4
14251 # is non-zero, OPERR is signaled. In all cases, all 4 digits are
14252 # written as specified in the 881/882 manual for packed decimal.
14253 #
14254 # Register usage:
14255 # Input/Output
14256 # d0: x/LEN call to binstr - final is 0
14257 # d1: x/scratch (0);shift count for final exponent packing
14258 # d2: x/ms 32-bits of exp fraction/scratch
14259 # d3: x/ls 32-bits of exp fraction
14260 # d4: LEN/Unchanged
14261 # d5: ICTR:LAMBDA/LAMBDA:ICTR
14262 # d6: ILOG
14263 # d7: k-factor/Unchanged
14264 # a0: ptr to result string/ptr to L_SCR1(a6)
14265 # a1: ptr to PTENxx array/Unchanged
14266 # a2: ptr to FP_SCR1(a6)/Unchanged
14267 # fp0: abs(YINT) adjusted/float(ILOG)
14268 # fp1: 10^ISCALE/Unchanged
14269 # fp2: 10^LEN/Unchanged
14270 # F_SCR1:Work area for final result/BCD result
14271 # F_SCR2:Y with original exponent/ILOG/10^4
14272 # L_SCR1:original USER_FPCR/Exponent digits on return from binstr
14273 # L_SCR2:first word of X packed/Unchanged
14275 A15_st:
14277 beq.b not_denorm
14279 fbeq.w den_zero # if zero, use k-factor or 4933
14282 bra.b convrt
14283 den_zero:
14288 use_ilog:
14291 bra.b convrt
14292 not_denorm:
14294 fbneq.w not_zero # if zero, force exponent
14297 not_zero:
14300 convrt:
14309 x_loop:
14313 x_loop_fin:
14320 bsr binstr # call binstr to convert exp
14332 # A16. Write sign bits to final string.
14333 # Sigma is bit 31 of initial value; RHO is bit 31 of d6 (ILOG).
14334 #
14335 # Register usage:
14336 # Input/Output
14337 # d0: x/scratch - final is x
14338 # d2: x/x
14339 # d3: x/x
14340 # d4: LEN/Unchanged
14341 # d5: ICTR:LAMBDA/LAMBDA:ICTR
14342 # d6: ILOG/ILOG adjusted
14343 # d7: k-factor/Unchanged
14344 # a0: ptr to L_SCR1(a6)/Unchanged
14345 # a1: ptr to PTENxx array/Unchanged
14346 # a2: ptr to FP_SCR1(a6)/Unchanged
14347 # fp0: float(ILOG)/Unchanged
14348 # fp1: 10^ISCALE/Unchanged
14349 # fp2: 10^LEN/Unchanged
14350 # F_SCR1:BCD result with correct signs
14351 # F_SCR2:ILOG/10^4
14352 # L_SCR1:Exponent digits on return from binstr
14353 # L_SCR2:first word of X packed/Unchanged
14355 A16_st:
14361 mant_p:
14365 wr_sgn:
14368 # Clean up and restore all registers used.
14373 rts
14375 global PTENRN
14376 PTENRN:
14391 global PTENRP
14392 PTENRP:
14407 global PTENRM
14408 PTENRM:
14423 #########################################################################
14424 # binstr(): Converts a 64-bit binary integer to bcd. #
14425 # #
14426 # INPUT *************************************************************** #
14427 # d2:d3 = 64-bit binary integer #
14428 # d0 = desired length (LEN) #
14429 # a0 = pointer to start in memory for bcd characters #
14430 # (This pointer must point to byte 4 of the first #
14431 # lword of the packed decimal memory string.) #
14432 # #
14433 # OUTPUT ************************************************************** #
14434 # a0 = pointer to LEN bcd digits representing the 64-bit integer. #
14435 # #
14436 # ALGORITHM *********************************************************** #
14437 # The 64-bit binary is assumed to have a decimal point before #
14438 # bit 63. The fraction is multiplied by 10 using a mul by 2 #
14439 # shift and a mul by 8 shift. The bits shifted out of the #
14440 # msb form a decimal digit. This process is iterated until #
14441 # LEN digits are formed. #
14442 # #
14443 # A1. Init d7 to 1. D7 is the byte digit counter, and if 1, the #
14444 # digit formed will be assumed the least significant. This is #
14445 # to force the first byte formed to have a 0 in the upper 4 bits. #
14446 # #
14447 # A2. Beginning of the loop: #
14448 # Copy the fraction in d2:d3 to d4:d5. #
14449 # #
14450 # A3. Multiply the fraction in d2:d3 by 8 using bit-field #
14451 # extracts and shifts. The three msbs from d2 will go into d1. #
14452 # #
14453 # A4. Multiply the fraction in d4:d5 by 2 using shifts. The msb #
14454 # will be collected by the carry. #
14455 # #
14456 # A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5 #
14457 # into d2:d3. D1 will contain the bcd digit formed. #
14458 # #
14459 # A6. Test d7. If zero, the digit formed is the ms digit. If non- #
14460 # zero, it is the ls digit. Put the digit in its place in the #
14461 # upper word of d0. If it is the ls digit, write the word #
14462 # from d0 to memory. #
14463 # #
14464 # A7. Decrement d6 (LEN counter) and repeat the loop until zero. #
14465 # #
14466 #########################################################################
14468 # Implementation Notes:
14469 #
14470 # The registers are used as follows:
14471 #
14472 # d0: LEN counter
14473 # d1: temp used to form the digit
14474 # d2: upper 32-bits of fraction for mul by 8
14475 # d3: lower 32-bits of fraction for mul by 8
14476 # d4: upper 32-bits of fraction for mul by 2
14477 # d5: lower 32-bits of fraction for mul by 2
14478 # d6: temp for bit-field extracts
14479 # d7: byte digit formation word;digit count {0,1}
14480 # a0: pointer into memory for packed bcd string formation
14481 #
14483 global binstr
14484 binstr:
14487 #
14488 # A1: Init d7
14489 #
14492 #
14493 # A2. Copy d2:d3 to d4:d5. Start loop.
14494 #
14495 loop:
14498 #
14499 # A3. Multiply d2:d3 by 8; extract msbs into d1.
14500 #
14506 #
14507 # A4. Multiply d4:d5 by 2; add carry out to d1.
14508 #
14513 #
14514 # A5. Add mul by 8 to mul by 2. D1 contains the digit formed.
14515 #
14522 #
14523 # A6. Test d7 and branch.
14524 #
14527 sec_d:
14536 first_d:
14545 #
14546 # Clean up and return with result in fp0.
14547 #
14548 end_bstr:
14550 rts
14552 #########################################################################
14553 # XDEF **************************************************************** #
14554 # facc_in_b(): dmem_read_byte failed #
14555 # facc_in_w(): dmem_read_word failed #
14556 # facc_in_l(): dmem_read_long failed #
14557 # facc_in_d(): dmem_read of dbl prec failed #
14558 # facc_in_x(): dmem_read of ext prec failed #
14559 # #
14560 # facc_out_b(): dmem_write_byte failed #
14561 # facc_out_w(): dmem_write_word failed #
14562 # facc_out_l(): dmem_write_long failed #
14563 # facc_out_d(): dmem_write of dbl prec failed #
14564 # facc_out_x(): dmem_write of ext prec failed #
14565 # #
14566 # XREF **************************************************************** #
14567 # _real_access() - exit through access error handler #
14568 # #
14569 # INPUT *************************************************************** #
14570 # None #
14571 # #
14572 # OUTPUT ************************************************************** #
14573 # None #
14574 # #
14575 # ALGORITHM *********************************************************** #
14576 # Flow jumps here when an FP data fetch call gets an error #
14577 # result. This means the operating system wants an access error frame #
14578 # made out of the current exception stack frame. #
14579 # So, we first call restore() which makes sure that any updated #
14580 # -(an)+ register gets returned to its pre-exception value and then #
14581 # we change the stack to an acess error stack frame. #
14582 # #
14583 #########################################################################
14585 facc_in_b:
14587 bsr.w restore # fix An
14590 bra.w facc_finish
14592 facc_in_w:
14594 bsr.w restore # fix An
14597 bra.b facc_finish
14599 facc_in_l:
14601 bsr.w restore # fix An
14604 bra.b facc_finish
14606 facc_in_d:
14608 bsr.w restore # fix An
14611 bra.b facc_finish
14613 facc_in_x:
14615 bsr.w restore # fix An
14618 bra.b facc_finish
14620 ################################################################
14622 facc_out_b:
14624 bsr.w restore # restore An
14627 bra.b facc_finish
14629 facc_out_w:
14631 bsr.w restore # restore An
14634 bra.b facc_finish
14636 facc_out_l:
14638 bsr.w restore # restore An
14641 bra.b facc_finish
14643 facc_out_d:
14645 bsr.w restore # restore An
14648 bra.b facc_finish
14650 facc_out_x:
14652 bsr.w restore # restore An
14656 # here's where we actually create the access error frame from the
14657 # current exception stack frame.
14658 facc_finish:
14665 unlk %a6
14678 facc_out2:
14679 bra.l _real_access
14681 ##################################################################
14683 # if the effective addressing mode was predecrement or postincrement,
14684 # the emulation has already changed its value to the correct post-
14685 # instruction value. but since we're exiting to the access error
14686 # handler, then AN must be returned to its pre-instruction value.
14687 # we do that here.
14688 restore:
14692 beq.w rest_inc
14694 beq.w rest_dec
14695 rts
14697 rest_inc:
14704 tbl_rest_inc:
14705 short ri_a0 - tbl_rest_inc
14706 short ri_a1 - tbl_rest_inc
14707 short ri_a2 - tbl_rest_inc
14708 short ri_a3 - tbl_rest_inc
14709 short ri_a4 - tbl_rest_inc
14710 short ri_a5 - tbl_rest_inc
14711 short ri_a6 - tbl_rest_inc
14712 short ri_a7 - tbl_rest_inc
14714 ri_a0:
14716 rts
14717 ri_a1:
14719 rts
14720 ri_a2:
14722 rts
14723 ri_a3:
14725 rts
14726 ri_a4:
14728 rts
14729 ri_a5:
14731 rts
14732 ri_a6:
14734 rts
14735 # if it's a fmove out instruction, we don't have to fix a7
14736 # because we hadn't changed it yet. if it's an opclass two
14737 # instruction (data moved in) and the exception was in supervisor
14738 # mode, then also also wasn't updated. if it was user mode, then
14739 # restore the correct a7 which is in the USP currently.
14740 ri_a7:
14749 ri_a7_done:
14750 rts
14752 # need to invert adjustment value if the <ea> was predec
14753 rest_dec:
14755 bra.b rest_inc