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[AROS.git] / workbench / hidds / radeon / radeon_driver.c
blob83c45e05c232014be1af862071ba3b7b5e192d7e
1 /*
2 Copyright © 2004, The AROS Development Team. All rights reserved.
3 $Id$
4 */
5
6 #include "ati.h"
7 #include "radeon.h"
8 #include "radeon_reg.h"
9 #include "radeon_bios.h"
10 #include "radeon_accel.h"
11 #include "radeon_macros.h"
12
13 #include "bitmap.h"
14
15 #include <math.h>
16
17 #define DEBUG 0
18 #include <aros/debug.h>
19
20 #include <proto/oop.h>
21 #include <hidd/i2c.h>
22
23 #define MAX(a,b) ((a) > (b) ? (a) : (b))
24
25 static void usleep(struct ati_staticdata *sd, ULONG usec)
26 {
27 D(bug("[ATI] usleep(%p, %d)\n", sd, usec));
28 sd->mp.mp_SigTask = FindTask(NULL);
29 sd->tr.tr_node.io_Command = TR_ADDREQUEST;
30 sd->tr.tr_time.tv_secs = usec / 1000000;
31 sd->tr.tr_time.tv_micro = usec % 1000000;
32
33 DoIO((struct IORequest *)&sd->tr);
34
35 sd->mp.mp_SigTask = NULL;
36 }
37
38 /* Compute n/d with rounding */
39 static int RADEONDiv(int n, int d)
40 {
41 return (n + (d / 2)) / d;
42 }
43
44 /* This function is required to workaround a hardware bug in some (all?)
45 * revisions of the R300. This workaround should be called after every
46 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
47 * may not be correct.
48 */
49 void R300CGWorkaround(struct ati_staticdata *sd)
50 {
51 ULONG save, tmp;
52
53 save = INREG(RADEON_CLOCK_CNTL_INDEX);
54 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
55 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
56 tmp = INREG(RADEON_CLOCK_CNTL_DATA);
57 OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
58 }
59
60 void RADEONPllErrataAfterIndex(struct ati_staticdata *sd)
61 {
62 if (!(sd->Card.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
63 return;
64
65 /* This workaround is necessary on rv200 and RS200 or PLL
66 * reads may return garbage (among others...)
67 */
68 (void)INREG(RADEON_CLOCK_CNTL_DATA);
69 (void)INREG(RADEON_CRTC_GEN_CNTL);
70 }
71
72 void RADEONPllErrataAfterData(struct ati_staticdata *sd)
73 {
74 /* This workarounds is necessary on RV100, RS100 and RS200 chips
75 * or the chip could hang on a subsequent access
76 */
77 if (sd->Card.ChipErrata & CHIP_ERRATA_PLL_DELAY) {
78 /* we can't deal with posted writes here ... */
79 usleep(sd, 5000);
80 }
81
82 /* This function is required to workaround a hardware bug in some (all?)
83 * revisions of the R300. This workaround should be called after every
84 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
85 * may not be correct.
86 */
87 if (sd->Card.ChipErrata & CHIP_ERRATA_R300_CG) {
88 ULONG save, tmp;
89
90 save = INREG(RADEON_CLOCK_CNTL_INDEX);
91 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
92 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
93 tmp = INREG(RADEON_CLOCK_CNTL_DATA);
94 OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
95 }
96 }
97
98 /* Read PLL information */
99 unsigned RADEONINPLL(struct ati_staticdata *sd, int addr)
100 {
101 ULONG data;
102
103 OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
104 RADEONPllErrataAfterIndex(sd);
105 data = INREG(RADEON_CLOCK_CNTL_DATA);
106 RADEONPllErrataAfterData(sd);
107
108 return data;
109 }
110
111 /* Blank screen */
112 static void RADEONBlank(struct ati_staticdata *sd)
113 {
114 if (!sd->Card.IsSecondary) {
115 switch(sd->Card.MonType1) {
116 case MT_LCD:
117 case MT_CRT:
118 case MT_DFP:
119 OUTREGP(RADEON_CRTC_EXT_CNTL,
120 RADEON_CRTC_DISPLAY_DIS,
121 ~(RADEON_CRTC_DISPLAY_DIS));
122 break;
123
124 case MT_NONE:
125 default:
126 break;
127 }
128 } else {
129 OUTREGP(RADEON_CRTC2_GEN_CNTL,
130 RADEON_CRTC2_DISP_DIS,
131 ~(RADEON_CRTC2_DISP_DIS));
132 }
133 }
134
135 /* Unblank screen */
136 static void RADEONUnblank(struct ati_staticdata *sd)
137 {
138 if (!sd->Card.IsSecondary) {
139 switch (sd->Card.MonType1) {
140 case MT_LCD:
141 case MT_CRT:
142 case MT_DFP:
143 OUTREGP(RADEON_CRTC_EXT_CNTL,
144 RADEON_CRTC_CRT_ON,
145 ~(RADEON_CRTC_DISPLAY_DIS));
146 break;
147
148 case MT_NONE:
149 default:
150 break;
151 }
152 } else {
153 switch (sd->Card.MonType1) {
154 case MT_LCD:
155 case MT_DFP:
156 case MT_CRT:
157 OUTREGP(RADEON_CRTC2_GEN_CNTL,
158 0,
159 ~(RADEON_CRTC2_DISP_DIS));
160 break;
161
162 case MT_NONE:
163 default:
164 break;
165 }
166 }
167 }
168
169 //static void RADEONPLLWaitForReadUpdateComplete(struct ati_staticdata *sd)
170 //{
171 // int i = 0;
172 //
173 // /* FIXME: Certain revisions of R300 can't recover here. Not sure of
174 // the cause yet, but this workaround will mask the problem for now.
175 // Other chips usually will pass at the very first test, so the
176 // workaround shouldn't have any effect on them. */
177 // for (i = 0;
178 // (i < 100000 &&
179 // RADEONINPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
180 // i++);
181 //}
182 //
183 //static void RADEONPLLWriteUpdate(struct ati_staticdata *sd)
184 //{
185 // while (INPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
186 //
187 // OUTPLLP(sd, RADEON_PPLL_REF_DIV,
188 // RADEON_PPLL_ATOMIC_UPDATE_W,
189 // ~(RADEON_PPLL_ATOMIC_UPDATE_W));
190 //}
191
192 /* Calculate display buffer watermark to prevent buffer underflow */
193 static void RADEONInitDispBandwidth(struct ati_staticdata *sd, struct CardState *mode)
194 {
195 ULONG temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0;
196 float mem_tcas;
197 int k1, c;
198 ULONG MemTrcdExtMemCntl[4] = {1, 2, 3, 4};
199 ULONG MemTrpExtMemCntl[4] = {1, 2, 3, 4};
200 ULONG MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
201
202 ULONG MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
203 ULONG MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
204 ULONG MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19};
205
206 float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0};
207 float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7};
208 float MemTrbs[8] = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5};
209
210 float mem_bw, peak_disp_bw;
211 float min_mem_eff = 0.8;
212 float sclk_eff, sclk_delay;
213 float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk;
214 float disp_latency, disp_latency_overhead, disp_drain_rate;
215 float pix_clk; /* in MHz */
216 int cur_size = 16; /* in octawords */
217 int critical_point;
218 int stop_req, max_stop_req;
219
220 /* R420 family not supported yet */
221 if (sd->Card.Type == R420) return;
222
223 /*
224 * Determine if there is enough bandwidth for current display mode
225 */
226 mem_bw = sd->Card.mclk * (sd->Card.RamWidth / 8) * (sd->Card.IsDDR ? 2 : 1);
227
228 pix_clk = mode->pixelc/1000.0;
229
230 peak_disp_bw = (pix_clk * mode->bpp);
231
232 D(bug("[ATI] mem_bw=%d peak_disp_bw=%d mode->bpp=%d mode->pixelc=%d mode->HDisplay=%d\n", (ULONG)mem_bw, (ULONG)peak_disp_bw,
233 mode->bpp, mode->pixelc, mode->HDisplay));
234
235 if (peak_disp_bw >= mem_bw * min_mem_eff) {
236 D(bug("[ATI] You may not have enough display bandwidth for current mode\n"
237 "[ATI] If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"));
238 }
239
240 /* CRTC1
241 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
242 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
243 */
244 stop_req = mode->HDisplay * mode->bpp / 16;
245
246 /* setup Max GRPH_STOP_REQ default value */
247 if (IS_RV100_VARIANT)
248 max_stop_req = 0x5c;
249 else
250 max_stop_req = 0x7c;
251 if (stop_req > max_stop_req)
252 stop_req = max_stop_req;
253
254 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
255 temp = INREG(RADEON_MEM_TIMING_CNTL);
256 if ((sd->Card.Type == RV100) || sd->Card.IsIGP) { /* RV100, M6, IGPs */
257 mem_trcd = MemTrcdExtMemCntl[(temp & 0x0c) >> 2];
258 mem_trp = MemTrpExtMemCntl[ (temp & 0x03) >> 0];
259 mem_tras = MemTrasExtMemCntl[(temp & 0x70) >> 4];
260 } else { /* RV200 and later */
261 mem_trcd = MemTrcdMemTimingCntl[(temp & 0x07) >> 0];
262 mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8];
263 mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12];
264 }
265
266 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
267 temp = INREG(RADEON_MEM_SDRAM_MODE_REG);
268 data = (temp & (7<<20)) >> 20;
269 if ((sd->Card.Type == RV100) || sd->Card.IsIGP) { /* RV100, M6, IGPs */
270 mem_tcas = MemTcas [data];
271 } else {
272 mem_tcas = MemTcas2 [data];
273 }
274
275 if (IS_R300_VARIANT) {
276
277 /* on the R300, Tcas is included in Trbs.
278 */
279 temp = INREG(RADEON_MEM_CNTL);
280 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
281 if (data == 2) {
282 if (R300_MEM_USE_CD_CH_ONLY & temp) {
283 temp = INREG(R300_MC_IND_INDEX);
284 temp &= ~R300_MC_IND_ADDR_MASK;
285 temp |= R300_MC_READ_CNTL_CD_mcind;
286 OUTREG(R300_MC_IND_INDEX, temp);
287 temp = INREG(R300_MC_IND_DATA);
288 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
289 } else {
290 temp = INREG(R300_MC_READ_CNTL_AB);
291 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
292 }
293 } else {
294 temp = INREG(R300_MC_READ_CNTL_AB);
295 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
296 }
297
298 mem_trbs = MemTrbs[data];
299 mem_tcas += mem_trbs;
300 }
301
302 if ((sd->Card.Type == RV100) || sd->Card.IsIGP) { /* RV100, M6, IGPs */
303 /* DDR64 SCLK_EFF = SCLK for analysis */
304 sclk_eff = sd->Card.sclk;
305 } else {
306 sclk_eff = sd->Card.sclk;
307 }
308
309 /* Find the memory controller latency for the display client.
310 */
311 if (IS_R300_VARIANT) {
312 /*not enough for R350 ???*/
313 /*
314 if (!mode2) sclk_delay = 150;
315 else {
316 if (info->RamWidth == 256) sclk_delay = 87;
317 else sclk_delay = 97;
318 }
319 */
320 sclk_delay = 250;
321 } else {
322 if ((sd->Card.Type == RV100) || sd->Card.IsIGP) {
323 if (sd->Card.IsDDR) sclk_delay = 41;
324 else sclk_delay = 33;
325 } else {
326 if (sd->Card.RamWidth == 128) sclk_delay = 57;
327 else sclk_delay = 41;
328 }
329 }
330
331 mc_latency_sclk = sclk_delay / sclk_eff;
332
333 if (sd->Card.IsDDR) {
334 if (sd->Card.RamWidth == 32) {
335 k1 = 40;
336 c = 3;
337 } else {
338 k1 = 20;
339 c = 1;
340 }
341 } else {
342 k1 = 40;
343 c = 3;
344 }
345 mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) /
346 sd->Card.mclk) + (4.0 / sclk_eff);
347
348 /*
349 HW cursor time assuming worst case of full size colour cursor.
350 */
351 cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (sd->Card.IsDDR+1))))) / sd->Card.mclk;
352 cur_latency_sclk = cur_size / sclk_eff;
353
354 /*
355 Find the total latency for the display data.
356 */
357 disp_latency_overhead = 8.0 / sd->Card.sclk;
358 mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk;
359 mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk;
360 disp_latency = MAX(mc_latency_mclk, mc_latency_sclk);
361
362 /*
363 Find the drain rate of the display buffer.
364 */
365 disp_drain_rate = pix_clk / (16.0/mode->bpp);
366
367 /*
368 Find the critical point of the display buffer.
369 */
370 critical_point= (ULONG)(disp_drain_rate * disp_latency + 0.5);
371
372 /* ???? */
373 /*
374 temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT;
375 if (critical_point < temp) critical_point = temp;
376 */
377
378 /*
379 The critical point should never be above max_stop_req-4. Setting
380 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
381 */
382 if (max_stop_req - critical_point < 4) critical_point = 0;
383
384 temp = sd->poweron_state->grph_buffer_cntl;
385 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
386 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
387 temp &= ~(RADEON_GRPH_START_REQ_MASK);
388 if ((sd->Card.Type == R350) &&
389 (stop_req > 0x15)) {
390 stop_req -= 0x10;
391 }
392 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
393
394 temp |= RADEON_GRPH_BUFFER_SIZE;
395 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
396 RADEON_GRPH_CRITICAL_AT_SOF |
397 RADEON_GRPH_STOP_CNTL);
398 /*
399 Write the result into the register.
400 */
401 OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
402 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
403
404 D(bug("[ATI] GRPH_BUFFER_CNTL from %x to %x\n",
405 sd->poweron_state->grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL)));
406
407 }
408
409 /*
410 * Powering done DAC, needed for DPMS problem with ViewSonic P817 (or its variant).
411 *
412 * Note for current DAC mapping when calling this function:
413 * For most of cards:
414 * single CRT: Driver doesn't change the existing CRTC->DAC mapping,
415 * CRTC1 could be driving either DAC or both DACs.
416 * CRT+CRT: CRTC1->TV DAC, CRTC2->Primary DAC
417 * DFP/LCD+CRT: CRTC2->TV DAC, CRTC2->Primary DAC.
418 * Some boards have two DACs reversed or don't even have a primary DAC,
419 * this is reflected in pRADEONEnt->ReversedDAC. And radeon 7200 doesn't
420 * have a second DAC.
421 * It's kind of messy, we'll need to redo DAC mapping part some day.
422 */
423 static void RADEONDacPowerSet(struct ati_staticdata *sd, BOOL IsOn, BOOL IsPrimaryDAC)
424 {
425 if (IsPrimaryDAC) {
426 ULONG dac_cntl;
427 ULONG dac_macro_cntl = 0;
428 dac_cntl = INREG(RADEON_DAC_CNTL);
429 if ((!sd->Card.IsMobility) || (sd->Card.Type == RV350))
430 dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL);
431 if (IsOn) {
432 dac_cntl &= ~RADEON_DAC_PDWN;
433 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
434 RADEON_DAC_PDWN_G |
435 RADEON_DAC_PDWN_B);
436 } else {
437 dac_cntl |= RADEON_DAC_PDWN;
438 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
439 RADEON_DAC_PDWN_G |
440 RADEON_DAC_PDWN_B);
441 }
442 OUTREG(RADEON_DAC_CNTL, dac_cntl);
443 if ((!sd->Card.IsMobility) || (sd->Card.Type == RV350))
444 OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
445 } else {
446 if (sd->Card.Type != R200) {
447 ULONG tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
448 if (IsOn) {
449 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
450 RADEON_TV_DAC_GDACPD |
451 RADEON_TV_DAC_BDACPD |
452 RADEON_TV_DAC_BGSLEEP);
453 } else {
454 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
455 RADEON_TV_DAC_GDACPD |
456 RADEON_TV_DAC_BDACPD |
457 RADEON_TV_DAC_BGSLEEP);
458 }
459 OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl);
460 } else {
461 ULONG fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL);
462 if (IsOn) {
463 fp2_gen_cntl |= RADEON_FP2_DVO_EN;
464 } else {
465 fp2_gen_cntl &= ~RADEON_FP2_DVO_EN;
466 }
467 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
468 }
469 }
470 }
471
472 /* Define common registers for requested video mode */
473 static void RADEONInitCommonRegisters(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *info)
474 {
475 save->ovr_clr = 0;
476 save->ovr_wid_left_right = 0;
477 save->ovr_wid_top_bottom = 0;
478 save->ov0_scale_cntl = 0;
479 save->subpic_cntl = 0;
480 save->viph_control = 0;
481 save->i2c_cntl_1 = 0;
482 save->rbbm_soft_reset = 0;
483 save->cap0_trig_cntl = 0;
484 save->cap1_trig_cntl = 0;
485 save->bus_cntl = sd->Card.BusCntl;
486 /*
487 * If bursts are enabled, turn on discards
488 * Radeon doesn't have write bursts
489 */
490 if (save->bus_cntl & (RADEON_BUS_READ_BURST))
491 save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
492 }
493
494 /* Define CRTC registers for requested video mode */
495 static BOOL RADEONInitCrtcRegisters(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
496 {
497 int format;
498 int hsync_start;
499 int hsync_wid;
500 int vsync_wid;
501
502 switch (mode->bpp) {
503 case 15: format = 3; mode->bpp = 16; break; /* 555 */
504 case 16: format = 4; break; /* 565 */
505 case 24: format = 5; mode->bpp = 32; break; /* RGB */
506 case 32: format = 6; break; /* xRGB */
507 default:
508 return FALSE;
509 }
510
511 if (mode->bpp == 16)
512 save->bpp = 2;
513 else
514 save->bpp = 4;
515
516 if ((sd->Card.MonType1 == MT_DFP) ||
517 (sd->Card.MonType1 == MT_LCD))
518 {
519 if (mode->Flags & RADEON_USE_RMX)
520 {
521 mode->HTotal = mode->HDisplay + sd->Card.HBlank;
522 mode->HSyncStart = mode->HDisplay + sd->Card.HOverPlus;
523 mode->HSyncEnd = mode->HSyncStart + sd->Card.HSyncWidth;
524
525 mode->VTotal = mode->VDisplay + sd->Card.VBlank;
526 mode->VSyncStart = mode->VDisplay + sd->Card.VOverPlus;
527 mode->VSyncEnd = mode->VSyncStart + sd->Card.VSyncWidth;
528
529 mode->pixelc = sd->Card.DotClock;
530 mode->Flags = sd->Card.Flags | RADEON_USE_RMX;
531 }
532 }
533
534 save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
535 | RADEON_CRTC_EN
536 | RADEON_CRTC_ARGB_EN
537 | (format << 8)
538 | ((mode->height < 400)
539 ? RADEON_CRTC_DBL_SCAN_EN
540 : 0));
541
542 if ((sd->Card.MonType1 == MT_DFP) ||
543 (sd->Card.MonType1 == MT_LCD)) {
544 save->crtc_ext_cntl = RADEON_VGA_ATI_LINEAR | RADEON_XCRT_CNT_EN;
545 save->crtc_gen_cntl &= ~(RADEON_CRTC_DBL_SCAN_EN |
546 RADEON_CRTC_CSYNC_EN |
547 RADEON_CRTC_INTERLACE_EN);
548 } else {
549 save->crtc_ext_cntl = (RADEON_VGA_ATI_LINEAR |
550 RADEON_XCRT_CNT_EN |
551 RADEON_CRTC_CRT_ON);
552 }
553
554 save->dac_cntl = (RADEON_DAC_MASK_ALL
555 | RADEON_DAC_VGA_ADR_EN
556 | RADEON_DAC_8BIT_EN);
557
558 save->crtc_h_total_disp = ((((mode->HTotal / 8) - 1) & 0x3ff)
559 | ((((mode->HDisplay / 8) - 1) & 0x1ff) << 16));
560
561 hsync_wid = (mode->HSyncEnd - mode->HSyncStart) / 8;
562 if (!hsync_wid) hsync_wid = 1;
563 hsync_start = mode->HSyncStart - 8;
564
565 save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
566 | ((hsync_wid & 0x3f) << 16));
567
568 /* This works for double scan mode. */
569 save->crtc_v_total_disp = (((mode->VTotal - 1) & 0xffff)
570 | ((mode->VDisplay - 1) << 16));
571
572 vsync_wid = mode->VSyncEnd - mode->VSyncStart;
573 if (!vsync_wid) vsync_wid = 1;
574
575 save->crtc_v_sync_strt_wid = (((mode->VSyncStart - 1) & 0xfff)
576 | ((vsync_wid & 0x1f) << 16));
577
578 save->crtc_offset = mode->base;
579 save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
580
581 save->crtc_pitch = (((mode->width * mode->bpp) +
582 ((mode->bpp * 8) -1)) /
583 (mode->bpp * 8));
584
585 D(bug("[RADEON] crtc_pitch = %08x\n", save->crtc_pitch));
586
587 save->crtc_pitch |= save->crtc_pitch << 16;
588
589 save->crtc_more_cntl = 0;
590 if ((sd->Card.Type == RS100) ||
591 (sd->Card.Type == RS200)) {
592 /* This is to workaround the asic bug for RMX, some versions
593 of BIOS dosen't have this register initialized correctly.
594 */
595 save->crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
596 }
597
598 save->surface_cntl = 0;
599 save->disp_merge_cntl = sd->poweron_state->disp_merge_cntl;
600 save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
601
602 #if AROS_BIG_ENDIAN
603 /* Alhought we current onlu use aperture 0, also setting aperture 1 should not harm -ReneR */
604 switch (mode->bpp) {
605 case 16:
606 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
607 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
608 break;
609
610 case 32:
611 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
612 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
613 break;
614 }
615 #endif
616
617 return TRUE;
618 }
619
620 /* Define CRTC registers for requested video mode */
621 static BOOL RADEONInitCrtc2Registers(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
622 {
623 int format;
624 int hsync_start;
625 int hsync_wid;
626 int vsync_wid;
627
628 switch (mode->bpp) {
629 case 15: format = 3; mode->bpp = 16; break; /* 555 */
630 case 16: format = 4; break; /* 565 */
631 case 24: format = 5; mode->bpp = 32; break; /* RGB */
632 case 32: format = 6; break; /* xRGB */
633 default:
634 return FALSE;
635 }
636
637 if (mode->bpp == 16)
638 save->bpp = 2;
639 else
640 save->bpp = 4;
641
642 save->crtc2_gen_cntl = (RADEON_CRTC2_EN
643 | RADEON_CRTC2_CRT2_ON
644 | RADEON_CRTC_ARGB_EN
645 | (format << 8)
646 | ((mode->height < 400)
647 ? RADEON_CRTC2_DBL_SCAN_EN
648 : 0));
649
650 /* Turn CRT on in case the first head is a DFP */
651 save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
652 save->dac2_cntl = sd->poweron_state->dac2_cntl;
653 /* always let TVDAC drive CRT2, we don't support tvout yet */
654 save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
655 save->disp_output_cntl = sd->poweron_state->disp_output_cntl;
656 if (sd->Card.Type == R200 || IS_R300_VARIANT) {
657 save->disp_output_cntl &= ~(RADEON_DISP_DAC_SOURCE_MASK |
658 RADEON_DISP_DAC2_SOURCE_MASK);
659 if (sd->Card.MonType2 != MT_CRT) {
660 save->disp_output_cntl |= (RADEON_DISP_DAC_SOURCE_CRTC2 |
661 RADEON_DISP_DAC2_SOURCE_CRTC2);
662 } else {
663 if (sd->Card.ReversedDAC) {
664 save->disp_output_cntl |= RADEON_DISP_DAC2_SOURCE_CRTC2;
665 } else {
666 save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
667 }
668 }
669 } else {
670 save->disp_hw_debug = sd->poweron_state->disp_hw_debug;
671 /* Turn on 2nd CRT */
672 if (sd->Card.MonType2 != MT_CRT) {
673 /* This is for some sample boards with the VGA port
674 connected to the TVDAC, but BIOS doesn't reflect this.
675 Here we configure both DACs to use CRTC2.
676 Not sure if this happens in any retail board.
677 */
678 save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
679 save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
680 } else {
681 if (sd->Card.ReversedDAC) {
682 save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
683 save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
684 } else {
685 save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
686 save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
687 }
688 }
689 }
690
691 save->crtc2_h_total_disp =
692 ((((mode->HTotal / 8) - 1) & 0x3ff)
693 | ((((mode->HDisplay / 8) - 1) & 0x1ff) << 16));
694
695 hsync_wid = (mode->HSyncEnd - mode->HSyncStart) / 8;
696 if (!hsync_wid) hsync_wid = 1;
697 hsync_start = mode->HSyncStart - 8;
698
699 save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
700 | ((hsync_wid & 0x3f) << 16));
701
702 /* This works for double scan mode. */
703 save->crtc2_v_total_disp = (((mode->VTotal - 1) & 0xffff)
704 | ((mode->VDisplay - 1) << 16));
705
706 vsync_wid = mode->VSyncEnd - mode->VSyncStart;
707 if (!vsync_wid) vsync_wid = 1;
708
709 save->crtc2_v_sync_strt_wid = (((mode->VSyncStart - 1) & 0xfff)
710 | ((vsync_wid & 0x1f) << 16));
711
712 save->crtc2_offset = mode->base;
713 save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
714 /* this should be right */
715 save->crtc2_pitch = (((mode->width * mode->bpp) +
716 ((mode->bpp * 8) -1)) /
717 (mode->bpp * 8));
718 save->crtc2_pitch |= save->crtc2_pitch << 16;
719
720 save->disp2_merge_cntl = sd->poweron_state->disp2_merge_cntl;
721 save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
722
723 if (sd->Card.MonType2 == MT_DFP && sd->Card.IsSecondary) {
724 save->crtc2_gen_cntl = (RADEON_CRTC2_EN | (format << 8));
725 save->fp2_h_sync_strt_wid = save->crtc2_h_sync_strt_wid;
726 save->fp2_v_sync_strt_wid = save->crtc2_v_sync_strt_wid;
727 save->fp2_gen_cntl = sd->poweron_state->fp2_gen_cntl | RADEON_FP2_ON;
728
729 if (sd->Card.Type == R200 || IS_R300_VARIANT) {
730 save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
731 RADEON_FP2_DVO_RATE_SEL_SDR);
732
733 save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 |
734 RADEON_FP2_DVO_EN);
735 } else {
736 save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_MASK;
737 save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
738 }
739
740 save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format */
741 }
742
743 save->surface_cntl = 0;
744
745 #if AROS_BIG_ENDIAN
746 /* Alhought we current onlu use aperture 0, also setting aperture 1 should not harm -ReneR */
747 switch (mode->bpp) {
748 case 16:
749 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
750 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
751 break;
752
753 case 32:
754 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
755 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
756 break;
757 }
758 #endif
759
760 return TRUE;
761 }
762
763 /* Define CRTC registers for requested video mode */
764 static void RADEONInitFPRegisters(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
765 {
766 int xres = mode->HDisplay;
767 int yres = mode->VDisplay;
768 float Hratio, Vratio;
769
770 /* If the FP registers have been initialized before for a panel,
771 * but the primary port is a CRT, we need to reinitialize
772 * FP registers in order for CRT to work properly
773 */
774
775 if ((sd->Card.MonType1 != MT_DFP) && (sd->Card.MonType1 != MT_LCD)) {
776 save->fp_crtc_h_total_disp = sd->poweron_state->fp_crtc_h_total_disp;
777 save->fp_crtc_v_total_disp = sd->poweron_state->fp_crtc_v_total_disp;
778 save->fp_gen_cntl = 0;
779 save->fp_h_sync_strt_wid = sd->poweron_state->fp_h_sync_strt_wid;
780 save->fp_horz_stretch = 0;
781 save->fp_v_sync_strt_wid = sd->poweron_state->fp_v_sync_strt_wid;
782 save->fp_vert_stretch = 0;
783 save->lvds_gen_cntl = sd->poweron_state->lvds_gen_cntl;
784 save->lvds_pll_cntl = sd->poweron_state->lvds_pll_cntl;
785 save->tmds_pll_cntl = sd->poweron_state->tmds_pll_cntl;
786 save->tmds_transmitter_cntl= sd->poweron_state->tmds_transmitter_cntl;
787
788 save->lvds_gen_cntl |= ( RADEON_LVDS_DISPLAY_DIS | (1 << 23));
789 save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON);
790 save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
791
792 return;
793 }
794
795 if (sd->Card.PanelXRes == 0 || sd->Card.PanelYRes == 0) {
796 Hratio = 1.0;
797 Vratio = 1.0;
798 } else {
799 if (xres > sd->Card.PanelXRes) xres = sd->Card.PanelXRes;
800 if (yres > sd->Card.PanelYRes) yres = sd->Card.PanelYRes;
801
802 Hratio = (float)xres/(float)sd->Card.PanelXRes;
803 Vratio = (float)yres/(float)sd->Card.PanelYRes;
804 }
805
806 if (Hratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
807 save->fp_horz_stretch = sd->poweron_state->fp_horz_stretch;
808 save->fp_horz_stretch &= ~(RADEON_HORZ_STRETCH_BLEND |
809 RADEON_HORZ_STRETCH_ENABLE);
810 save->fp_horz_stretch &= ~(RADEON_HORZ_AUTO_RATIO |
811 RADEON_HORZ_PANEL_SIZE);
812 save->fp_horz_stretch |= ((xres/8-1)<<16);
813 } else {
814 save->fp_horz_stretch =
815 ((((unsigned long)(Hratio * RADEON_HORZ_STRETCH_RATIO_MAX +
816 0.5)) & RADEON_HORZ_STRETCH_RATIO_MASK)) |
817 (sd->poweron_state->fp_horz_stretch & (RADEON_HORZ_PANEL_SIZE |
818 RADEON_HORZ_FP_LOOP_STRETCH |
819 RADEON_HORZ_AUTO_RATIO_INC));
820 save->fp_horz_stretch |= (RADEON_HORZ_STRETCH_BLEND |
821 RADEON_HORZ_STRETCH_ENABLE);
822
823 save->fp_horz_stretch &= ~(RADEON_HORZ_AUTO_RATIO |
824 RADEON_HORZ_PANEL_SIZE);
825 save->fp_horz_stretch |= ((sd->Card.PanelXRes / 8 - 1) << 16);
826 }
827
828 if (Vratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
829 save->fp_vert_stretch = sd->poweron_state->fp_vert_stretch;
830 save->fp_vert_stretch &= ~(RADEON_VERT_STRETCH_ENABLE|
831 RADEON_VERT_STRETCH_BLEND);
832 save->fp_vert_stretch &= ~(RADEON_VERT_AUTO_RATIO_EN |
833 RADEON_VERT_PANEL_SIZE);
834 save->fp_vert_stretch |= ((yres-1) << 12);
835 } else {
836 save->fp_vert_stretch =
837 (((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX +
838 0.5)) & RADEON_VERT_STRETCH_RATIO_MASK)) |
839 (sd->poweron_state->fp_vert_stretch & (RADEON_VERT_PANEL_SIZE |
840 RADEON_VERT_STRETCH_RESERVED)));
841 save->fp_vert_stretch |= (RADEON_VERT_STRETCH_ENABLE |
842 RADEON_VERT_STRETCH_BLEND);
843
844 save->fp_vert_stretch &= ~(RADEON_VERT_AUTO_RATIO_EN |
845 RADEON_VERT_PANEL_SIZE);
846 save->fp_vert_stretch |= ((sd->Card.PanelYRes-1) << 12);
847 }
848
849 save->fp_gen_cntl = (sd->poweron_state->fp_gen_cntl & (ULONG)
850 ~(RADEON_FP_SEL_CRTC2 |
851 RADEON_FP_RMX_HVSYNC_CONTROL_EN |
852 RADEON_FP_DFP_SYNC_SEL |
853 RADEON_FP_CRT_SYNC_SEL |
854 RADEON_FP_CRTC_LOCK_8DOT |
855 RADEON_FP_USE_SHADOW_EN |
856 RADEON_FP_CRTC_USE_SHADOW_VEND |
857 RADEON_FP_CRT_SYNC_ALT));
858 save->fp_gen_cntl |= (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
859 RADEON_FP_CRTC_DONT_SHADOW_HEND );
860
861 save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
862
863 if (IS_R300_VARIANT || (sd->Card.Type == R200)) {
864 save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
865 if (sd->Card.Flags & RADEON_USE_RMX)
866 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
867 else
868 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
869 } else
870 save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
871
872 save->lvds_gen_cntl = sd->poweron_state->lvds_gen_cntl;
873 save->lvds_pll_cntl = sd->poweron_state->lvds_pll_cntl;
874
875 save->tmds_pll_cntl = sd->poweron_state->tmds_pll_cntl;
876 save->tmds_transmitter_cntl= sd->poweron_state->tmds_transmitter_cntl;
877
878 if (sd->Card.MonType1 == MT_LCD) {
879
880 save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
881 save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
882
883 } else if (sd->Card.MonType1 == MT_DFP) {
884 int i;
885 ULONG tmp = sd->poweron_state->tmds_pll_cntl & 0xfffff;
886 for (i=0; i<4; i++) {
887 if (sd->Card.tmds_pll[i].freq == 0) break;
888 if (save->dot_clock_freq < sd->Card.tmds_pll[i].freq) {
889 tmp = sd->Card.tmds_pll[i].value ;
890 break;
891 }
892 }
893 if (IS_R300_VARIANT || (sd->Card.Type == RV280)) {
894 if (tmp & 0xfff00000)
895 save->tmds_pll_cntl = tmp;
896 else
897 save->tmds_pll_cntl = (sd->poweron_state->tmds_pll_cntl & 0xfff00000) | tmp;
898 } else save->tmds_pll_cntl = tmp;
899
900 D(bug("[ATI] TMDS_PLL from %x to %x\n",
901 sd->poweron_state->tmds_pll_cntl,
902 save->tmds_pll_cntl));
903
904 save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST);
905
906 if (IS_R300_VARIANT || (sd->Card.Type == R200)) // || !sd->Card.HasCRTC2)
907 save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
908 else /* weird, RV chips got this bit reversed? */
909 save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
910
911 save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
912 }
913
914 if (sd->Card.IsMobility) {
915 /* To work correctly with laptop hotkeys.
916 * Since there is no machnism for accessing ACPI evnets
917 * and the driver currently doesn't know how to validate
918 * a mode dynamically, we have to tell BIOS don't do
919 * display switching after X has started.
920 * If LCD is on, lid close/open should still work
921 * with below settings
922 */
923 if (sd->Card.MonType1 == MT_LCD) {
924 if (sd->Card.MonType2 == MT_CRT)
925 save->bios_5_scratch = 0x0201;
926 else if (sd->Card.MonType2 == MT_DFP)
927 save->bios_5_scratch = 0x0801;
928 else
929 save->bios_5_scratch = sd->poweron_state->bios_5_scratch;
930 } else {
931 if (sd->Card.MonType2 == MT_CRT)
932 save->bios_5_scratch = 0x0200;
933 else if (sd->Card.MonType2 == MT_DFP)
934 save->bios_5_scratch = 0x0800;
935 else
936 save->bios_5_scratch = 0x0;
937 }
938 save->bios_4_scratch = 0x4;
939 save->bios_6_scratch = sd->poweron_state->bios_6_scratch | 0x40000000;
940 }
941
942 save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
943 save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
944 save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
945 save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
946 }
947
948 static void RADEONInitPLLRegisters(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
949 {
950 double freq = mode->pixelc/10.0;
951
952 struct {
953 int divider;
954 int bitvalue;
955 } *post_div, post_divs[] = {
956 /* From RAGE 128 VR/RAGE 128 GL Register
957 * Reference Manual (Technical Reference
958 * Manual P/N RRG-G04100-C Rev. 0.04), page
959 * 3-17 (PLL_DIV_[3:0]).
960 */
961 { 1, 0 }, /* VCLK_SRC */
962 { 2, 1 }, /* VCLK_SRC/2 */
963 { 4, 2 }, /* VCLK_SRC/4 */
964 { 8, 3 }, /* VCLK_SRC/8 */
965 { 3, 4 }, /* VCLK_SRC/3 */
966 { 16, 5 }, /* VCLK_SRC/16 */
967 { 6, 6 }, /* VCLK_SRC/6 */
968 { 12, 7 }, /* VCLK_SRC/12 */
969 { 0, 0 }
970 };
971
972 if (freq > sd->Card.pll.max_pll_freq) freq = sd->Card.pll.max_pll_freq;
973 if (freq * 12 < sd->Card.pll.min_pll_freq) freq = sd->Card.pll.min_pll_freq / 12;
974
975 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
976 save->pll_output_freq = post_div->divider * freq;
977
978 if (save->pll_output_freq >= sd->Card.pll.min_pll_freq
979 && save->pll_output_freq <= sd->Card.pll.max_pll_freq) break;
980 }
981
982 if (!post_div->divider) {
983 save->pll_output_freq = freq;
984 post_div = &post_divs[0];
985 }
986
987 save->dot_clock_freq = freq;
988 save->feedback_div = RADEONDiv(sd->Card.pll.reference_div
989 * save->pll_output_freq,
990 sd->Card.pll.reference_freq);
991 save->post_div = post_div->divider;
992
993 D(bug("[ATI] dc=%d, of=%d, fd=%d, pd=%d\n",
994 save->dot_clock_freq,
995 save->pll_output_freq,
996 save->feedback_div,
997 save->post_div));
998
999 save->ppll_ref_div = sd->Card.pll.reference_div;
1000 save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
1001 save->htotal_cntl = 0;
1002 }
1003
1004 /* Define PLL2 registers for requested video mode */
1005 static void RADEONInitPLL2Registers(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
1006 {
1007 double freq = mode->pixelc/10.0;
1008
1009 struct {
1010 int divider;
1011 int bitvalue;
1012 } *post_div, post_divs[] = {
1013 /* From RAGE 128 VR/RAGE 128 GL Register
1014 * Reference Manual (Technical Reference
1015 * Manual P/N RRG-G04100-C Rev. 0.04), page
1016 * 3-17 (PLL_DIV_[3:0]).
1017 */
1018 { 1, 0 }, /* VCLK_SRC */
1019 { 2, 1 }, /* VCLK_SRC/2 */
1020 { 4, 2 }, /* VCLK_SRC/4 */
1021 { 8, 3 }, /* VCLK_SRC/8 */
1022 { 3, 4 }, /* VCLK_SRC/3 */
1023 { 6, 6 }, /* VCLK_SRC/6 */
1024 { 12, 7 }, /* VCLK_SRC/12 */
1025 { 0, 0 }
1026 };
1027
1028 if (freq > sd->Card.pll.max_pll_freq) freq = sd->Card.pll.max_pll_freq;
1029 if (freq * 12 < sd->Card.pll.min_pll_freq) freq = sd->Card.pll.min_pll_freq / 12;
1030
1031 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1032 save->pll_output_freq_2 = post_div->divider * freq;
1033 if (save->pll_output_freq_2 >= sd->Card.pll.min_pll_freq
1034 && save->pll_output_freq_2 <= sd->Card.pll.max_pll_freq) break;
1035 }
1036
1037 if (!post_div->divider) {
1038 save->pll_output_freq_2 = freq;
1039 post_div = &post_divs[0];
1040 }
1041
1042 save->dot_clock_freq_2 = freq;
1043 save->feedback_div_2 = RADEONDiv(sd->Card.pll.reference_div
1044 * save->pll_output_freq_2,
1045 sd->Card.pll.reference_freq);
1046 save->post_div_2 = post_div->divider;
1047
1048 D(bug("[ATI] dc=%d, of=%d, fd=%d, pd=%d\n",
1049 save->dot_clock_freq_2,
1050 save->pll_output_freq_2,
1051 save->feedback_div_2,
1052 save->post_div_2));
1053
1054 save->p2pll_ref_div = sd->Card.pll.reference_div;
1055 save->p2pll_div_0 = (save->feedback_div_2 |
1056 (post_div->bitvalue << 16));
1057 save->htotal_cntl2 = 0;
1058 }
1059
1060 static void RADEONGetVRamType(struct ati_staticdata *sd)
1061 {
1062 ULONG tmp;
1063
1064 if (sd->Card.IsIGP || (sd->Card.Type >= R300) ||
1065 (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30)))
1066 sd->Card.IsDDR = TRUE;
1067 else
1068 sd->Card.IsDDR = FALSE;
1069
1070 tmp = INREG(RADEON_MEM_CNTL);
1071 if (IS_R300_VARIANT) {
1072 tmp &= R300_MEM_NUM_CHANNELS_MASK;
1073 switch (tmp) {
1074 case 0: sd->Card.RamWidth = 64; break;
1075 case 1: sd->Card.RamWidth = 128; break;
1076 case 2: sd->Card.RamWidth = 256; break;
1077 default: sd->Card.RamWidth = 128; break;
1078 }
1079 } else if ((sd->Card.Type == RV100) ||
1080 (sd->Card.Type == RS100) ||
1081 (sd->Card.Type == RS200)){
1082 if (tmp & RV100_HALF_MODE) sd->Card.RamWidth = 32;
1083 else sd->Card.RamWidth = 64;
1084 } else {
1085 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) sd->Card.RamWidth = 128;
1086 else sd->Card.RamWidth = 64;
1087 }
1088
1089 /* This may not be correct, as some cards can have half of channel disabled
1090 * ToDo: identify these cases
1091 */
1092 }
1093
1094 struct RADEONInt10Save {
1095 ULONG MEM_CNTL;
1096 ULONG MEMSIZE;
1097 ULONG MPP_TB_CONFIG;
1098 };
1099
1100 #if 0
1101 static void RADEONPreInt10Save(struct ati_staticdata *sd, void **pPtr)
1102 {
1103 ULONG CardTmp;
1104 static struct RADEONInt10Save SaveStruct = { 0, 0, 0 };
1105
1106 /* Save the values and zap MEM_CNTL */
1107 SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
1108 SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
1109 SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
1110
1111 /*
1112 * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
1113 */
1114 OUTREG(RADEON_MEM_CNTL, 0);
1115 CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu;
1116 CardTmp |= 0x04 << 24;
1117 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
1118
1119 *pPtr = (void *)&SaveStruct;
1120 }
1121
1122 static void RADEONPostInt10Check(struct ati_staticdata *sd, void *ptr)
1123 {
1124 struct RADEONInt10Save *pSave = ptr;
1125 ULONG CardTmp;
1126
1127 /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */
1128 if (!pSave || !pSave->MEM_CNTL)
1129 return;
1130
1131 /*
1132 * If either MEM_CNTL is currently zero or inconistent (configured for
1133 * two channels with the two channels configured differently), restore
1134 * the saved registers.
1135 */
1136 CardTmp = INREG(RADEON_MEM_CNTL);
1137 if (!CardTmp ||
1138 ((CardTmp & 1) &&
1139 (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) {
1140 /* Restore the saved registers */
1141 D(bug("[ATI] Restoring MEM_CNTL (%08lx), setting to %08lx\n",
1142 (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL));
1143 OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL);
1144
1145 CardTmp = INREG(RADEON_CONFIG_MEMSIZE);
1146 if (CardTmp != pSave->MEMSIZE) {
1147 D(bug("[ATI] Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n",
1148 (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE));
1149 OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE);
1150 }
1151 }
1152
1153 CardTmp = INREG(RADEON_MPP_TB_CONFIG);
1154 if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) {
1155 D(bug("[ATI] Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n",
1156 (unsigned long)CardTmp >> 24,
1157 (unsigned long)pSave->MPP_TB_CONFIG >> 24));
1158 CardTmp &= 0x00ffffffu;
1159 CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u);
1160 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
1161 }
1162 }
1163 #endif
1164
1165 static void RADEONGetPanelInfo(struct ati_staticdata *sd)
1166 {
1167 }
1168
1169 static void RADEONGetClockInfo(struct ati_staticdata *sd)
1170 {
1171 RADEONPLLRec *pll = &sd->Card.pll;
1172
1173 if (RADEONGetClockInfoFromBIOS(sd)) {
1174 if (pll->reference_div < 2) {
1175 /* retrive it from register setting for fitting into current PLL algorithm.
1176 We'll probably need a new routine to calculate the best ref_div from BIOS
1177 provided min_input_pll and max_input_pll
1178 */
1179 ULONG tmp;
1180 tmp = RADEONINPLL(sd, RADEON_PPLL_REF_DIV);
1181 if (IS_R300_VARIANT ||
1182 (sd->Card.Type == RS300)) {
1183 pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
1184 } else {
1185 pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
1186 }
1187
1188 if (pll->reference_div < 2) pll->reference_div = 12;
1189 }
1190
1191 } else {
1192 D(bug("[ATI] Video BIOS not detected, using default clock settings!\n"));
1193
1194 if (sd->Card.IsIGP)
1195 pll->reference_freq = 1432;
1196 else
1197 pll->reference_freq = 2700;
1198
1199 pll->reference_div = 12;
1200 pll->min_pll_freq = 12500;
1201 pll->max_pll_freq = 35000;
1202 pll->xclk = 10300;
1203
1204 sd->Card.sclk = 200.00;
1205 sd->Card.mclk = 200.00;
1206 }
1207
1208 D(bug("[ATI] PLL parameters: rf=%d rd=%d min=%ld max=%ld; xclk=%d\n",
1209 pll->reference_freq,
1210 pll->reference_div,
1211 pll->min_pll_freq, pll->max_pll_freq, pll->xclk));
1212 }
1213
1214 BOOL HIDD_I2C_ProbeAddress(OOP_Object *obj, UWORD address);
1215
1216 #undef HiddI2CDeviceAttrBase
1217 #undef HiddI2CAttrBase
1218 #define HiddI2CDeviceAttrBase (sd->i2cDeviceAttrBase)
1219 #define HiddI2CAttrBase (sd->i2cAttrBase)
1220
1221 RADEONMonitorType RADEONDisplayDDCConnected(struct ati_staticdata *sd, RADEONDDCType type, RADEONConnector *port)
1222 {
1223 OOP_Object *i2c;
1224 RADEONMonitorType montyp = MT_NONE;
1225
1226 D(bug("[ATI] Probing monitor type\n"));
1227
1228 switch (type)
1229 {
1230 case DDC_MONID:
1231 sd->Card.DDCReg = RADEON_GPIO_MONID;
1232 break;
1233
1234 case DDC_DVI:
1235 sd->Card.DDCReg = RADEON_GPIO_DVI_DDC;
1236 break;
1237
1238 case DDC_VGA:
1239 sd->Card.DDCReg = RADEON_GPIO_VGA_DDC;
1240 break;
1241
1242 case DDC_CRT2:
1243 sd->Card.DDCReg = RADEON_GPIO_CRT2_DDC;
1244 break;
1245
1246 default:
1247 return MT_NONE;
1248 }
1249
1250 i2c = OOP_NewObject(sd->AtiI2C, NULL, NULL);
1251
1252 if (HIDD_I2C_ProbeAddress(i2c, 0xa0))
1253 {
1254 char edid[128];
1255 char wb[2] = {0, 0};
1256
1257 struct TagItem attrs[] = {
1258 { aHidd_I2CDevice_Driver, (IPTR)i2c },
1259 { aHidd_I2CDevice_Address, 0xa0 },
1260 { aHidd_I2CDevice_Name, (IPTR)"Display" },
1261 { TAG_DONE, 0UL }
1262 };
1263
1264 D(bug("[ATI] I2C device found\n"));
1265
1266 OOP_Object *obj = OOP_NewObject(NULL, CLID_Hidd_I2CDevice, attrs);
1267
1268 if (obj)
1269 {
1270 D(bug("[ATI] I2C Device @ %p\n", obj));
1271
1272 struct pHidd_I2CDevice_WriteRead msg;
1273
1274 msg.mID = OOP_GetMethodID((STRPTR)IID_Hidd_I2CDevice, moHidd_I2CDevice_WriteRead);
1275 msg.readBuffer = &edid[0];
1276 msg.readLength = 128;
1277 msg.writeBuffer = &wb[0];
1278 msg.writeLength = 1;
1279
1280 OOP_DoMethod(obj, &msg.mID);
1281
1282 int i;
1283
1284 D(bug("[ATI] DDC1 Dump:\n[ATI] "));
1285 for (i=0; i < 128; i++)
1286 {
1287 D(bug("%02x ", edid[i]));
1288
1289 if (i % 20 == 19)
1290 D(bug("\n[ATI] "));
1291 }
1292 D(bug("\n"));
1293
1294 OOP_DisposeObject(obj);
1295
1296 if (edid[0x14] & 0x80) {
1297 /* Note some laptops have a DVI output that uses internal TMDS,
1298 * when its DVI is enabled by hotkey, LVDS panel is not used.
1299 * In this case, the laptop is configured as DVI+VGA as a normal
1300 * desktop card.
1301 * Also for laptop, when X starts with lid closed (no DVI connection)
1302 * both LDVS and TMDS are disable, we still need to treat it as a LVDS panel.
1303 */
1304 if (port->TMDSType == TMDS_EXT) montyp = MT_DFP;
1305 else {
1306 if ((INREG(RADEON_FP_GEN_CNTL) & (1<<7)) || !sd->Card.IsMobility)
1307 montyp = MT_DFP;
1308 else
1309 montyp = MT_LCD;
1310 }
1311 } else montyp = MT_CRT;
1312 }
1313 }
1314
1315 OOP_DisposeObject(i2c);
1316
1317 return montyp;
1318 }
1319
1320 static BOOL RADEONQueryConnectedMonitors(struct ati_staticdata *sd)
1321 {
1322 int i = 0;
1323
1324 #if DEBUG
1325 const char *MonTypeName[7] =
1326 {
1327 "AUTO",
1328 "NONE",
1329 "CRT",
1330 "LVDS",
1331 "TMDS",
1332 "CTV",
1333 "STV"
1334 };
1335
1336 const RADEONMonitorType MonTypeID[7] =
1337 {
1338 MT_UNKNOWN, /* this is just a dummy value for AUTO DETECTION */
1339 MT_NONE, /* NONE -> NONE */
1340 MT_CRT, /* CRT -> CRT */
1341 MT_LCD, /* Laptop LCDs are driven via LVDS port */
1342 MT_DFP, /* DFPs are driven via TMDS */
1343 MT_CTV, /* CTV -> CTV */
1344 MT_STV, /* STV -> STV */
1345 };
1346
1347 const char *TMDSTypeName[3] =
1348 {
1349 "NONE",
1350 "Internal",
1351 "External"
1352 };
1353
1354 const char *DDCTypeName[5] =
1355 {
1356 "NONE",
1357 "MONID",
1358 "DVI_DDC",
1359 "VGA_DDC",
1360 "CRT2_DDC"
1361 };
1362
1363 const char *DACTypeName[3] =
1364 {
1365 "Unknown",
1366 "Primary",
1367 "TVDAC/ExtDAC",
1368 };
1369
1370 const char *ConnectorTypeName[8] =
1371 {
1372 "None",
1373 "Proprietary",
1374 "VGA",
1375 "DVI-I",
1376 "DVI-D",
1377 "CTV",
1378 "STV",
1379 "Unsupported"
1380 };
1381
1382 const char *ConnectorTypeNameATOM[10] =
1383 {
1384 "None",
1385 "VGA",
1386 "DVI-I",
1387 "DVI-D",
1388 "DVI-A",
1389 "STV",
1390 "CTV",
1391 "LVDS",
1392 "Digital",
1393 "Unsupported"
1394 };
1395 #endif
1396
1397 /*
1398 if(info->IsSecondary) {
1399 info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType2;
1400 if(info->DisplayType == MT_NONE) return FALSE;
1401 return TRUE;
1402 }
1403 */
1404
1405 /* We first get the information about all connectors from BIOS.
1406 * This is how the card is phyiscally wired up.
1407 * The information should be correct even on a OEM card.
1408 * If not, we may have problem -- need to use MonitorLayout option.
1409 */
1410 for (i = 0; i < 2; i++) {
1411 sd->Card.PortInfo[i].MonType = MT_UNKNOWN;
1412 // sd->Card.PortInfo[i].MonInfo = NULL;
1413 sd->Card.PortInfo[i].DDCType = DDC_NONE_DETECTED;
1414 sd->Card.PortInfo[i].DACType = DAC_UNKNOWN;
1415 sd->Card.PortInfo[i].TMDSType = TMDS_UNKNOWN;
1416 sd->Card.PortInfo[i].ConnectorType = CONNECTOR_NONE;
1417 }
1418
1419 if (!RADEONGetConnectorInfoFromBIOS(sd)) {
1420 /* Below is the most common setting, but may not be true */
1421 sd->Card.PortInfo[0].MonType = MT_UNKNOWN;
1422 // sd->Card.PortInfo[0].MonInfo = NULL;
1423 sd->Card.PortInfo[0].DDCType = DDC_DVI;
1424 sd->Card.PortInfo[0].DACType = DAC_TVDAC;
1425 sd->Card.PortInfo[0].TMDSType = TMDS_INT;
1426 sd->Card.PortInfo[0].ConnectorType = CONNECTOR_DVI_D;
1427
1428 sd->Card.PortInfo[1].MonType = MT_UNKNOWN;
1429 // sd->Card.PortInfo[1].MonInfo = NULL;
1430 sd->Card.PortInfo[1].DDCType = DDC_VGA;
1431 sd->Card.PortInfo[1].DACType = DAC_PRIMARY;
1432 sd->Card.PortInfo[1].TMDSType = TMDS_EXT;
1433 sd->Card.PortInfo[1].ConnectorType = CONNECTOR_CRT;
1434 }
1435
1436 /* always make TMDS_INT port first*/
1437 if (sd->Card.PortInfo[1].TMDSType == TMDS_INT) {
1438 RADEONConnector connector;
1439 connector = sd->Card.PortInfo[0];
1440 sd->Card.PortInfo[0] = sd->Card.PortInfo[1];
1441 sd->Card.PortInfo[1] = connector;
1442 } else if ((sd->Card.PortInfo[0].TMDSType != TMDS_INT &&
1443 sd->Card.PortInfo[1].TMDSType != TMDS_INT)) {
1444 /* no TMDS_INT port, make primary DAC port first */
1445 if (sd->Card.PortInfo[1].DACType == DAC_PRIMARY) {
1446 RADEONConnector connector;
1447 connector = sd->Card.PortInfo[0];
1448 sd->Card.PortInfo[0] = sd->Card.PortInfo[1];
1449 sd->Card.PortInfo[1] = connector;
1450 }
1451 }
1452
1453 if (sd->Card.HasSingleDAC) {
1454 /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/
1455 if (sd->Card.PortInfo[0].ConnectorType == CONNECTOR_CRT) {
1456 sd->Card.PortInfo[0].DACType = DAC_TVDAC;
1457 sd->Card.PortInfo[1].DACType = DAC_PRIMARY;
1458 } else {
1459 sd->Card.PortInfo[1].DACType = DAC_TVDAC;
1460 sd->Card.PortInfo[0].DACType = DAC_PRIMARY;
1461 }
1462 } else if (!sd->Card.HasCRTC2) {
1463 sd->Card.PortInfo[0].DACType = DAC_PRIMARY;
1464 }
1465
1466 if(((!sd->Card.HasCRTC2) || sd->Card.IsDellServer)) {
1467 if (sd->Card.PortInfo[0].MonType == MT_UNKNOWN) {
1468 if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_DVI, &sd->Card.PortInfo[0])));
1469 else if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_VGA, &sd->Card.PortInfo[0])));
1470 else if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_CRT2, &sd->Card.PortInfo[0])));
1471 else
1472 sd->Card.PortInfo[0].MonType = MT_CRT;
1473 }
1474
1475 sd->Card.MonType1 = sd->Card.PortInfo[0].MonType;
1476 // pRADEONEnt->MonInfo1 = sd->Card.PortInfo[0]. .MonInfo;
1477 sd->Card.MonType2 = MT_NONE;
1478 // pRADEONEnt->MonInfo2 = NULL;
1479
1480 D(bug("[ATI] Primary:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n",
1481 MonTypeName[sd->Card.PortInfo[0].MonType+1],
1482 sd->Card.IsAtomBios ?
1483 ConnectorTypeNameATOM[sd->Card.PortInfo[0].ConnectorType]:
1484 ConnectorTypeName[sd->Card.PortInfo[0].ConnectorType],
1485 DACTypeName[sd->Card.PortInfo[0].DACType+1],
1486 TMDSTypeName[sd->Card.PortInfo[0].TMDSType+1],
1487 DDCTypeName[sd->Card.PortInfo[0].DDCType]));
1488
1489 return TRUE;
1490 }
1491
1492 if (sd->Card.PortInfo[0].MonType == MT_UNKNOWN || sd->Card.PortInfo[1].MonType == MT_UNKNOWN) {
1493
1494 /* Primary Head (DVI or Laptop Int. panel)*/
1495 /* A ddc capable display connected on DVI port */
1496 if (sd->Card.PortInfo[0].MonType == MT_UNKNOWN) {
1497 if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, sd->Card.PortInfo[0].DDCType, &sd->Card.PortInfo[0])));
1498 else
1499 // if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_DVI, &sd->Card.PortInfo[0])));
1500 // else if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_VGA, &sd->Card.PortInfo[0])));
1501 // else if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_CRT2, &sd->Card.PortInfo[0])));
1502 // else
1503 if (sd->Card.IsMobility &&
1504 (INREG(RADEON_BIOS_4_SCRATCH) & 4)) {
1505 /* non-DDC laptop panel connected on primary */
1506 sd->Card.PortInfo[0].MonType = MT_LCD;
1507 } else {
1508 /* CRT on DVI, TODO: not reliable, make it always return false for now*/
1509 // sd->Card.PortInfo[0].MonType = RADEONCrtIsPhysicallyConnected(pScrn, !(pRADEONEnt->PortInfo[0].DACType));
1510 }
1511 }
1512
1513 /* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/
1514 if (sd->Card.PortInfo[1].MonType == MT_UNKNOWN) {
1515 if((sd->Card.PortInfo[1].MonType =
1516 RADEONDisplayDDCConnected(sd, sd->Card.PortInfo[1].DDCType, &sd->Card.PortInfo[1])));
1517 else
1518 // if((sd->Card.PortInfo[1].MonType = RADEONDisplayDDCConnected(sd, DDC_DVI, &sd->Card.PortInfo[1])));
1519 // else if((sd->Card.PortInfo[1].MonType = RADEONDisplayDDCConnected(sd, DDC_VGA, &sd->Card.PortInfo[1])));
1520 // else if((sd->Card.PortInfo[1].MonType = RADEONDisplayDDCConnected(sd, DDC_CRT2, &sd->Card.PortInfo[1])));
1521 // else
1522 if (sd->Card.IsMobility &&
1523 (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_ON)) {
1524 /* non-DDC TMDS panel connected through DVO */
1525 sd->Card.PortInfo[1].MonType = MT_DFP;
1526 }
1527 //else
1528 // sd->Card.PortInfo[1].MonType = RADEONCrtIsPhysicallyConnected(pScrn, !(pRADEONEnt->PortInfo[1].DACType));
1529
1530 }
1531 }
1532
1533 sd->Card.MonType1 = sd->Card.PortInfo[0].MonType;
1534 sd->Card.MonType2 = sd->Card.PortInfo[1].MonType;
1535 if (sd->Card.PortInfo[0].MonType == MT_NONE) {
1536 if (sd->Card.PortInfo[1].MonType == MT_NONE) {
1537 sd->Card.MonType1 = MT_CRT;
1538 } else {
1539 RADEONConnector tmp;
1540 sd->Card.MonType1 = sd->Card.PortInfo[1].MonType;
1541 tmp = sd->Card.PortInfo[0];
1542 sd->Card.PortInfo[0] = sd->Card.PortInfo[1];
1543 sd->Card.PortInfo[1] = tmp;
1544 }
1545 sd->Card.MonType2 = MT_NONE;
1546 }
1547 sd->Card.ReversedDAC = FALSE;
1548 sd->Card.OverlayOnCRTC2 = FALSE;
1549
1550 if (sd->Card.MonType2 != MT_NONE) {
1551
1552 if (sd->Card.PortInfo[1].DACType == DAC_TVDAC) {
1553 D(bug("[ATI] Reversed DAC decteced\n"));
1554 sd->Card.ReversedDAC = TRUE;
1555 }
1556 } else {
1557 sd->Card.HasSecondary = FALSE;
1558 }
1559 D(bug("[ATI] Primary:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n",
1560 MonTypeName[sd->Card.PortInfo[0].MonType+1],
1561 sd->Card.IsAtomBios ?
1562 ConnectorTypeNameATOM[sd->Card.PortInfo[0].ConnectorType]:
1563 ConnectorTypeName[sd->Card.PortInfo[0].ConnectorType],
1564 DACTypeName[sd->Card.PortInfo[0].DACType+1],
1565 TMDSTypeName[sd->Card.PortInfo[0].TMDSType+1],
1566 DDCTypeName[sd->Card.PortInfo[0].DDCType]));
1567
1568 D(bug("[ATI] Secondary:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n",
1569 MonTypeName[sd->Card.PortInfo[1].MonType+1],
1570 sd->Card.IsAtomBios ?
1571 ConnectorTypeNameATOM[sd->Card.PortInfo[1].ConnectorType]:
1572 ConnectorTypeName[sd->Card.PortInfo[1].ConnectorType],
1573 DACTypeName[sd->Card.PortInfo[1].DACType+1],
1574 TMDSTypeName[sd->Card.PortInfo[1].TMDSType+1],
1575 DDCTypeName[sd->Card.PortInfo[1].DDCType]));
1576
1577 return TRUE;
1578 }
1579
1580
1581
1582
1583 /*
1584 * Accesible functions
1585 */
1586
1587 void InitMode(struct ati_staticdata *sd, struct CardState *save,
1588 ULONG width, ULONG height, UBYTE bpp, ULONG pixelc, IPTR base,
1589 ULONG HDisplay, ULONG VDisplay,
1590 ULONG HSyncStart, ULONG HSyncEnd, ULONG HTotal,
1591 ULONG VSyncStart, ULONG VSyncEnd, ULONG VTotal)
1592 {
1593 RADEONModeInfo info = {
1594 width, height, bpp, pixelc, base,
1595 HDisplay, VDisplay, HSyncStart, HSyncEnd, HTotal,
1596 VSyncStart, VSyncEnd, VTotal };
1597
1598 RADEONInitCommonRegisters(sd, save, &info);
1599
1600 if (sd->Card.IsSecondary)
1601 {
1602 RADEONInitCrtc2Registers(sd, save, &info);
1603 RADEONInitPLL2Registers(sd, save, &info);
1604 }
1605 else
1606 {
1607 RADEONInitCrtcRegisters(sd, save, &info);
1608 RADEONInitPLLRegisters(sd, save, &info);
1609 }
1610 RADEONInitFPRegisters(sd, save, &info);
1611
1612 save->pixelc = info.pixelc;
1613 save->HDisplay = info.HDisplay;
1614 }
1615
1616 void ShowHideCursor(struct ati_staticdata *sd, BOOL visible)
1617 {
1618 D(bug("[ATI] ShowHideCursor: %s\n", visible ? "show":"hide"));
1619
1620 if (visible)
1621 {
1622 if (sd->Card.IsSecondary)
1623 OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN, ~RADEON_CRTC2_CUR_EN);
1624 else
1625 OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN, ~RADEON_CRTC_CUR_EN);
1626 }
1627 else
1628 {
1629 if (sd->Card.IsSecondary)
1630 OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN);
1631 else
1632 OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_CUR_EN);
1633 }
1634 }
1635
1636 void SaveState(struct ati_staticdata *sd, struct CardState *save)
1637 {
1638 save->dp_datatype = INREG(RADEON_DP_DATATYPE);
1639 save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
1640 save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
1641 if (sd->Card.R300CGWorkaround) R300CGWorkaround(sd);
1642
1643 // Common registers
1644 save->ovr_clr = INREG(RADEON_OVR_CLR);
1645 save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT);
1646 save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM);
1647 save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
1648 save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL);
1649 save->viph_control = INREG(RADEON_VIPH_CONTROL);
1650 save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1);
1651 save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
1652 save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNTL);
1653 save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL);
1654 save->bus_cntl = INREG(RADEON_BUS_CNTL);
1655 save->surface_cntl = INREG(RADEON_SURFACE_CNTL);
1656 save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL);
1657 save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL);
1658
1659 if (!sd->Card.IsSecondary)
1660 {
1661 // PLL
1662 save->ppll_ref_div = RADEONINPLL(sd, RADEON_PPLL_REF_DIV);
1663 save->ppll_div_3 = RADEONINPLL(sd, RADEON_PPLL_DIV_3);
1664 save->htotal_cntl = RADEONINPLL(sd, RADEON_HTOTAL_CNTL);
1665
1666 // CRTC
1667 save->crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
1668 save->crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
1669 save->dac_cntl = INREG(RADEON_DAC_CNTL);
1670 save->crtc_h_total_disp = INREG(RADEON_CRTC_H_TOTAL_DISP);
1671 save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID);
1672 save->crtc_v_total_disp = INREG(RADEON_CRTC_V_TOTAL_DISP);
1673 save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID);
1674 save->crtc_offset = INREG(RADEON_CRTC_OFFSET);
1675 save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
1676 save->crtc_pitch = INREG(RADEON_CRTC_PITCH);
1677 save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL);
1678 save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL);
1679
1680 if (sd->Card.IsDellServer) {
1681 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
1682 save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
1683 save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG);
1684 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
1685 }
1686
1687 // Flat panel
1688 save->fp_crtc_h_total_disp = INREG(RADEON_FP_CRTC_H_TOTAL_DISP);
1689 save->fp_crtc_v_total_disp = INREG(RADEON_FP_CRTC_V_TOTAL_DISP);
1690 save->fp_gen_cntl = INREG(RADEON_FP_GEN_CNTL);
1691 save->fp_h_sync_strt_wid = INREG(RADEON_FP_H_SYNC_STRT_WID);
1692 save->fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH);
1693 save->fp_v_sync_strt_wid = INREG(RADEON_FP_V_SYNC_STRT_WID);
1694 save->fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH);
1695 save->lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL);
1696 save->lvds_pll_cntl = INREG(RADEON_LVDS_PLL_CNTL);
1697 save->tmds_pll_cntl = INREG(RADEON_TMDS_PLL_CNTL);
1698 save->tmds_transmitter_cntl= INREG(RADEON_TMDS_TRANSMITTER_CNTL);
1699 save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH);
1700 save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH);
1701 save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH);
1702
1703 if (sd->Card.Type == RV280) {
1704 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
1705 save->tmds_pll_cntl ^= (1 << 22);
1706 }
1707 }
1708 else
1709 {
1710 // CRTC2
1711 save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
1712 save->disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL);
1713 save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG);
1714
1715 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
1716 save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP);
1717 save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID);
1718 save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP);
1719 save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID);
1720 save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET);
1721 save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
1722 save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH);
1723
1724 save->fp2_h_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID);
1725 save->fp2_v_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID);
1726 save->fp2_gen_cntl = INREG (RADEON_FP2_GEN_CNTL);
1727 save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL);
1728
1729 // PLL2
1730 save->p2pll_ref_div = RADEONINPLL(sd, RADEON_P2PLL_REF_DIV);
1731 save->p2pll_div_0 = RADEONINPLL(sd, RADEON_P2PLL_DIV_0);
1732 save->htotal_cntl2 = RADEONINPLL(sd, RADEON_HTOTAL2_CNTL);
1733 }
1734 }
1735
1736 /* Write common registers */
1737 static void RADEONRestoreCommonRegisters(struct ati_staticdata *sd, struct CardState *restore)
1738 {
1739 OUTREG(RADEON_OVR_CLR, restore->ovr_clr);
1740 OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
1741 OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
1742 OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
1743 OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl);
1744 OUTREG(RADEON_VIPH_CONTROL, restore->viph_control);
1745 OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1);
1746 OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl);
1747 OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
1748 OUTREG(RADEON_CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
1749 OUTREG(RADEON_BUS_CNTL, restore->bus_cntl);
1750 OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl);
1751 }
1752
1753 static void RADEONRestoreCrtcRegisters(struct ati_staticdata *sd, struct CardState *restore)
1754 {
1755 /* We prevent the CRTC from hitting the memory controller until
1756 * fully programmed
1757 */
1758 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl |
1759 RADEON_CRTC_DISP_REQ_EN_B);
1760
1761 OUTREGP(RADEON_CRTC_EXT_CNTL,
1762 restore->crtc_ext_cntl,
1763 RADEON_CRTC_VSYNC_DIS |
1764 RADEON_CRTC_HSYNC_DIS |
1765 RADEON_CRTC_DISPLAY_DIS);
1766
1767 OUTREGP(RADEON_DAC_CNTL,
1768 restore->dac_cntl,
1769 RADEON_DAC_RANGE_CNTL |
1770 RADEON_DAC_BLANKING);
1771
1772 OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
1773 OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
1774 OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
1775 OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
1776 OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset);
1777 OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
1778 OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch);
1779 OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl);
1780 OUTREG(RADEON_CRTC_MORE_CNTL, restore->crtc_more_cntl);
1781
1782 if (sd->Card.IsDellServer) {
1783 OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
1784 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
1785 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
1786 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
1787 }
1788
1789 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
1790
1791 }
1792
1793 static void RADEONRestoreCrtc2Registers(struct ati_staticdata *sd, struct CardState *restore)
1794 {
1795 ULONG crtc2_gen_cntl;
1796
1797 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) &
1798 (RADEON_CRTC2_VSYNC_DIS |
1799 RADEON_CRTC2_HSYNC_DIS |
1800 RADEON_CRTC2_DISP_DIS);
1801 crtc2_gen_cntl |= restore->crtc2_gen_cntl;
1802
1803 /* We prevent the CRTC from hitting the memory controller until
1804 * fully programmed
1805 */
1806 OUTREG(RADEON_CRTC2_GEN_CNTL,
1807 crtc2_gen_cntl | RADEON_CRTC2_DISP_REQ_EN_B);
1808
1809 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
1810
1811 OUTREG(RADEON_TV_DAC_CNTL, 0x00280203);
1812 if ((sd->Card.Type == R200) ||
1813 IS_R300_VARIANT) {
1814 OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
1815 } else {
1816 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
1817 }
1818
1819 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
1820 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
1821 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
1822 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
1823 OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset);
1824 OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
1825 OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
1826 OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
1827
1828 if ((sd->Card.MonType2 == MT_DFP && sd->Card.IsSecondary))
1829 {
1830 OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp2_h_sync_strt_wid);
1831 OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp2_v_sync_strt_wid);
1832 OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl);
1833 }
1834
1835 OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1836 }
1837
1838 static void RADEONRestoreFPRegisters(struct ati_staticdata *sd, struct CardState *restore)
1839 {
1840 unsigned long tmp;
1841
1842 OUTREG(RADEON_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
1843 OUTREG(RADEON_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
1844 OUTREG(RADEON_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
1845 OUTREG(RADEON_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
1846 OUTREG(RADEON_TMDS_PLL_CNTL, restore->tmds_pll_cntl);
1847 OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl);
1848 OUTREG(RADEON_FP_HORZ_STRETCH, restore->fp_horz_stretch);
1849 OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch);
1850 OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl);
1851
1852 /* old AIW Radeon has some BIOS initialization problem
1853 * with display buffer underflow, only occurs to DFP
1854 */
1855 if (!sd->Card.HasCRTC2)
1856 OUTREG(RADEON_GRPH_BUFFER_CNTL,
1857 INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
1858
1859 if (sd->Card.IsMobility) {
1860 OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch);
1861 OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch);
1862 OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch);
1863 }
1864
1865 if (sd->Card.MonType1 != MT_DFP) {
1866 unsigned long tmpPixclksCntl = INPLL(sd, RADEON_PIXCLKS_CNTL);
1867
1868 if (sd->Card.IsMobility || sd->Card.IsIGP) {
1869 /* Asic bug, when turning off LVDS_ON, we have to make sure
1870 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1871 */
1872 if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) {
1873 OUTPLLP(sd, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
1874 }
1875 }
1876
1877 tmp = INREG(RADEON_LVDS_GEN_CNTL);
1878 if ((tmp & (RADEON_LVDS_ON | RADEON_LVDS_BLON)) ==
1879 (restore->lvds_gen_cntl & (RADEON_LVDS_ON | RADEON_LVDS_BLON))) {
1880 OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
1881 } else {
1882 if (restore->lvds_gen_cntl & (RADEON_LVDS_ON | RADEON_LVDS_BLON)) {
1883 usleep(sd, sd->Card.PanelPwrDly * 1000);
1884 OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
1885 } else {
1886 OUTREG(RADEON_LVDS_GEN_CNTL,
1887 restore->lvds_gen_cntl | RADEON_LVDS_BLON);
1888 usleep(sd, sd->Card.PanelPwrDly * 1000);
1889 OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
1890 }
1891 }
1892
1893 if (sd->Card.IsMobility || sd->Card.IsIGP) {
1894 if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) {
1895 OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
1896 }
1897 }
1898 }
1899 }
1900
1901 static void RADEONPLLWaitForReadUpdateComplete(struct ati_staticdata *sd)
1902 {
1903 int i = 0;
1904
1905 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1906 the cause yet, but this workaround will mask the problem for now.
1907 Other chips usually will pass at the very first test, so the
1908 workaround shouldn't have any effect on them. */
1909 for (i = 0;
1910 (i < 10000 &&
1911 INPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
1912 i++);
1913 }
1914
1915 static void RADEONPLLWriteUpdate(struct ati_staticdata *sd)
1916 {
1917 while (INPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
1918
1919 OUTPLLP(sd, RADEON_PPLL_REF_DIV,
1920 RADEON_PPLL_ATOMIC_UPDATE_W,
1921 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
1922 }
1923
1924 static void RADEONPLL2WaitForReadUpdateComplete(struct ati_staticdata *sd)
1925 {
1926 int i = 0;
1927
1928 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1929 the cause yet, but this workaround will mask the problem for now.
1930 Other chips usually will pass at the very first test, so the
1931 workaround shouldn't have any effect on them. */
1932 for (i = 0;
1933 (i < 10000 &&
1934 INPLL(sd, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
1935 i++);
1936 }
1937
1938 static void RADEONPLL2WriteUpdate(struct ati_staticdata *sd)
1939 {
1940 while (INPLL(sd, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
1941
1942 OUTPLLP(sd, RADEON_P2PLL_REF_DIV,
1943 RADEON_P2PLL_ATOMIC_UPDATE_W,
1944 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
1945 }
1946
1947
1948 /* Write PLL registers */
1949 static void RADEONRestorePLLRegisters(struct ati_staticdata *sd, struct CardState *restore)
1950 {
1951 if (sd->Card.IsMobility) {
1952 /* A temporal workaround for the occational blanking on certain laptop panels.
1953 This appears to related to the PLL divider registers (fail to lock?).
1954 It occurs even when all dividers are the same with their old settings.
1955 In this case we really don't need to fiddle with PLL registers.
1956 By doing this we can avoid the blanking problem with some panels.
1957 */
1958 if ((restore->ppll_ref_div == (INPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
1959 (restore->ppll_div_3 == (INPLL(sd, RADEON_PPLL_DIV_3) &
1960 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
1961 OUTREGP(RADEON_CLOCK_CNTL_INDEX,
1962 RADEON_PLL_DIV_SEL,
1963 ~(RADEON_PLL_DIV_SEL));
1964 RADEONPllErrataAfterIndex(sd);
1965 return;
1966 }
1967 }
1968
1969 OUTPLLP(sd, RADEON_VCLK_ECP_CNTL,
1970 RADEON_VCLK_SRC_SEL_CPUCLK,
1971 ~(RADEON_VCLK_SRC_SEL_MASK));
1972
1973 OUTPLLP(sd,
1974 RADEON_PPLL_CNTL,
1975 RADEON_PPLL_RESET
1976 | RADEON_PPLL_ATOMIC_UPDATE_EN
1977 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN,
1978 ~(RADEON_PPLL_RESET
1979 | RADEON_PPLL_ATOMIC_UPDATE_EN
1980 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1981
1982 OUTREGP(RADEON_CLOCK_CNTL_INDEX,
1983 RADEON_PLL_DIV_SEL,
1984 ~(RADEON_PLL_DIV_SEL));
1985 RADEONPllErrataAfterIndex(sd);
1986
1987 if (IS_R300_VARIANT ||
1988 (sd->Card.Type == RS300)) {
1989 if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1990 /* When restoring console mode, use saved PPLL_REF_DIV
1991 * setting.
1992 */
1993 OUTPLLP(sd, RADEON_PPLL_REF_DIV,
1994 restore->ppll_ref_div,
1995 0);
1996 } else {
1997 /* R300 uses ref_div_acc field as real ref divider */
1998 OUTPLLP(sd, RADEON_PPLL_REF_DIV,
1999 (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
2000 ~R300_PPLL_REF_DIV_ACC_MASK);
2001 }
2002 } else {
2003 OUTPLLP(sd, RADEON_PPLL_REF_DIV,
2004 restore->ppll_ref_div,
2005 ~RADEON_PPLL_REF_DIV_MASK);
2006 }
2007
2008 OUTPLLP(sd, RADEON_PPLL_DIV_3,
2009 restore->ppll_div_3,
2010 ~RADEON_PPLL_FB3_DIV_MASK);
2011
2012 OUTPLLP(sd, RADEON_PPLL_DIV_3,
2013 restore->ppll_div_3,
2014 ~RADEON_PPLL_POST3_DIV_MASK);
2015
2016 RADEONPLLWriteUpdate(sd);
2017 RADEONPLLWaitForReadUpdateComplete(sd);
2018
2019 OUTPLL(RADEON_HTOTAL_CNTL, restore->htotal_cntl);
2020
2021 OUTPLLP(sd, RADEON_PPLL_CNTL,
2022 0,
2023 ~(RADEON_PPLL_RESET
2024 | RADEON_PPLL_SLEEP
2025 | RADEON_PPLL_ATOMIC_UPDATE_EN
2026 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
2027
2028 usleep(sd, 50000); /* Let the clock to lock */
2029
2030 OUTPLLP(sd, RADEON_VCLK_ECP_CNTL,
2031 RADEON_VCLK_SRC_SEL_PPLLCLK,
2032 ~(RADEON_VCLK_SRC_SEL_MASK));
2033 }
2034
2035 static void RADEONRestorePLL2Registers(struct ati_staticdata *sd, struct CardState *restore)
2036 {
2037 OUTPLLP(sd, RADEON_PIXCLKS_CNTL,
2038 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
2039 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
2040
2041 OUTPLLP(sd,
2042 RADEON_P2PLL_CNTL,
2043 RADEON_P2PLL_RESET
2044 | RADEON_P2PLL_ATOMIC_UPDATE_EN
2045 | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN,
2046 ~(RADEON_P2PLL_RESET
2047 | RADEON_P2PLL_ATOMIC_UPDATE_EN
2048 | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN));
2049
2050 OUTPLLP(sd, RADEON_P2PLL_REF_DIV,
2051 restore->p2pll_ref_div,
2052 ~RADEON_P2PLL_REF_DIV_MASK);
2053
2054 OUTPLLP(sd, RADEON_P2PLL_DIV_0,
2055 restore->p2pll_div_0,
2056 ~RADEON_P2PLL_FB0_DIV_MASK);
2057
2058 OUTPLLP(sd, RADEON_P2PLL_DIV_0,
2059 restore->p2pll_div_0,
2060 ~RADEON_P2PLL_POST0_DIV_MASK);
2061
2062 RADEONPLL2WriteUpdate(sd);
2063 RADEONPLL2WaitForReadUpdateComplete(sd);
2064
2065 OUTPLL(RADEON_HTOTAL2_CNTL, restore->htotal_cntl2);
2066
2067 OUTPLLP(sd, RADEON_P2PLL_CNTL,
2068 0,
2069 ~(RADEON_P2PLL_RESET
2070 | RADEON_P2PLL_SLEEP
2071 | RADEON_P2PLL_ATOMIC_UPDATE_EN
2072 | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN));
2073
2074 usleep(sd, 5000); /* Let the clock to lock */
2075
2076 OUTPLLP(sd, RADEON_PIXCLKS_CNTL,
2077 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
2078 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
2079 }
2080
2081 void LoadState(struct ati_staticdata *sd, struct CardState *restore)
2082 {
2083 RADEONBlank(sd);
2084
2085 /* For Non-dual head card, we don't have private field in the Entity */
2086 if (!sd->Card.HasCRTC2) {
2087 RADEONRestoreCommonRegisters(sd, restore);
2088 RADEONRestoreCrtcRegisters(sd, restore);
2089 RADEONRestoreFPRegisters(sd, restore);
2090 RADEONRestorePLLRegisters(sd, restore);
2091
2092 RADEONUnblank(sd);
2093
2094 RADEONInitDispBandwidth(sd, restore);
2095
2096 SetGamma(sd, 1.0, 1.0, 1.0);
2097
2098 return;
2099 }
2100
2101 if (sd->Card.IsSecondary) {
2102 RADEONRestoreCommonRegisters(sd, restore);
2103 RADEONRestoreCrtc2Registers(sd, restore);
2104 RADEONRestorePLL2Registers(sd, restore);
2105 }
2106 else
2107 {
2108 RADEONRestoreCommonRegisters(sd, restore);
2109
2110 if (!sd->Card.HasSecondary) {
2111 RADEONRestoreCrtcRegisters(sd, restore);
2112 RADEONRestoreFPRegisters(sd, restore);
2113 RADEONRestorePLLRegisters(sd, restore);
2114 } else {
2115 RADEONRestoreCrtcRegisters(sd, restore);
2116 RADEONRestoreFPRegisters(sd, restore);
2117 RADEONRestorePLLRegisters(sd, restore);
2118 RADEONRestoreCrtc2Registers(sd, restore);
2119 RADEONRestorePLL2Registers(sd, restore);
2120 }
2121 }
2122
2123 RADEONUnblank(sd);
2124
2125 RADEONInitDispBandwidth(sd, restore);
2126
2127 SetGamma(sd, 1.0, 1.0, 1.0);
2128 }
2129
2130 void DPMS(struct ati_staticdata *sd, HIDDT_DPMSLevel level)
2131 {
2132 int mask1 = (RADEON_CRTC_DISPLAY_DIS |
2133 RADEON_CRTC_HSYNC_DIS |
2134 RADEON_CRTC_VSYNC_DIS);
2135 int mask2 = (RADEON_CRTC2_DISP_DIS |
2136 RADEON_CRTC2_VSYNC_DIS |
2137 RADEON_CRTC2_HSYNC_DIS);
2138
2139 switch (level)
2140 {
2141 case vHidd_Gfx_DPMSLevel_On:
2142 /* Screen: On; HSync: On, VSync: On */
2143 if (sd->Card.IsSecondary)
2144 OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask2);
2145 else {
2146 OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask1);
2147 }
2148 break;
2149
2150 case vHidd_Gfx_DPMSLevel_Standby:
2151 /* Screen: Off; HSync: Off, VSync: On */
2152 if (sd->Card.IsSecondary)
2153 OUTREGP(RADEON_CRTC2_GEN_CNTL,
2154 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS,
2155 ~mask2);
2156 else {
2157 OUTREGP(RADEON_CRTC_EXT_CNTL,
2158 RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS,
2159 ~mask1);
2160 }
2161 break;
2162
2163 case vHidd_Gfx_DPMSLevel_Suspend:
2164 /* Screen: Off; HSync: On, VSync: Off */
2165 if (sd->Card.IsSecondary)
2166 OUTREGP(RADEON_CRTC2_GEN_CNTL,
2167 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS,
2168 ~mask2);
2169 else {
2170 OUTREGP(RADEON_CRTC_EXT_CNTL,
2171 RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS,
2172 ~mask1);
2173 }
2174 break;
2175
2176 case vHidd_Gfx_DPMSLevel_Off:
2177 /* Screen: Off; HSync: Off, VSync: Off */
2178 if (sd->Card.IsSecondary)
2179 OUTREGP(RADEON_CRTC2_GEN_CNTL, mask2, ~mask2);
2180 else {
2181 OUTREGP(RADEON_CRTC_EXT_CNTL, mask1, ~mask1);
2182 }
2183 break;
2184 }
2185 if (level == vHidd_Gfx_DPMSLevel_On)
2186 {
2187 if (sd->Card.IsSecondary) {
2188 if (sd->Card.MonType2 == MT_DFP) {
2189 OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
2190 OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON);
2191 if (sd->Card.Type >= R200) {
2192 OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DVO_EN, ~RADEON_FP2_DVO_EN);
2193 }
2194 } else if (sd->Card.MonType2 == MT_CRT) {
2195 RADEONDacPowerSet(sd, TRUE, !sd->Card.ReversedDAC);
2196 }
2197 } else {
2198 if (sd->Card.MonType1 == MT_DFP) {
2199 OUTREGP (RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN),
2200 ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN));
2201 } else if (sd->Card.MonType1 == MT_LCD) {
2202
2203 OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON);
2204 usleep (sd, sd->Card.PanelPwrDly * 1000);
2205 OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON);
2206 } else if (sd->Card.MonType1 == MT_CRT) {
2207 if (sd->Card.HasSecondary) {
2208 RADEONDacPowerSet(sd, TRUE, sd->Card.ReversedDAC);
2209 } else {
2210 RADEONDacPowerSet(sd, TRUE, TRUE);
2211 if (sd->Card.HasCRTC2)
2212 RADEONDacPowerSet(sd, TRUE, FALSE);
2213 }
2214 }
2215 }
2216 }
2217 else if ((level == vHidd_Gfx_DPMSLevel_Off) ||
2218 (level == vHidd_Gfx_DPMSLevel_Suspend) ||
2219 (level == vHidd_Gfx_DPMSLevel_Standby))
2220 {
2221 if (sd->Card.IsSecondary) {
2222 if (sd->Card.MonType2 == MT_DFP) {
2223 OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN);
2224 OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON);
2225 if (sd->Card.Type >= R200) {
2226 OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DVO_EN);
2227 }
2228 } else if (sd->Card.MonType2 == MT_CRT) {
2229 RADEONDacPowerSet(sd, FALSE, !sd->Card.ReversedDAC);
2230 }
2231 } else {
2232 if (sd->Card.MonType1 == MT_DFP) {
2233 OUTREGP (RADEON_FP_GEN_CNTL, 0, ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN));
2234 } else if (sd->Card.MonType1 == MT_LCD) {
2235 unsigned long tmpPixclksCntl = RADEONINPLL(sd, RADEON_PIXCLKS_CNTL);
2236
2237 if (sd->Card.IsMobility || sd->Card.IsIGP) {
2238 /* Asic bug, when turning off LVDS_ON, we have to make sure
2239 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
2240 */
2241 OUTPLLP(sd, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
2242 }
2243
2244 OUTREGP (RADEON_LVDS_GEN_CNTL, 0,
2245 ~(RADEON_LVDS_BLON | RADEON_LVDS_ON));
2246
2247 if (sd->Card.IsMobility || sd->Card.IsIGP) {
2248 OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
2249 }
2250 } else if (sd->Card.MonType1 == MT_CRT) {
2251 if (sd->Card.HasSecondary) {
2252 RADEONDacPowerSet(sd, FALSE, sd->Card.ReversedDAC);
2253 } else {
2254 /* single CRT, turning both DACs off, we don't really know
2255 * which DAC is actually connected.
2256 */
2257 RADEONDacPowerSet(sd, FALSE, TRUE);
2258 if (sd->Card.HasCRTC2) /* don't apply this to old radeon (singel CRTC) card */
2259 RADEONDacPowerSet(sd, FALSE, FALSE);
2260 }
2261 }
2262 }
2263 }
2264 }
2265
2266 BOOL RADEONInit(struct ati_staticdata *sd)
2267 {
2268 sd->Card.IsSecondary = FALSE;
2269
2270 // RADEONPreInt10Save(sd, &int10_save);
2271 // RADEONPostInt10Check(sd, int10_save);
2272
2273 D(bug("[ATI] Radeon init\n"));
2274 #if AROS_BIG_ENDIAN
2275 D(bug("[ATI] BigEndian machine\n"));
2276 #endif
2277
2278 sd->Card.HasCRTC2 = TRUE;
2279 sd->Card.IsMobility = FALSE;
2280 sd->Card.IsIGP = FALSE;
2281 sd->Card.IsDellServer = FALSE;
2282 sd->Card.HasSingleDAC = FALSE;
2283
2284 sd->Card.PanelPwrDly = 500;
2285
2286 sd->Card.ChipErrata = 0;
2287
2288 D(bug("[ATI] flags:"));
2289
2290 switch (sd->Card.ProductID)
2291 {
2292 case 0x4c59:
2293 case 0x4c5a:
2294 case 0x4c57:
2295 case 0x4c58:
2296 case 0x4c64:
2297 case 0x4c66:
2298 case 0x4c67:
2299 case 0x5c61:
2300 case 0x5c63:
2301 case 0x4e50:
2302 case 0x4e51:
2303 case 0x4e52:
2304 case 0x4e53:
2305 case 0x4e54:
2306 case 0x4e56:
2307 case 0x3150:
2308 case 0x3154:
2309 case 0x5460:
2310 case 0x5464:
2311 case 0x4a4e:
2312 sd->Card.IsMobility = TRUE;
2313 D(bug(" IsMobility\n"));
2314 break;
2315
2316 case 0x4336:
2317 case 0x4337:
2318 sd->Card.IsMobility = TRUE;
2319 D(bug(" IsMobility\n"));
2320 case 0x4136:
2321 case 0x4237:
2322 sd->Card.IsIGP = TRUE;
2323 D(bug(" IsIGP\n"));
2324 break;
2325
2326 case 0x5835:
2327 case 0x7835:
2328 sd->Card.IsMobility = TRUE;
2329 D(bug(" IsMobility\n"));
2330 case 0x5834:
2331 case 0x7834:
2332 sd->Card.IsIGP = TRUE;
2333 sd->Card.HasSingleDAC = TRUE;
2334 D(bug(" IsIGP HasSingleDAC\n"));
2335 break;
2336
2337 default:
2338 sd->Card.HasCRTC2 = FALSE;
2339 }
2340 D(bug("\n"));
2341
2342 if (sd->Card.Type == R300 &&
2343 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
2344 == RADEON_CFG_ATI_REV_A11)
2345 sd->Card.ChipErrata |= CHIP_ERRATA_R300_CG;
2346
2347 if (sd->Card.Type == RV200 ||
2348 sd->Card.Type == RS200)
2349 sd->Card.ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS;
2350
2351 if (sd->Card.Type == RV100 ||
2352 sd->Card.Type == RS100 ||
2353 sd->Card.Type == RS200)
2354 sd->Card.ChipErrata |= CHIP_ERRATA_PLL_DELAY;
2355
2356 if ((sd->Card.Type == RS100) ||
2357 (sd->Card.Type == RS200) ||
2358 (sd->Card.Type == RS300)) {
2359 ULONG tom = INREG(RADEON_NB_TOM);
2360
2361 sd->Card.FbUsableSize = (((tom >> 16) -
2362 (tom & 0xffff) + 1) << 6) * 1024;
2363
2364 OUTREG(RADEON_CONFIG_MEMSIZE, sd->Card.FbUsableSize);
2365 } else {
2366 /* There are different HDP mapping schemes depending on single/multi funciton setting,
2367 * chip family, HDP mode, and the generation of HDP mapping scheme.
2368 * To make things simple, we only allow maximum 128M addressable FB. Anything more than
2369 * 128M is configured as invisible FB to CPU that can only be accessed from chip side.
2370 */
2371 sd->Card.FbUsableSize = INREG(RADEON_CONFIG_MEMSIZE);
2372 if (sd->Card.FbUsableSize > 128*1024*1024) sd->Card.FbUsableSize = 128*1024*1024;
2373 if ((sd->Card.Type == RV350) ||
2374 (sd->Card.Type == RV380) ||
2375 (sd->Card.Type == R420)) {
2376 OUTREGP (RADEON_HOST_PATH_CNTL, (1<<23), ~(1<<23));
2377 }
2378 }
2379
2380 /* Some production boards of m6 will return 0 if it's 8 MB */
2381 if (sd->Card.FbUsableSize == 0) sd->Card.FbUsableSize = 8192*1024;
2382
2383 #if 0
2384 if (sd->Card.IsSecondary) {
2385 /* FIXME: For now, split FB into two equal sections. This should
2386 * be able to be adjusted by user with a config option. */
2387 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
2388 RADEONInfoPtr info1;
2389
2390 pScrn->videoRam /= 2;
2391 pRADEONEnt->pPrimaryScrn->videoRam = pScrn->videoRam;
2392
2393 info1 = RADEONPTR(pRADEONEnt->pPrimaryScrn);
2394 info1->FbMapSize = pScrn->videoRam * 1024;
2395 info->LinearAddr += pScrn->videoRam * 1024;
2396 info1->MergedFB = FALSE;
2397 }
2398 #endif
2399
2400 sd->Card.R300CGWorkaround = (sd->Card.Type == R300 &&
2401 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
2402 == RADEON_CFG_ATI_REV_A11);
2403
2404 D(bug("[ATI] R300CGWorkaroung = %s\n", sd->Card.R300CGWorkaround? "Yes":"No"));
2405
2406 sd->Card.MemCntl = INREG(RADEON_SDRAM_MODE_REG);
2407 sd->Card.BusCntl = INREG(RADEON_BUS_CNTL);
2408
2409 sd->Card.DDCReg = RADEON_GPIO_DVI_DDC;
2410
2411 RADEONGetVRamType(sd);
2412
2413 D(bug("[ATI] Video memory = %dMiB (%d bit %s SDRAM)\n", sd->Card.FbUsableSize >> 20,
2414 sd->Card.RamWidth, sd->Card.IsDDR ? "DDR":"SDR"));
2415
2416 BitmapInit(sd);
2417
2418 /* RADEONPreInitDDC */
2419 sd->Card.DDC1 = FALSE;
2420 sd->Card.DDC2 = FALSE;
2421 sd->Card.DDCBios = FALSE;
2422
2423 RADEONGetBIOSInfo(sd);
2424 RADEONQueryConnectedMonitors(sd);
2425 RADEONGetClockInfo(sd);
2426 RADEONGetPanelInfo(sd);
2427
2428 if (sd->Card.MonType1 == MT_UNKNOWN)
2429 sd->Card.MonType1 = MT_CRT;
2430
2431 return TRUE;
2432 }
2433
2434 /*
2435 Allocates some memory area on GFX card, which may be sufficient for bitmap
2436 with given size and depth. The must_have bit may be defined but doesn't
2437 have to. If it is TRUE, the allocator will do everything to get the memory -
2438 eg. it will throw other bitmaps away from it or it will shift them within
2439 GFX memory
2440 */
2441
2442 IPTR AllocBitmapArea(struct ati_staticdata *sd, ULONG width, ULONG height,
2443 ULONG bpp, BOOL must_have)
2444 {
2445 IPTR result;
2446 ULONG size = (((width * bpp + 63) & ~63) * height + 1023) & ~1023;
2447
2448 LOCK_HW
2449
2450 // Forbid();
2451 // result = (IPTR)Allocate(&sd->CardMem, size);
2452 // Permit();
2453 //
2454 // /*
2455 // If Allocate failed, make the 0xffffffff as return. If it succeeded, make
2456 // the memory pointer relative to the begin of GFX memory
2457 // */
2458 // if (result == 0) --result;
2459 // else result -= (IPTR)sd->Card.FrameBuffer;
2460
2461 //Forbid();
2462 ObtainSemaphore(&sd->CardMemLock);
2463 result = BitmapAlloc(sd, size);
2464 //Permit();
2465 ReleaseSemaphore(&sd->CardMemLock);
2466
2467 D(bug("[ATI] AllocBitmapArea(%dx%d@%d) = %p\n", width, height, bpp, result));
2468
2469 UNLOCK_HW
2470
2471 /* Generic thing. Will be extended later */
2472 return result;
2473 }
2474
2475 VOID FreeBitmapArea(struct ati_staticdata *sd, IPTR bmp, ULONG width, ULONG height, ULONG bpp)
2476 {
2477 // APTR ptr = (APTR)(bmp + sd->Card.FrameBuffer);
2478 ULONG size = (((width * bpp + 63) & ~63) * height + 1023) & ~1023;
2479
2480 LOCK_HW
2481
2482 D(bug("[ATI] FreeBitmapArea(%p,%dx%d@%d)\n",
2483 bmp, width, height, bpp));
2484
2485 // Forbid();
2486 ObtainSemaphore(&sd->CardMemLock);
2487 // Deallocate(&sd->CardMem, ptr, size);
2488 BitmapFree(sd, bmp, size);
2489 // Permit();
2490 ReleaseSemaphore(&sd->CardMemLock);
2491
2492 UNLOCK_HW
2493 }
2494
2495 VOID SetGamma(struct ati_staticdata *sd, float r, float g, float b)
2496 {
2497 int i;
2498
2499 if (sd->Card.IsSecondary)
2500 PAL_SELECT(1);
2501 else
2502 PAL_SELECT(0);
2503
2504 for (i=0; i < 256; i++)
2505 {
2506 int ri = 256.0*pow((double)i / 256.0, 1/r);
2507 int gi = 256.0*pow((double)i / 256.0, 1/g);
2508 int bi = 256.0*pow((double)i / 256.0, 1/b);
2509
2510 RADEONWaitForFifo(sd, 32);
2511 OUTPAL(i, ri, gi, bi);
2512 }
2513 }
Mirror of AROS' svn.