arch/.unmaintained/ppc-native/exec/enable.s

   1 /*
   2     Copyright © 1995-2001, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 /*****************************************************************************
   7
   8     NAME
   9
  10         AROS_LH0(void, Enable,
  11
  12     LOCATION
  13         struct ExecBase *, SysBase, 21, Exec)
  14
  15     FUNCTION
  16         This function reenables the delivery of interrupts after a call to
  17         Disable().
  18
  19     INPUTS
  20
  21     RESULT
  22
  23     NOTES
  24         This function preserves all registers.
  25
  26         This function may be used from interrupts.
  27
  28     EXAMPLE
  29
  30     BUGS
  31
  32     SEE ALSO
  33         Forbid(), Permit(), Disable()
  34
  35     INTERNALS
  36
  37     HISTORY
  38
  39 ******************************************************************************/
  40
  41         INTENA      =   0xdff09a
  42         INTEN       =   0x4000
  43         SET         =   0x8000
  44
  45         #include "machine.i"
  46
  47         .text
  48         .balign 4
  49         .globl  AROS_SLIB_ENTRY(Enable,Exec)
  50         .type   AROS_SLIB_ENTRY(Enable,Exec),@function
  51 AROS_SLIB_ENTRY(Enable,Exec):
  52         /* decrement nesting count and return if there are Disable()s left */
  53         subr
  54         push    scr
  55
  56         lbz     scr,IDNestCnt(base)
  57         subic.  scr,scr,1
  58         stw     scr,IDNestCnt(base)
  59         bge     end
  60
  61         lwz     arg0,_enab(0)
  62         jsrlvo  Supervisor,base
  63         /* we should come back here from _disab */
  64         /* enable Amiga chipset interrupts */
  65         li      scr,INTEN+SET
  66         stw     scr,INTENA
  67
  68         /* return if there are no delayed switches pending. */
  69         lwz     scr,AttnResched+1(base)
  70         cmpdi   scr,0
  71         beq     end
  72
  73         /* if TDNestCnt is not -1 taskswitches are still forbidden */
  74         lwz     scr,TDNestCnt(base)
  75         cmpdi   scr,0
  76         beq     end
  77
  78         /* Unset delayed switch bit and do the delayed switch */
  79         lwz     scr,0x12b(base)
  80         andi.   scr,scr,0x7f
  81         sth     scr,0x12b(base)
  82         jsrlvo  Switch,base
  83
  84         /* all done. */
  85 end:    pop     scr
  86         rts
  87
  88 _enab:
  89         mfmsr   p1
  90         ori     p1,p1,0x8000
  91         isync
  92         mtmsr
  93         sync
  94         rfi